2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 11
30 struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle;
36 /* FIFO control regs */
39 /* DMA command buffer */
43 drm_handle_t notifier;
47 struct drm_nouveau_channel_free {
51 struct drm_nouveau_grobj_alloc {
57 #define NOUVEAU_MEM_ACCESS_RO 1
58 #define NOUVEAU_MEM_ACCESS_WO 2
59 #define NOUVEAU_MEM_ACCESS_RW 3
60 struct drm_nouveau_notifierobj_alloc {
68 struct drm_nouveau_gpuobj_free {
73 /* This is needed to avoid a race condition.
74 * Otherwise you may be writing in the fetch area.
75 * Is this large enough, as it's only 32 bytes, and the maximum fetch size is 256 bytes?
77 #define NOUVEAU_DMA_SKIPS 8
79 #define NOUVEAU_MEM_FB 0x00000001
80 #define NOUVEAU_MEM_AGP 0x00000002
81 #define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004
82 #define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008
83 #define NOUVEAU_MEM_PCI 0x00000010
84 #define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020
85 #define NOUVEAU_MEM_PINNED 0x00000040
86 #define NOUVEAU_MEM_USER_BACKED 0x00000080
87 #define NOUVEAU_MEM_MAPPED 0x00000100
88 #define NOUVEAU_MEM_TILE 0x00000200
89 #define NOUVEAU_MEM_TILE_ZETA 0x00000400
90 #define NOUVEAU_MEM_INSTANCE 0x01000000 /* internal */
91 #define NOUVEAU_MEM_NOTIFIER 0x02000000 /* internal */
92 #define NOUVEAU_MEM_NOVM 0x04000000 /* internal */
93 #define NOUVEAU_MEM_USER 0x08000000 /* internal */
94 #define NOUVEAU_MEM_INTERNAL (NOUVEAU_MEM_INSTANCE | \
95 NOUVEAU_MEM_NOTIFIER | \
99 struct drm_nouveau_mem_alloc {
102 uint64_t size; // in bytes
104 drm_handle_t map_handle;
107 struct drm_nouveau_mem_free {
112 struct drm_nouveau_mem_tile {
119 /* FIXME : maybe unify {GET,SET}PARAMs */
120 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
121 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
122 #define NOUVEAU_GETPARAM_BUS_TYPE 5
123 #define NOUVEAU_GETPARAM_FB_PHYSICAL 6
124 #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
125 #define NOUVEAU_GETPARAM_FB_SIZE 8
126 #define NOUVEAU_GETPARAM_AGP_SIZE 9
127 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
128 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
129 struct drm_nouveau_getparam {
134 #define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
135 #define NOUVEAU_SETPARAM_CMDBUF_SIZE 2
136 struct drm_nouveau_setparam {
141 enum nouveau_card_type {
156 enum nouveau_bus_type {
162 #define NOUVEAU_MAX_SAREA_CLIPRECTS 16
164 struct drm_nouveau_sarea {
166 struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
170 #define DRM_NOUVEAU_CARD_INIT 0x00
171 #define DRM_NOUVEAU_GETPARAM 0x01
172 #define DRM_NOUVEAU_SETPARAM 0x02
173 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
174 #define DRM_NOUVEAU_CHANNEL_FREE 0x04
175 #define DRM_NOUVEAU_GROBJ_ALLOC 0x05
176 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
177 #define DRM_NOUVEAU_GPUOBJ_FREE 0x07
178 #define DRM_NOUVEAU_MEM_ALLOC 0x08
179 #define DRM_NOUVEAU_MEM_FREE 0x09
180 #define DRM_NOUVEAU_MEM_TILE 0x0a
182 #endif /* __NOUVEAU_DRM_H__ */