shared-core/mga_state.c

   1 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
   2  * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Jeff Hartmann <jhartmann@valinux.com>
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *
  31  * Rewritten by:
  32  *    Gareth Hughes <gareth@valinux.com>
  33  */
  34
  35 #include "drmP.h"
  36 #include "drm.h"
  37 #include "mga_drm.h"
  38 #include "mga_drv.h"
  39
  40 /* ================================================================
  41  * DMA hardware state programming functions
  42  */
  43
  44 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv,
  45                                drm_clip_rect_t * box)
  46 {
  47         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  48         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  49         unsigned int pitch = dev_priv->front_pitch;
  50         DMA_LOCALS;
  51
  52         BEGIN_DMA(2);
  53
  54         /* Force reset of DWGCTL on G400 (eliminates clip disable bit).
  55          */
  56         if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
  57                 DMA_BLOCK(MGA_DWGCTL, ctx->dwgctl,
  58                           MGA_LEN + MGA_EXEC, 0x80000000,
  59                           MGA_DWGCTL, ctx->dwgctl,
  60                           MGA_LEN + MGA_EXEC, 0x80000000);
  61         }
  62         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
  63                   MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1,
  64                   MGA_YTOP, box->y1 * pitch,
  65                   MGA_YBOT, (box->y2 - 1) * pitch);
  66
  67         ADVANCE_DMA();
  68 }
  69
  70 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv)
  71 {
  72         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  73         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
  74         DMA_LOCALS;
  75
  76         BEGIN_DMA(3);
  77
  78         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
  79                   MGA_MACCESS, ctx->maccess,
  80                   MGA_PLNWT, ctx->plnwt,
  81                   MGA_DWGCTL, ctx->dwgctl);
  82
  83         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
  84                   MGA_FOGCOL, ctx->fogcolor,
  85                   MGA_WFLAG, ctx->wflag,
  86                   MGA_ZORG, dev_priv->depth_offset);
  87
  88         DMA_BLOCK(MGA_FCOL, ctx->fcol,
  89                   MGA_DMAPAD, 0x00000000,
  90                   MGA_DMAPAD, 0x00000000,
  91                   MGA_DMAPAD, 0x00000000);
  92
  93         ADVANCE_DMA();
  94 }
  95
  96 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv)
  97 {
  98         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  99         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 100         DMA_LOCALS;
 101
 102         BEGIN_DMA(4);
 103
 104         DMA_BLOCK(MGA_DSTORG, ctx->dstorg,
 105                   MGA_MACCESS, ctx->maccess,
 106                   MGA_PLNWT, ctx->plnwt,
 107                   MGA_DWGCTL, ctx->dwgctl);
 108
 109         DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl,
 110                   MGA_FOGCOL, ctx->fogcolor,
 111                   MGA_WFLAG, ctx->wflag,
 112                   MGA_ZORG, dev_priv->depth_offset);
 113
 114         DMA_BLOCK(MGA_WFLAG1, ctx->wflag,
 115                   MGA_TDUALSTAGE0, ctx->tdualstage0,
 116                   MGA_TDUALSTAGE1, ctx->tdualstage1,
 117                   MGA_FCOL, ctx->fcol);
 118
 119         DMA_BLOCK(MGA_STENCIL, ctx->stencil,
 120                   MGA_STENCILCTL, ctx->stencilctl,
 121                   MGA_DMAPAD, 0x00000000,
 122                   MGA_DMAPAD, 0x00000000);
 123
 124         ADVANCE_DMA();
 125 }
 126
 127 static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv)
 128 {
 129         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 130         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 131         DMA_LOCALS;
 132
 133         BEGIN_DMA(4);
 134
 135         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2,
 136                   MGA_TEXCTL, tex->texctl,
 137                   MGA_TEXFILTER, tex->texfilter,
 138                   MGA_TEXBORDERCOL, tex->texbordercol);
 139
 140         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 141                   MGA_TEXORG1, tex->texorg1,
 142                   MGA_TEXORG2, tex->texorg2,
 143                   MGA_TEXORG3, tex->texorg3);
 144
 145         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 146                   MGA_TEXWIDTH, tex->texwidth,
 147                   MGA_TEXHEIGHT, tex->texheight,
 148                   MGA_WR24, tex->texwidth);
 149
 150         DMA_BLOCK(MGA_WR34, tex->texheight,
 151                   MGA_TEXTRANS, 0x0000ffff,
 152                   MGA_TEXTRANSHIGH, 0x0000ffff,
 153                   MGA_DMAPAD, 0x00000000);
 154
 155         ADVANCE_DMA();
 156 }
 157
 158 static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv)
 159 {
 160         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 161         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
 162         DMA_LOCALS;
 163
 164 /*      printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
 165 /*             tex->texctl, tex->texctl2); */
 166
 167         BEGIN_DMA(6);
 168
 169         DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC,
 170                   MGA_TEXCTL, tex->texctl,
 171                   MGA_TEXFILTER, tex->texfilter,
 172                   MGA_TEXBORDERCOL, tex->texbordercol);
 173
 174         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 175                   MGA_TEXORG1, tex->texorg1,
 176                   MGA_TEXORG2, tex->texorg2,
 177                   MGA_TEXORG3, tex->texorg3);
 178
 179         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 180                   MGA_TEXWIDTH, tex->texwidth,
 181                   MGA_TEXHEIGHT, tex->texheight,
 182                   MGA_WR49, 0x00000000);
 183
 184         DMA_BLOCK(MGA_WR57, 0x00000000,
 185                   MGA_WR53, 0x00000000,
 186                   MGA_WR61, 0x00000000,
 187                   MGA_WR52, MGA_G400_WR_MAGIC);
 188
 189         DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC,
 190                   MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC,
 191                   MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC,
 192                   MGA_DMAPAD, 0x00000000);
 193
 194         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 195                   MGA_DMAPAD, 0x00000000,
 196                   MGA_TEXTRANS, 0x0000ffff,
 197                   MGA_TEXTRANSHIGH, 0x0000ffff);
 198
 199         ADVANCE_DMA();
 200 }
 201
 202 static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv)
 203 {
 204         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 205         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
 206         DMA_LOCALS;
 207
 208 /*      printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
 209 /*             tex->texctl, tex->texctl2); */
 210
 211         BEGIN_DMA(5);
 212
 213         DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 |
 214                                 MGA_MAP1_ENABLE |
 215                                 MGA_G400_TC2_MAGIC),
 216                   MGA_TEXCTL, tex->texctl,
 217                   MGA_TEXFILTER, tex->texfilter,
 218                   MGA_TEXBORDERCOL, tex->texbordercol);
 219
 220         DMA_BLOCK(MGA_TEXORG, tex->texorg,
 221                   MGA_TEXORG1, tex->texorg1,
 222                   MGA_TEXORG2, tex->texorg2,
 223                   MGA_TEXORG3, tex->texorg3);
 224
 225         DMA_BLOCK(MGA_TEXORG4, tex->texorg4,
 226                   MGA_TEXWIDTH, tex->texwidth,
 227                   MGA_TEXHEIGHT, tex->texheight,
 228                   MGA_WR49, 0x00000000);
 229
 230         DMA_BLOCK(MGA_WR57, 0x00000000,
 231                   MGA_WR53, 0x00000000,
 232                   MGA_WR61, 0x00000000,
 233                   MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC);
 234
 235         DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC,
 236                   MGA_TEXTRANS, 0x0000ffff,
 237                   MGA_TEXTRANSHIGH, 0x0000ffff,
 238                   MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC);
 239
 240         ADVANCE_DMA();
 241 }
 242
 243 static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv)
 244 {
 245         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 246         unsigned int pipe = sarea_priv->warp_pipe;
 247         DMA_LOCALS;
 248
 249         BEGIN_DMA(3);
 250
 251         DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND,
 252                   MGA_WVRTXSZ, 0x00000007,
 253                   MGA_WFLAG, 0x00000000,
 254                   MGA_WR24, 0x00000000);
 255
 256         DMA_BLOCK(MGA_WR25, 0x00000100,
 257                   MGA_WR34, 0x00000000,
 258                   MGA_WR42, 0x0000ffff,
 259                   MGA_WR60, 0x0000ffff);
 260
 261         /* Padding required to to hardware bug.
 262          */
 263         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 264                   MGA_DMAPAD, 0xffffffff,
 265                   MGA_DMAPAD, 0xffffffff,
 266                   MGA_WIADDR, (dev_priv->warp_pipe_phys[pipe] |
 267                                MGA_WMODE_START | MGA_WAGP_ENABLE));
 268
 269         ADVANCE_DMA();
 270 }
 271
 272 static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv)
 273 {
 274         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 275         unsigned int pipe = sarea_priv->warp_pipe;
 276         DMA_LOCALS;
 277
 278 /*      printk("mga_g400_emit_pipe %x\n", pipe); */
 279
 280         BEGIN_DMA(10);
 281
 282         DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND,
 283                   MGA_DMAPAD, 0x00000000,
 284                   MGA_DMAPAD, 0x00000000,
 285                   MGA_DMAPAD, 0x00000000);
 286
 287         if (pipe & MGA_T2) {
 288                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09,
 289                           MGA_DMAPAD, 0x00000000,
 290                           MGA_DMAPAD, 0x00000000,
 291                           MGA_DMAPAD, 0x00000000);
 292
 293                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 294                           MGA_WACCEPTSEQ, 0x00000000,
 295                           MGA_WACCEPTSEQ, 0x00000000,
 296                           MGA_WACCEPTSEQ, 0x1e000000);
 297         } else {
 298                 if (dev_priv->warp_pipe & MGA_T2) {
 299                         /* Flush the WARP pipe */
 300                         DMA_BLOCK(MGA_YDST, 0x00000000,
 301                                   MGA_FXLEFT, 0x00000000,
 302                                   MGA_FXRIGHT, 0x00000001,
 303                                   MGA_DWGCTL, MGA_DWGCTL_FLUSH);
 304
 305                         DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001,
 306                                   MGA_DWGSYNC, 0x00007000,
 307                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 308                                   MGA_LEN + MGA_EXEC, 0x00000000);
 309
 310                         DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX |
 311                                                 MGA_G400_TC2_MAGIC),
 312                                   MGA_LEN + MGA_EXEC, 0x00000000,
 313                                   MGA_TEXCTL2, MGA_G400_TC2_MAGIC,
 314                                   MGA_DMAPAD, 0x00000000);
 315                 }
 316
 317                 DMA_BLOCK(MGA_WVRTXSZ, 0x00001807,
 318                           MGA_DMAPAD, 0x00000000,
 319                           MGA_DMAPAD, 0x00000000,
 320                           MGA_DMAPAD, 0x00000000);
 321
 322                 DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000,
 323                           MGA_WACCEPTSEQ, 0x00000000,
 324                           MGA_WACCEPTSEQ, 0x00000000,
 325                           MGA_WACCEPTSEQ, 0x18000000);
 326         }
 327
 328         DMA_BLOCK(MGA_WFLAG, 0x00000000,
 329                   MGA_WFLAG1, 0x00000000,
 330                   MGA_WR56, MGA_G400_WR56_MAGIC,
 331                   MGA_DMAPAD, 0x00000000);
 332
 333         DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0              */
 334                   MGA_WR57, 0x00000000, /* tex0              */
 335                   MGA_WR53, 0x00000000, /* tex1              */
 336                   MGA_WR61, 0x00000000);        /* tex1              */
 337
 338         DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC,  /* tex0 width        */
 339                   MGA_WR62, MGA_G400_WR_MAGIC,  /* tex0 height       */
 340                   MGA_WR52, MGA_G400_WR_MAGIC,  /* tex1 width        */
 341                   MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height       */
 342
 343         /* Padding required to to hardware bug */
 344         DMA_BLOCK(MGA_DMAPAD, 0xffffffff,
 345                   MGA_DMAPAD, 0xffffffff,
 346                   MGA_DMAPAD, 0xffffffff,
 347                   MGA_WIADDR2, (dev_priv->warp_pipe_phys[pipe] |
 348                                 MGA_WMODE_START | MGA_WAGP_ENABLE));
 349
 350         ADVANCE_DMA();
 351 }
 352
 353 static void mga_g200_emit_state(drm_mga_private_t * dev_priv)
 354 {
 355         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 356         unsigned int dirty = sarea_priv->dirty;
 357
 358         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 359                 mga_g200_emit_pipe(dev_priv);
 360                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 361         }
 362
 363         if (dirty & MGA_UPLOAD_CONTEXT) {
 364                 mga_g200_emit_context(dev_priv);
 365                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 366         }
 367
 368         if (dirty & MGA_UPLOAD_TEX0) {
 369                 mga_g200_emit_tex0(dev_priv);
 370                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 371         }
 372 }
 373
 374 static void mga_g400_emit_state(drm_mga_private_t * dev_priv)
 375 {
 376         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 377         unsigned int dirty = sarea_priv->dirty;
 378         int multitex = sarea_priv->warp_pipe & MGA_T2;
 379
 380         if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
 381                 mga_g400_emit_pipe(dev_priv);
 382                 dev_priv->warp_pipe = sarea_priv->warp_pipe;
 383         }
 384
 385         if (dirty & MGA_UPLOAD_CONTEXT) {
 386                 mga_g400_emit_context(dev_priv);
 387                 sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
 388         }
 389
 390         if (dirty & MGA_UPLOAD_TEX0) {
 391                 mga_g400_emit_tex0(dev_priv);
 392                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
 393         }
 394
 395         if ((dirty & MGA_UPLOAD_TEX1) && multitex) {
 396                 mga_g400_emit_tex1(dev_priv);
 397                 sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
 398         }
 399 }
 400
 401 /* ================================================================
 402  * SAREA state verification
 403  */
 404
 405 /* Disallow all write destinations except the front and backbuffer.
 406  */
 407 static int mga_verify_context(drm_mga_private_t * dev_priv)
 408 {
 409         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 410         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 411
 412         if (ctx->dstorg != dev_priv->front_offset &&
 413             ctx->dstorg != dev_priv->back_offset) {
 414                 DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n",
 415                           ctx->dstorg, dev_priv->front_offset,
 416                           dev_priv->back_offset);
 417                 ctx->dstorg = 0;
 418                 return DRM_ERR(EINVAL);
 419         }
 420
 421         return 0;
 422 }
 423
 424 /* Disallow texture reads from PCI space.
 425  */
 426 static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit)
 427 {
 428         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 429         drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
 430         unsigned int org;
 431
 432         org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
 433
 434         if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) {
 435                 DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit);
 436                 tex->texorg = 0;
 437                 return DRM_ERR(EINVAL);
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int mga_verify_state(drm_mga_private_t * dev_priv)
 444 {
 445         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 446         unsigned int dirty = sarea_priv->dirty;
 447         int ret = 0;
 448
 449         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 450                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 451
 452         if (dirty & MGA_UPLOAD_CONTEXT)
 453                 ret |= mga_verify_context(dev_priv);
 454
 455         if (dirty & MGA_UPLOAD_TEX0)
 456                 ret |= mga_verify_tex(dev_priv, 0);
 457
 458         if (dev_priv->chipset == MGA_CARD_TYPE_G400) {
 459                 if (dirty & MGA_UPLOAD_TEX1)
 460                         ret |= mga_verify_tex(dev_priv, 1);
 461
 462                 if (dirty & MGA_UPLOAD_PIPE)
 463                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
 464         } else {
 465                 if (dirty & MGA_UPLOAD_PIPE)
 466                         ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
 467         }
 468
 469         return (ret == 0);
 470 }
 471
 472 static int mga_verify_iload(drm_mga_private_t * dev_priv,
 473                             unsigned int dstorg, unsigned int length)
 474 {
 475         if (dstorg < dev_priv->texture_offset ||
 476             dstorg + length > (dev_priv->texture_offset +
 477                                dev_priv->texture_size)) {
 478                 DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg);
 479                 return DRM_ERR(EINVAL);
 480         }
 481
 482         if (length & MGA_ILOAD_MASK) {
 483                 DRM_ERROR("*** bad iload length: 0x%x\n",
 484                           length & MGA_ILOAD_MASK);
 485                 return DRM_ERR(EINVAL);
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int mga_verify_blit(drm_mga_private_t * dev_priv,
 492                            unsigned int srcorg, unsigned int dstorg)
 493 {
 494         if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
 495             (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) {
 496                 DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg);
 497                 return DRM_ERR(EINVAL);
 498         }
 499         return 0;
 500 }
 501
 502 /* ================================================================
 503  *
 504  */
 505
 506 static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear)
 507 {
 508         drm_mga_private_t *dev_priv = dev->dev_private;
 509         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 510         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 511         drm_clip_rect_t *pbox = sarea_priv->boxes;
 512         int nbox = sarea_priv->nbox;
 513         int i;
 514         DMA_LOCALS;
 515         DRM_DEBUG("\n");
 516
 517         BEGIN_DMA(1);
 518
 519         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 520                   MGA_DMAPAD, 0x00000000,
 521                   MGA_DWGSYNC, 0x00007100,
 522                   MGA_DWGSYNC, 0x00007000);
 523
 524         ADVANCE_DMA();
 525
 526         for (i = 0; i < nbox; i++) {
 527                 drm_clip_rect_t *box = &pbox[i];
 528                 u32 height = box->y2 - box->y1;
 529
 530                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 531                           box->x1, box->y1, box->x2, box->y2);
 532
 533                 if (clear->flags & MGA_FRONT) {
 534                         BEGIN_DMA(2);
 535
 536                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 537                                   MGA_PLNWT, clear->color_mask,
 538                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 539                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 540
 541                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 542                                   MGA_FCOL, clear->clear_color,
 543                                   MGA_DSTORG, dev_priv->front_offset,
 544                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 545
 546                         ADVANCE_DMA();
 547                 }
 548
 549                 if (clear->flags & MGA_BACK) {
 550                         BEGIN_DMA(2);
 551
 552                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 553                                   MGA_PLNWT, clear->color_mask,
 554                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 555                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 556
 557                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 558                                   MGA_FCOL, clear->clear_color,
 559                                   MGA_DSTORG, dev_priv->back_offset,
 560                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 561
 562                         ADVANCE_DMA();
 563                 }
 564
 565                 if (clear->flags & MGA_DEPTH) {
 566                         BEGIN_DMA(2);
 567
 568                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 569                                   MGA_PLNWT, clear->depth_mask,
 570                                   MGA_YDSTLEN, (box->y1 << 16) | height,
 571                                   MGA_FXBNDRY, (box->x2 << 16) | box->x1);
 572
 573                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 574                                   MGA_FCOL, clear->clear_depth,
 575                                   MGA_DSTORG, dev_priv->depth_offset,
 576                                   MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd);
 577
 578                         ADVANCE_DMA();
 579                 }
 580
 581         }
 582
 583         BEGIN_DMA(1);
 584
 585         /* Force reset of DWGCTL */
 586         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 587                   MGA_DMAPAD, 0x00000000,
 588                   MGA_PLNWT, ctx->plnwt,
 589                   MGA_DWGCTL, ctx->dwgctl);
 590
 591         ADVANCE_DMA();
 592
 593         FLUSH_DMA();
 594 }
 595
 596 static void mga_dma_dispatch_swap(drm_device_t * dev)
 597 {
 598         drm_mga_private_t *dev_priv = dev->dev_private;
 599         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 600         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 601         drm_clip_rect_t *pbox = sarea_priv->boxes;
 602         int nbox = sarea_priv->nbox;
 603         int i;
 604         DMA_LOCALS;
 605         DRM_DEBUG("\n");
 606
 607         sarea_priv->last_frame.head = dev_priv->prim.tail;
 608         sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
 609
 610         BEGIN_DMA(4 + nbox);
 611
 612         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 613                   MGA_DMAPAD, 0x00000000,
 614                   MGA_DWGSYNC, 0x00007100,
 615                   MGA_DWGSYNC, 0x00007000);
 616
 617         DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset,
 618                   MGA_MACCESS, dev_priv->maccess,
 619                   MGA_SRCORG, dev_priv->back_offset,
 620                   MGA_AR5, dev_priv->front_pitch);
 621
 622         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 623                   MGA_DMAPAD, 0x00000000,
 624                   MGA_PLNWT, 0xffffffff,
 625                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 626
 627         for (i = 0; i < nbox; i++) {
 628                 drm_clip_rect_t *box = &pbox[i];
 629                 u32 height = box->y2 - box->y1;
 630                 u32 start = box->y1 * dev_priv->front_pitch;
 631
 632                 DRM_DEBUG("   from=%d,%d to=%d,%d\n",
 633                           box->x1, box->y1, box->x2, box->y2);
 634
 635                 DMA_BLOCK(MGA_AR0, start + box->x2 - 1,
 636                           MGA_AR3, start + box->x1,
 637                           MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1,
 638                           MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height);
 639         }
 640
 641         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 642                   MGA_PLNWT, ctx->plnwt,
 643                   MGA_SRCORG, dev_priv->front_offset,
 644                   MGA_DWGCTL, ctx->dwgctl);
 645
 646         ADVANCE_DMA();
 647
 648         FLUSH_DMA();
 649
 650         DRM_DEBUG("%s... done.\n", __FUNCTION__);
 651 }
 652
 653 static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
 654 {
 655         drm_mga_private_t *dev_priv = dev->dev_private;
 656         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 657         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 658         u32 address = (u32) buf->bus_address;
 659         u32 length = (u32) buf->used;
 660         int i = 0;
 661         DMA_LOCALS;
 662         DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used);
 663
 664         if (buf->used) {
 665                 buf_priv->dispatched = 1;
 666
 667                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 668
 669                 do {
 670                         if (i < sarea_priv->nbox) {
 671                                 mga_emit_clip_rect(dev_priv,
 672                                                    &sarea_priv->boxes[i]);
 673                         }
 674
 675                         BEGIN_DMA(1);
 676
 677                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 678                                   MGA_DMAPAD, 0x00000000,
 679                                   MGA_SECADDRESS, (address |
 680                                                    MGA_DMA_VERTEX),
 681                                   MGA_SECEND, ((address + length) |
 682                                                MGA_PAGPXFER));
 683
 684                         ADVANCE_DMA();
 685                 } while (++i < sarea_priv->nbox);
 686         }
 687
 688         if (buf_priv->discard) {
 689                 AGE_BUFFER(buf_priv);
 690                 buf->pending = 0;
 691                 buf->used = 0;
 692                 buf_priv->dispatched = 0;
 693
 694                 mga_freelist_put(dev, buf);
 695         }
 696
 697         FLUSH_DMA();
 698 }
 699
 700 static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf,
 701                                      unsigned int start, unsigned int end)
 702 {
 703         drm_mga_private_t *dev_priv = dev->dev_private;
 704         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 705         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 706         u32 address = (u32) buf->bus_address;
 707         int i = 0;
 708         DMA_LOCALS;
 709         DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end);
 710
 711         if (start != end) {
 712                 buf_priv->dispatched = 1;
 713
 714                 MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
 715
 716                 do {
 717                         if (i < sarea_priv->nbox) {
 718                                 mga_emit_clip_rect(dev_priv,
 719                                                    &sarea_priv->boxes[i]);
 720                         }
 721
 722                         BEGIN_DMA(1);
 723
 724                         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 725                                   MGA_DMAPAD, 0x00000000,
 726                                   MGA_SETUPADDRESS, address + start,
 727                                   MGA_SETUPEND, ((address + end) |
 728                                                  MGA_PAGPXFER));
 729
 730                         ADVANCE_DMA();
 731                 } while (++i < sarea_priv->nbox);
 732         }
 733
 734         if (buf_priv->discard) {
 735                 AGE_BUFFER(buf_priv);
 736                 buf->pending = 0;
 737                 buf->used = 0;
 738                 buf_priv->dispatched = 0;
 739
 740                 mga_freelist_put(dev, buf);
 741         }
 742
 743         FLUSH_DMA();
 744 }
 745
 746 /* This copies a 64 byte aligned agp region to the frambuffer with a
 747  * standard blit, the ioctl needs to do checking.
 748  */
 749 static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf,
 750                                    unsigned int dstorg, unsigned int length)
 751 {
 752         drm_mga_private_t *dev_priv = dev->dev_private;
 753         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 754         drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
 755         u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
 756         u32 y2;
 757         DMA_LOCALS;
 758         DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used);
 759
 760         y2 = length / 64;
 761
 762         BEGIN_DMA(5);
 763
 764         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 765                   MGA_DMAPAD, 0x00000000,
 766                   MGA_DWGSYNC, 0x00007100,
 767                   MGA_DWGSYNC, 0x00007000);
 768
 769         DMA_BLOCK(MGA_DSTORG, dstorg,
 770                   MGA_MACCESS, 0x00000000,
 771                   MGA_SRCORG, srcorg,
 772                   MGA_AR5, 64);
 773
 774         DMA_BLOCK(MGA_PITCH, 64,
 775                   MGA_PLNWT, 0xffffffff,
 776                   MGA_DMAPAD, 0x00000000,
 777                   MGA_DWGCTL, MGA_DWGCTL_COPY);
 778
 779         DMA_BLOCK(MGA_AR0, 63,
 780                   MGA_AR3, 0,
 781                   MGA_FXBNDRY, (63 << 16) | 0,
 782                   MGA_YDSTLEN + MGA_EXEC, y2);
 783
 784         DMA_BLOCK(MGA_PLNWT, ctx->plnwt,
 785                   MGA_SRCORG, dev_priv->front_offset,
 786                   MGA_PITCH, dev_priv->front_pitch,
 787                   MGA_DWGSYNC, 0x00007000);
 788
 789         ADVANCE_DMA();
 790
 791         AGE_BUFFER(buf_priv);
 792
 793         buf->pending = 0;
 794         buf->used = 0;
 795         buf_priv->dispatched = 0;
 796
 797         mga_freelist_put(dev, buf);
 798
 799         FLUSH_DMA();
 800 }
 801
 802 static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit)
 803 {
 804         drm_mga_private_t *dev_priv = dev->dev_private;
 805         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 806         drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
 807         drm_clip_rect_t *pbox = sarea_priv->boxes;
 808         int nbox = sarea_priv->nbox;
 809         u32 scandir = 0, i;
 810         DMA_LOCALS;
 811         DRM_DEBUG("\n");
 812
 813         BEGIN_DMA(4 + nbox);
 814
 815         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 816                   MGA_DMAPAD, 0x00000000,
 817                   MGA_DWGSYNC, 0x00007100,
 818                   MGA_DWGSYNC, 0x00007000);
 819
 820         DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY,
 821                   MGA_PLNWT, blit->planemask,
 822                   MGA_SRCORG, blit->srcorg,
 823                   MGA_DSTORG, blit->dstorg);
 824
 825         DMA_BLOCK(MGA_SGN, scandir,
 826                   MGA_MACCESS, dev_priv->maccess,
 827                   MGA_AR5, blit->ydir * blit->src_pitch,
 828                   MGA_PITCH, blit->dst_pitch);
 829
 830         for (i = 0; i < nbox; i++) {
 831                 int srcx = pbox[i].x1 + blit->delta_sx;
 832                 int srcy = pbox[i].y1 + blit->delta_sy;
 833                 int dstx = pbox[i].x1 + blit->delta_dx;
 834                 int dsty = pbox[i].y1 + blit->delta_dy;
 835                 int h = pbox[i].y2 - pbox[i].y1;
 836                 int w = pbox[i].x2 - pbox[i].x1 - 1;
 837                 int start;
 838
 839                 if (blit->ydir == -1) {
 840                         srcy = blit->height - srcy - 1;
 841                 }
 842
 843                 start = srcy * blit->src_pitch + srcx;
 844
 845                 DMA_BLOCK(MGA_AR0, start + w,
 846                           MGA_AR3, start,
 847                           MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff),
 848                           MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h);
 849         }
 850
 851         /* Do something to flush AGP?
 852          */
 853
 854         /* Force reset of DWGCTL */
 855         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 856                   MGA_PLNWT, ctx->plnwt,
 857                   MGA_PITCH, dev_priv->front_pitch,
 858                   MGA_DWGCTL, ctx->dwgctl);
 859
 860         ADVANCE_DMA();
 861 }
 862
 863 /* ================================================================
 864  *
 865  */
 866
 867 static int mga_dma_clear(DRM_IOCTL_ARGS)
 868 {
 869         DRM_DEVICE;
 870         drm_mga_private_t *dev_priv = dev->dev_private;
 871         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 872         drm_mga_clear_t clear;
 873
 874         LOCK_TEST_WITH_RETURN(dev, filp);
 875
 876         DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data,
 877                                  sizeof(clear));
 878
 879         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 880                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 881
 882         WRAP_TEST_WITH_RETURN(dev_priv);
 883
 884         mga_dma_dispatch_clear(dev, &clear);
 885
 886         /* Make sure we restore the 3D state next time.
 887          */
 888         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 889
 890         return 0;
 891 }
 892
 893 static int mga_dma_swap(DRM_IOCTL_ARGS)
 894 {
 895         DRM_DEVICE;
 896         drm_mga_private_t *dev_priv = dev->dev_private;
 897         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 898
 899         LOCK_TEST_WITH_RETURN(dev, filp);
 900
 901         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
 902                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
 903
 904         WRAP_TEST_WITH_RETURN(dev_priv);
 905
 906         mga_dma_dispatch_swap(dev);
 907
 908         /* Make sure we restore the 3D state next time.
 909          */
 910         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
 911
 912         return 0;
 913 }
 914
 915 static int mga_dma_vertex(DRM_IOCTL_ARGS)
 916 {
 917         DRM_DEVICE;
 918         drm_mga_private_t *dev_priv = dev->dev_private;
 919         drm_device_dma_t *dma = dev->dma;
 920         drm_buf_t *buf;
 921         drm_mga_buf_priv_t *buf_priv;
 922         drm_mga_vertex_t vertex;
 923
 924         LOCK_TEST_WITH_RETURN(dev, filp);
 925
 926         DRM_COPY_FROM_USER_IOCTL(vertex,
 927                                  (drm_mga_vertex_t __user *) data,
 928                                  sizeof(vertex));
 929
 930         if (vertex.idx < 0 || vertex.idx > dma->buf_count)
 931                 return DRM_ERR(EINVAL);
 932         buf = dma->buflist[vertex.idx];
 933         buf_priv = buf->dev_private;
 934
 935         buf->used = vertex.used;
 936         buf_priv->discard = vertex.discard;
 937
 938         if (!mga_verify_state(dev_priv)) {
 939                 if (vertex.discard) {
 940                         if (buf_priv->dispatched == 1)
 941                                 AGE_BUFFER(buf_priv);
 942                         buf_priv->dispatched = 0;
 943                         mga_freelist_put(dev, buf);
 944                 }
 945                 return DRM_ERR(EINVAL);
 946         }
 947
 948         WRAP_TEST_WITH_RETURN(dev_priv);
 949
 950         mga_dma_dispatch_vertex(dev, buf);
 951
 952         return 0;
 953 }
 954
 955 static int mga_dma_indices(DRM_IOCTL_ARGS)
 956 {
 957         DRM_DEVICE;
 958         drm_mga_private_t *dev_priv = dev->dev_private;
 959         drm_device_dma_t *dma = dev->dma;
 960         drm_buf_t *buf;
 961         drm_mga_buf_priv_t *buf_priv;
 962         drm_mga_indices_t indices;
 963
 964         LOCK_TEST_WITH_RETURN(dev, filp);
 965
 966         DRM_COPY_FROM_USER_IOCTL(indices,
 967                                  (drm_mga_indices_t __user *) data,
 968                                  sizeof(indices));
 969
 970         if (indices.idx < 0 || indices.idx > dma->buf_count)
 971                 return DRM_ERR(EINVAL);
 972
 973         buf = dma->buflist[indices.idx];
 974         buf_priv = buf->dev_private;
 975
 976         buf_priv->discard = indices.discard;
 977
 978         if (!mga_verify_state(dev_priv)) {
 979                 if (indices.discard) {
 980                         if (buf_priv->dispatched == 1)
 981                                 AGE_BUFFER(buf_priv);
 982                         buf_priv->dispatched = 0;
 983                         mga_freelist_put(dev, buf);
 984                 }
 985                 return DRM_ERR(EINVAL);
 986         }
 987
 988         WRAP_TEST_WITH_RETURN(dev_priv);
 989
 990         mga_dma_dispatch_indices(dev, buf, indices.start, indices.end);
 991
 992         return 0;
 993 }
 994
 995 static int mga_dma_iload(DRM_IOCTL_ARGS)
 996 {
 997         DRM_DEVICE;
 998         drm_device_dma_t *dma = dev->dma;
 999         drm_mga_private_t *dev_priv = dev->dev_private;
1000         drm_buf_t *buf;
1001         drm_mga_buf_priv_t *buf_priv;
1002         drm_mga_iload_t iload;
1003         DRM_DEBUG("\n");
1004
1005         LOCK_TEST_WITH_RETURN(dev, filp);
1006
1007         DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data,
1008                                  sizeof(iload));
1009
1010 #if 0
1011         if (mga_do_wait_for_idle(dev_priv) < 0) {
1012                 if (MGA_DMA_DEBUG)
1013                         DRM_INFO("%s: -EBUSY\n", __FUNCTION__);
1014                 return DRM_ERR(EBUSY);
1015         }
1016 #endif
1017         if (iload.idx < 0 || iload.idx > dma->buf_count)
1018                 return DRM_ERR(EINVAL);
1019
1020         buf = dma->buflist[iload.idx];
1021         buf_priv = buf->dev_private;
1022
1023         if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) {
1024                 mga_freelist_put(dev, buf);
1025                 return DRM_ERR(EINVAL);
1026         }
1027
1028         WRAP_TEST_WITH_RETURN(dev_priv);
1029
1030         mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length);
1031
1032         /* Make sure we restore the 3D state next time.
1033          */
1034         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1035
1036         return 0;
1037 }
1038
1039 static int mga_dma_blit(DRM_IOCTL_ARGS)
1040 {
1041         DRM_DEVICE;
1042         drm_mga_private_t *dev_priv = dev->dev_private;
1043         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
1044         drm_mga_blit_t blit;
1045         DRM_DEBUG("\n");
1046
1047         LOCK_TEST_WITH_RETURN(dev, filp);
1048
1049         DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data,
1050                                  sizeof(blit));
1051
1052         if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
1053                 sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
1054
1055         if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg))
1056                 return DRM_ERR(EINVAL);
1057
1058         WRAP_TEST_WITH_RETURN(dev_priv);
1059
1060         mga_dma_dispatch_blit(dev, &blit);
1061
1062         /* Make sure we restore the 3D state next time.
1063          */
1064         dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
1065
1066         return 0;
1067 }
1068
1069 static int mga_getparam(DRM_IOCTL_ARGS)
1070 {
1071         DRM_DEVICE;
1072         drm_mga_private_t *dev_priv = dev->dev_private;
1073         drm_mga_getparam_t param;
1074         int value;
1075
1076         if (!dev_priv) {
1077                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1078                 return DRM_ERR(EINVAL);
1079         }
1080
1081         DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data,
1082                                  sizeof(param));
1083
1084         DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1085
1086         switch (param.param) {
1087         case MGA_PARAM_IRQ_NR:
1088                 value = dev->irq;
1089                 break;
1090         default:
1091                 return DRM_ERR(EINVAL);
1092         }
1093
1094         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1095                 DRM_ERROR("copy_to_user\n");
1096                 return DRM_ERR(EFAULT);
1097         }
1098
1099         return 0;
1100 }
1101
1102 drm_ioctl_desc_t mga_ioctls[] = {
1103         [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1},
1104         [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0},
1105         [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0},
1106         [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0},
1107         [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0},
1108         [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0},
1109         [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0},
1110         [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0},
1111         [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0},
1112         [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0},
1113 };
1114
1115 int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls);