shared-core/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /**
  37  * i915_get_pipe - return the the pipe associated with a given plane
  38  * @dev: DRM device
  39  * @plane: plane to look for
  40  *
  41  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  42  * rather than a pipe number, since they may not always be equal.  This routine
  43  * maps the given @plane back to a pipe number.
  44  */
  45 static int
  46 i915_get_pipe(struct drm_device *dev, int plane)
  47 {
  48         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  49         u32 dspcntr;
  50
  51         dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
  52
  53         return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
  54 }
  55
  56 /**
  57  * i915_get_plane - return the the plane associated with a given pipe
  58  * @dev: DRM device
  59  * @pipe: pipe to look for
  60  *
  61  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  62  * rather than a plane number, since they may not always be equal.  This routine
  63  * maps the given @pipe back to a plane number.
  64  */
  65 static int
  66 i915_get_plane(struct drm_device *dev, int pipe)
  67 {
  68         if (i915_get_pipe(dev, 0) == pipe)
  69                 return 0;
  70         return 1;
  71 }
  72
  73 /**
  74  * i915_pipe_enabled - check if a pipe is enabled
  75  * @dev: DRM device
  76  * @pipe: pipe to check
  77  *
  78  * Reading certain registers when the pipe is disabled can hang the chip.
  79  * Use this routine to make sure the PLL is running and the pipe is active
  80  * before reading such registers if unsure.
  81  */
  82 static int
  83 i915_pipe_enabled(struct drm_device *dev, int pipe)
  84 {
  85         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  86         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  87
  88         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  89                 return 1;
  90
  91         return 0;
  92 }
  93
  94 /**
  95  * Emit a synchronous flip.
  96  *
  97  * This function must be called with the drawable spinlock held.
  98  */
  99 static void
 100 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
 101                          int plane)
 102 {
 103         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 104         drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
 105         u16 x1, y1, x2, y2;
 106         int pf_planes = 1 << plane;
 107
 108         DRM_SPINLOCK_ASSERT(&dev->drw_lock);
 109
 110         /* If the window is visible on the other plane, we have to flip on that
 111          * plane as well.
 112          */
 113         if (plane == 1) {
 114                 x1 = sarea_priv->planeA_x;
 115                 y1 = sarea_priv->planeA_y;
 116                 x2 = x1 + sarea_priv->planeA_w;
 117                 y2 = y1 + sarea_priv->planeA_h;
 118         } else {
 119                 x1 = sarea_priv->planeB_x;
 120                 y1 = sarea_priv->planeB_y;
 121                 x2 = x1 + sarea_priv->planeB_w;
 122                 y2 = y1 + sarea_priv->planeB_h;
 123         }
 124
 125         if (x2 > 0 && y2 > 0) {
 126                 int i, num_rects = drw->num_rects;
 127                 struct drm_clip_rect *rect = drw->rects;
 128
 129                 for (i = 0; i < num_rects; i++)
 130                         if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
 131                               rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
 132                                 pf_planes = 0x3;
 133
 134                                 break;
 135                         }
 136         }
 137
 138         i915_dispatch_flip(dev, pf_planes, 1);
 139 }
 140
 141 /**
 142  * Emit blits for scheduled buffer swaps.
 143  *
 144  * This function will be called with the HW lock held.
 145  */
 146 static void i915_vblank_tasklet(struct drm_device *dev)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         struct list_head *list, *tmp, hits, *hit;
 150         int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
 151         unsigned counter[2];
 152         struct drm_drawable_info *drw;
 153         drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
 154         u32 cpp = dev_priv->cpp,  offsets[3];
 155         u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
 156                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
 157                                 XY_SRC_COPY_BLT_WRITE_RGB)
 158                              : XY_SRC_COPY_BLT_CMD;
 159         u32 src_pitch = sarea_priv->pitch * cpp;
 160         u32 dst_pitch = sarea_priv->pitch * cpp;
 161         /* COPY rop (0xcc), map cpp to magic color depth constants */
 162         u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
 163         RING_LOCALS;
 164
 165         if (sarea_priv->front_tiled) {
 166                 cmd |= XY_SRC_COPY_BLT_DST_TILED;
 167                 dst_pitch >>= 2;
 168         }
 169         if (sarea_priv->back_tiled) {
 170                 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
 171                 src_pitch >>= 2;
 172         }
 173
 174         counter[0] = drm_vblank_count(dev, 0);
 175         counter[1] = drm_vblank_count(dev, 1);
 176
 177         DRM_DEBUG("\n");
 178
 179         INIT_LIST_HEAD(&hits);
 180
 181         nhits = nrects = 0;
 182
 183         /* No irqsave/restore necessary.  This tasklet may be run in an
 184          * interrupt context or normal context, but we don't have to worry
 185          * about getting interrupted by something acquiring the lock, because
 186          * we are the interrupt context thing that acquires the lock.
 187          */
 188         DRM_SPINLOCK(&dev_priv->swaps_lock);
 189
 190         /* Find buffer swaps scheduled for this vertical blank */
 191         list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
 192                 drm_i915_vbl_swap_t *vbl_swap =
 193                         list_entry(list, drm_i915_vbl_swap_t, head);
 194                 int pipe = i915_get_pipe(dev, vbl_swap->plane);
 195
 196                 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
 197                         continue;
 198
 199                 list_del(list);
 200                 dev_priv->swaps_pending--;
 201                 drm_vblank_put(dev, pipe);
 202
 203                 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 204                 DRM_SPINLOCK(&dev->drw_lock);
 205
 206                 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
 207
 208                 if (!drw) {
 209                         DRM_SPINUNLOCK(&dev->drw_lock);
 210                         drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 211                         DRM_SPINLOCK(&dev_priv->swaps_lock);
 212                         continue;
 213                 }
 214
 215                 list_for_each(hit, &hits) {
 216                         drm_i915_vbl_swap_t *swap_cmp =
 217                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 218                         struct drm_drawable_info *drw_cmp =
 219                                 drm_get_drawable_info(dev, swap_cmp->drw_id);
 220
 221                         if (drw_cmp &&
 222                             drw_cmp->rects[0].y1 > drw->rects[0].y1) {
 223                                 list_add_tail(list, hit);
 224                                 break;
 225                         }
 226                 }
 227
 228                 DRM_SPINUNLOCK(&dev->drw_lock);
 229
 230                 /* List of hits was empty, or we reached the end of it */
 231                 if (hit == &hits)
 232                         list_add_tail(list, hits.prev);
 233
 234                 nhits++;
 235
 236                 DRM_SPINLOCK(&dev_priv->swaps_lock);
 237         }
 238
 239         DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 240
 241         if (nhits == 0) {
 242                 return;
 243         }
 244
 245         i915_kernel_lost_context(dev);
 246
 247         upper[0] = upper[1] = 0;
 248         slice[0] = max(sarea_priv->planeA_h / nhits, 1);
 249         slice[1] = max(sarea_priv->planeB_h / nhits, 1);
 250         lower[0] = sarea_priv->planeA_y + slice[0];
 251         lower[1] = sarea_priv->planeB_y + slice[0];
 252
 253         offsets[0] = sarea_priv->front_offset;
 254         offsets[1] = sarea_priv->back_offset;
 255         offsets[2] = sarea_priv->third_offset;
 256         num_pages = sarea_priv->third_handle ? 3 : 2;
 257
 258         DRM_SPINLOCK(&dev->drw_lock);
 259
 260         /* Emit blits for buffer swaps, partitioning both outputs into as many
 261          * slices as there are buffer swaps scheduled in order to avoid tearing
 262          * (based on the assumption that a single buffer swap would always
 263          * complete before scanout starts).
 264          */
 265         for (i = 0; i++ < nhits;
 266              upper[0] = lower[0], lower[0] += slice[0],
 267              upper[1] = lower[1], lower[1] += slice[1]) {
 268                 int init_drawrect = 1;
 269
 270                 if (i == nhits)
 271                         lower[0] = lower[1] = sarea_priv->height;
 272
 273                 list_for_each(hit, &hits) {
 274                         drm_i915_vbl_swap_t *swap_hit =
 275                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 276                         struct drm_clip_rect *rect;
 277                         int num_rects, plane, front, back;
 278                         unsigned short top, bottom;
 279
 280                         drw = drm_get_drawable_info(dev, swap_hit->drw_id);
 281
 282                         if (!drw)
 283                                 continue;
 284
 285                         plane = swap_hit->plane;
 286
 287                         if (swap_hit->flip) {
 288                                 i915_dispatch_vsync_flip(dev, drw, plane);
 289                                 continue;
 290                         }
 291
 292                         if (init_drawrect) {
 293                                 int width  = sarea_priv->width;
 294                                 int height = sarea_priv->height;
 295                                 if (IS_I965G(dev)) {
 296                                         BEGIN_LP_RING(4);
 297
 298                                         OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 299                                         OUT_RING(0);
 300                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 301                                         OUT_RING(0);
 302
 303                                         ADVANCE_LP_RING();
 304                                 } else {
 305                                         BEGIN_LP_RING(6);
 306
 307                                         OUT_RING(GFX_OP_DRAWRECT_INFO);
 308                                         OUT_RING(0);
 309                                         OUT_RING(0);
 310                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 311                                         OUT_RING(0);
 312                                         OUT_RING(0);
 313
 314                                         ADVANCE_LP_RING();
 315                                 }
 316
 317                                 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
 318
 319                                 init_drawrect = 0;
 320                         }
 321
 322                         rect = drw->rects;
 323                         top = upper[plane];
 324                         bottom = lower[plane];
 325
 326                         front = (dev_priv->sarea_priv->pf_current_page >>
 327                                  (2 * plane)) & 0x3;
 328                         back = (front + 1) % num_pages;
 329
 330                         for (num_rects = drw->num_rects; num_rects--; rect++) {
 331                                 int y1 = max(rect->y1, top);
 332                                 int y2 = min(rect->y2, bottom);
 333
 334                                 if (y1 >= y2)
 335                                         continue;
 336
 337                                 BEGIN_LP_RING(8);
 338
 339                                 OUT_RING(cmd);
 340                                 OUT_RING(ropcpp | dst_pitch);
 341                                 OUT_RING((y1 << 16) | rect->x1);
 342                                 OUT_RING((y2 << 16) | rect->x2);
 343                                 OUT_RING(offsets[front]);
 344                                 OUT_RING((y1 << 16) | rect->x1);
 345                                 OUT_RING(src_pitch);
 346                                 OUT_RING(offsets[back]);
 347
 348                                 ADVANCE_LP_RING();
 349                         }
 350                 }
 351         }
 352
 353         DRM_SPINUNLOCK(&dev->drw_lock);
 354
 355         list_for_each_safe(hit, tmp, &hits) {
 356                 drm_i915_vbl_swap_t *swap_hit =
 357                         list_entry(hit, drm_i915_vbl_swap_t, head);
 358
 359                 list_del(hit);
 360
 361                 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
 362         }
 363 }
 364 #if 0
 365 static int i915_in_vblank(struct drm_device *dev, int pipe)
 366 {
 367         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 368         unsigned long pipedsl, vblank, vtotal;
 369         unsigned long vbl_start, vbl_end, cur_line;
 370
 371         pipedsl = pipe ? PIPEBDSL : PIPEADSL;
 372         vblank = pipe ? VBLANK_B : VBLANK_A;
 373         vtotal = pipe ? VTOTAL_B : VTOTAL_A;
 374
 375         vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
 376         vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
 377
 378         cur_line = I915_READ(pipedsl);
 379
 380         if (cur_line >= vbl_start)
 381                 return 1;
 382
 383         return 0;
 384 }
 385 #endif
 386 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
 387 {
 388         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 389         unsigned long high_frame;
 390         unsigned long low_frame;
 391         u32 high1, high2, low, count;
 392         int pipe;
 393
 394         pipe = i915_get_pipe(dev, plane);
 395         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 396         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 397
 398         if (!i915_pipe_enabled(dev, pipe)) {
 399             DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 400             return 0;
 401         }
 402
 403         /*
 404          * High & low register fields aren't synchronized, so make sure
 405          * we get a low value that's stable across two reads of the high
 406          * register.
 407          */
 408         do {
 409                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 410                          PIPE_FRAME_HIGH_SHIFT);
 411                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 412                         PIPE_FRAME_LOW_SHIFT);
 413                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 414                          PIPE_FRAME_HIGH_SHIFT);
 415         } while (high1 != high2);
 416
 417         count = (high1 << 8) | low;
 418
 419         /*
 420          * If we're in the middle of the vblank period, the
 421          * above regs won't have been updated yet, so return
 422          * an incremented count to stay accurate
 423          */
 424 #if 0
 425         if (i915_in_vblank(dev, pipe))
 426                 count++;
 427 #endif
 428         /* count may be reset by other driver(e.g. 2D driver),
 429            we have no way to know if it is wrapped or resetted
 430            when count is zero. do a rough guess.
 431         */
 432         if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
 433                 dev->last_vblank[pipe] = 0;
 434
 435         return count;
 436 }
 437
 438 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 439 {
 440         struct drm_device *dev = (struct drm_device *) arg;
 441         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 442         u32 iir;
 443         u32 pipea_stats, pipeb_stats;
 444         int vblank = 0;
 445
 446         iir = I915_READ(IIR);
 447 #if 0
 448         DRM_DEBUG("flag=%08x\n", iir);
 449 #endif
 450         if (iir == 0) {
 451                 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
 452                            iir,
 453                            I915_READ(IMR),
 454                            I915_READ(IER),
 455                            I915_READ(PIPEASTAT),
 456                            I915_READ(PIPEBSTAT));
 457                 return IRQ_NONE;
 458         }
 459
 460         /*
 461          * Clear the PIPE(A|B)STAT regs before the IIR otherwise
 462          * we may get extra interrupts.
 463          */
 464         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 465                 pipea_stats = I915_READ(PIPEASTAT);
 466                 if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 467                                    PIPE_VBLANK_INTERRUPT_STATUS))
 468                 {
 469                         vblank++;
 470                         drm_handle_vblank(dev, i915_get_plane(dev, 0));
 471                 }
 472
 473                 I915_WRITE(PIPEASTAT, pipea_stats);
 474         }
 475         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 476                 pipeb_stats = I915_READ(PIPEBSTAT);
 477                 if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 478                                    PIPE_VBLANK_INTERRUPT_STATUS))
 479                 {
 480                         vblank++;
 481                         drm_handle_vblank(dev, i915_get_plane(dev, 1));
 482                 }
 483                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 484         }
 485
 486         if (dev_priv->sarea_priv)
 487             dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 488
 489         I915_WRITE(IIR, iir);
 490         (void) I915_READ(IIR);
 491
 492         if (iir & I915_USER_INTERRUPT) {
 493                 DRM_WAKEUP(&dev_priv->irq_queue);
 494 #ifdef I915_HAVE_FENCE
 495                 i915_fence_handler(dev);
 496 #endif
 497         }
 498
 499         if (vblank) {
 500                 if (dev_priv->swaps_pending > 0)
 501                         drm_locked_tasklet(dev, i915_vblank_tasklet);
 502         }
 503
 504         return IRQ_HANDLED;
 505 }
 506
 507 int i915_emit_irq(struct drm_device *dev)
 508 {
 509         drm_i915_private_t *dev_priv = dev->dev_private;
 510         RING_LOCALS;
 511
 512         i915_kernel_lost_context(dev);
 513
 514         DRM_DEBUG("\n");
 515
 516         i915_emit_breadcrumb(dev);
 517
 518         BEGIN_LP_RING(2);
 519         OUT_RING(0);
 520         OUT_RING(MI_USER_INTERRUPT);
 521         ADVANCE_LP_RING();
 522
 523         return dev_priv->counter;
 524 }
 525
 526 void i915_user_irq_on(drm_i915_private_t *dev_priv)
 527 {
 528         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 529         if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
 530                 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
 531                 I915_WRITE(IER, dev_priv->irq_enable_reg);
 532         }
 533         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 534
 535 }
 536
 537 void i915_user_irq_off(drm_i915_private_t *dev_priv)
 538 {
 539         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 540         if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 541                 //              dev_priv->irq_enable_reg &= ~I915_USER_INTERRUPT;
 542                 //              I915_WRITE(IER, dev_priv->irq_enable_reg);
 543         }
 544         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 545 }
 546
 547
 548 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 549 {
 550         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 551         int ret = 0;
 552
 553         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 554                   READ_BREADCRUMB(dev_priv));
 555
 556         if (READ_BREADCRUMB(dev_priv) >= irq_nr)
 557                 return 0;
 558
 559         i915_user_irq_on(dev_priv);
 560         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 561                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 562         i915_user_irq_off(dev_priv);
 563
 564         if (ret == -EBUSY) {
 565                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 566                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 567         }
 568
 569         if (dev_priv->sarea_priv)
 570                 dev_priv->sarea_priv->last_dispatch =
 571                         READ_BREADCRUMB(dev_priv);
 572         return ret;
 573 }
 574
 575 /* Needs the lock as it touches the ring.
 576  */
 577 int i915_irq_emit(struct drm_device *dev, void *data,
 578                          struct drm_file *file_priv)
 579 {
 580         drm_i915_private_t *dev_priv = dev->dev_private;
 581         drm_i915_irq_emit_t *emit = data;
 582         int result;
 583
 584         LOCK_TEST_WITH_RETURN(dev, file_priv);
 585
 586         if (!dev_priv) {
 587                 DRM_ERROR("called with no initialization\n");
 588                 return -EINVAL;
 589         }
 590
 591         result = i915_emit_irq(dev);
 592
 593         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 594                 DRM_ERROR("copy_to_user\n");
 595                 return -EFAULT;
 596         }
 597
 598         return 0;
 599 }
 600
 601 /* Doesn't need the hardware lock.
 602  */
 603 int i915_irq_wait(struct drm_device *dev, void *data,
 604                   struct drm_file *file_priv)
 605 {
 606         drm_i915_private_t *dev_priv = dev->dev_private;
 607         drm_i915_irq_wait_t *irqwait = data;
 608
 609         if (!dev_priv) {
 610                 DRM_ERROR("called with no initialization\n");
 611                 return -EINVAL;
 612         }
 613
 614         return i915_wait_irq(dev, irqwait->irq_seq);
 615 }
 616
 617 int i915_enable_vblank(struct drm_device *dev, int plane)
 618 {
 619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 620         int pipe = i915_get_pipe(dev, plane);
 621         u32     pipestat_reg = 0;
 622         u32     pipestat;
 623
 624         switch (pipe) {
 625         case 0:
 626                 pipestat_reg = PIPEASTAT;
 627                 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 628                 break;
 629         case 1:
 630                 pipestat_reg = PIPEBSTAT;
 631                 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 632                 break;
 633         default:
 634                 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
 635                           pipe);
 636                 break;
 637         }
 638
 639         if (pipestat_reg)
 640         {
 641                 pipestat = I915_READ (pipestat_reg);
 642                 /*
 643                  * Older chips didn't have the start vblank interrupt,
 644                  * but
 645                  */
 646                 if (IS_I965G (dev))
 647                         pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
 648                 else
 649                         pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
 650                 /*
 651                  * Clear any pending status
 652                  */
 653                 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 654                              PIPE_VBLANK_INTERRUPT_STATUS);
 655                 I915_WRITE(pipestat_reg, pipestat);
 656         }
 657         I915_WRITE(IER, dev_priv->irq_enable_reg);
 658
 659         return 0;
 660 }
 661
 662 void i915_disable_vblank(struct drm_device *dev, int plane)
 663 {
 664         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 665         int pipe = i915_get_pipe(dev, plane);
 666         u32     pipestat_reg = 0;
 667         u32     pipestat;
 668
 669         switch (pipe) {
 670         case 0:
 671                 pipestat_reg = PIPEASTAT;
 672                 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 673                 break;
 674         case 1:
 675                 pipestat_reg = PIPEBSTAT;
 676                 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 677                 break;
 678         default:
 679                 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
 680                           pipe);
 681                 break;
 682         }
 683
 684         I915_WRITE(IER, dev_priv->irq_enable_reg);
 685
 686         if (pipestat_reg)
 687         {
 688                 pipestat = I915_READ (pipestat_reg);
 689                 pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 690                               PIPE_VBLANK_INTERRUPT_ENABLE);
 691                 /*
 692                  * Clear any pending status
 693                  */
 694                 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 695                              PIPE_VBLANK_INTERRUPT_STATUS);
 696                 I915_WRITE(pipestat_reg, pipestat);
 697         }
 698 }
 699
 700 static void i915_enable_interrupt (struct drm_device *dev)
 701 {
 702         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 703
 704         dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
 705
 706         I915_WRITE(IER, dev_priv->irq_enable_reg);
 707         dev_priv->irq_enabled = 1;
 708 }
 709
 710 /* Set the vblank monitor pipe
 711  */
 712 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 713                          struct drm_file *file_priv)
 714 {
 715         drm_i915_private_t *dev_priv = dev->dev_private;
 716         drm_i915_vblank_pipe_t *pipe = data;
 717
 718         if (!dev_priv) {
 719                 DRM_ERROR("called with no initialization\n");
 720                 return -EINVAL;
 721         }
 722
 723         if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
 724                 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
 725                 return -EINVAL;
 726         }
 727
 728         dev_priv->vblank_pipe = pipe->pipe;
 729
 730         return 0;
 731 }
 732
 733 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 734                          struct drm_file *file_priv)
 735 {
 736         drm_i915_private_t *dev_priv = dev->dev_private;
 737         drm_i915_vblank_pipe_t *pipe = data;
 738         u16 flag;
 739
 740         if (!dev_priv) {
 741                 DRM_ERROR("called with no initialization\n");
 742                 return -EINVAL;
 743         }
 744
 745         flag = I915_READ(IER);
 746
 747         pipe->pipe = 0;
 748         if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
 749                 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
 750         if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
 751                 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
 752
 753         return 0;
 754 }
 755
 756 /**
 757  * Schedule buffer swap at given vertical blank.
 758  */
 759 int i915_vblank_swap(struct drm_device *dev, void *data,
 760                      struct drm_file *file_priv)
 761 {
 762         drm_i915_private_t *dev_priv = dev->dev_private;
 763         drm_i915_vblank_swap_t *swap = data;
 764         drm_i915_vbl_swap_t *vbl_swap;
 765         unsigned int pipe, seqtype, curseq, plane;
 766         unsigned long irqflags;
 767         struct list_head *list;
 768         int ret;
 769
 770         if (!dev_priv) {
 771                 DRM_ERROR("%s called with no initialization\n", __func__);
 772                 return -EINVAL;
 773         }
 774
 775         if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
 776                 DRM_DEBUG("Rotation not supported\n");
 777                 return -EINVAL;
 778         }
 779
 780         if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
 781                              _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
 782                              _DRM_VBLANK_FLIP)) {
 783                 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
 784                 return -EINVAL;
 785         }
 786
 787         plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
 788         pipe = i915_get_pipe(dev, plane);
 789
 790         seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
 791
 792         if (!(dev_priv->vblank_pipe & (1 << pipe))) {
 793                 DRM_ERROR("Invalid pipe %d\n", pipe);
 794                 return -EINVAL;
 795         }
 796
 797         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
 798
 799         /* It makes no sense to schedule a swap for a drawable that doesn't have
 800          * valid information at this point. E.g. this could mean that the X
 801          * server is too old to push drawable information to the DRM, in which
 802          * case all such swaps would become ineffective.
 803          */
 804         if (!drm_get_drawable_info(dev, swap->drawable)) {
 805                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 806                 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
 807                 return -EINVAL;
 808         }
 809
 810         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 811
 812         drm_update_vblank_count(dev, pipe);
 813         curseq = drm_vblank_count(dev, pipe);
 814
 815         if (seqtype == _DRM_VBLANK_RELATIVE)
 816                 swap->sequence += curseq;
 817
 818         if ((curseq - swap->sequence) <= (1<<23)) {
 819                 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
 820                         swap->sequence = curseq + 1;
 821                 } else {
 822                         DRM_DEBUG("Missed target sequence\n");
 823                         return -EINVAL;
 824                 }
 825         }
 826
 827         if (swap->seqtype & _DRM_VBLANK_FLIP) {
 828                 swap->sequence--;
 829
 830                 if ((curseq - swap->sequence) <= (1<<23)) {
 831                         struct drm_drawable_info *drw;
 832
 833                         LOCK_TEST_WITH_RETURN(dev, file_priv);
 834
 835                         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
 836
 837                         drw = drm_get_drawable_info(dev, swap->drawable);
 838
 839                         if (!drw) {
 840                                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
 841                                     irqflags);
 842                                 DRM_DEBUG("Invalid drawable ID %d\n",
 843                                           swap->drawable);
 844                                 return -EINVAL;
 845                         }
 846
 847                         i915_dispatch_vsync_flip(dev, drw, plane);
 848
 849                         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 850
 851                         return 0;
 852                 }
 853         }
 854
 855         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
 856
 857         list_for_each(list, &dev_priv->vbl_swaps.head) {
 858                 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
 859
 860                 if (vbl_swap->drw_id == swap->drawable &&
 861                     vbl_swap->plane == plane &&
 862                     vbl_swap->sequence == swap->sequence) {
 863                         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
 864                         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 865                         DRM_DEBUG("Already scheduled\n");
 866                         return 0;
 867                 }
 868         }
 869
 870         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 871
 872         if (dev_priv->swaps_pending >= 100) {
 873                 DRM_DEBUG("Too many swaps queued\n");
 874                 return -EBUSY;
 875         }
 876
 877         vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 878
 879         if (!vbl_swap) {
 880                 DRM_ERROR("Failed to allocate memory to queue swap\n");
 881                 return -ENOMEM;
 882         }
 883
 884         DRM_DEBUG("\n");
 885
 886         ret = drm_vblank_get(dev, pipe);
 887         if (ret) {
 888                 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 889                 return ret;
 890         }
 891
 892         vbl_swap->drw_id = swap->drawable;
 893         vbl_swap->plane = plane;
 894         vbl_swap->sequence = swap->sequence;
 895         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
 896
 897         if (vbl_swap->flip)
 898                 swap->sequence++;
 899
 900         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
 901
 902         list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
 903         dev_priv->swaps_pending++;
 904
 905         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 906
 907         return 0;
 908 }
 909
 910 /* drm_dma.h hooks
 911 */
 912 void i915_driver_irq_preinstall(struct drm_device * dev)
 913 {
 914         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 915
 916         I915_WRITE16(HWSTAM, 0xeffe);
 917         I915_WRITE16(IMR, 0x0);
 918         I915_WRITE16(IER, 0x0);
 919 }
 920
 921 int i915_driver_irq_postinstall(struct drm_device * dev)
 922 {
 923         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 924         int ret, num_pipes = 2;
 925
 926         DRM_SPININIT(&dev_priv->swaps_lock, "swap");
 927         INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 928         dev_priv->swaps_pending = 0;
 929
 930         DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
 931         dev_priv->user_irq_refcount = 0;
 932         dev_priv->irq_enable_reg = 0;
 933
 934         ret = drm_vblank_init(dev, num_pipes);
 935         if (ret)
 936                 return ret;
 937
 938         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 939
 940         i915_enable_interrupt(dev);
 941         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 942
 943         /*
 944          * Initialize the hardware status page IRQ location.
 945          */
 946
 947         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
 948         return 0;
 949 }
 950
 951 void i915_driver_irq_uninstall(struct drm_device * dev)
 952 {
 953         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 954         u32 temp;
 955
 956         if (!dev_priv)
 957                 return;
 958
 959         dev_priv->irq_enabled = 0;
 960         I915_WRITE(HWSTAM, 0xffffffff);
 961         I915_WRITE(IMR, 0xffffffff);
 962         I915_WRITE(IER, 0x0);
 963
 964         temp = I915_READ(PIPEASTAT);
 965         I915_WRITE(PIPEASTAT, temp);
 966         temp = I915_READ(PIPEBSTAT);
 967         I915_WRITE(PIPEBSTAT, temp);
 968         temp = I915_READ(IIR);
 969         I915_WRITE(IIR, temp);
 970 }