1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
3 /**************************************************************************
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 **************************************************************************/
13 /* General customization:
16 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
18 #define DRIVER_NAME "i915"
19 #define DRIVER_DESC "Intel Graphics"
20 #define DRIVER_DATE "20041217"
25 * 1.2: Add Power Management
27 #define DRIVER_MAJOR 1
28 #define DRIVER_MINOR 2
29 #define DRIVER_PATCHLEVEL 0
31 typedef struct _drm_i915_ring_buffer {
41 } drm_i915_ring_buffer_t;
44 struct mem_block *next;
45 struct mem_block *prev;
48 DRMFILE filp; /* 0: free, -1: heap, other: real files */
51 typedef struct drm_i915_private {
52 drm_local_map_t *sarea;
53 drm_local_map_t *mmio_map;
55 drm_i915_sarea_t *sarea_priv;
56 drm_i915_ring_buffer_t ring;
59 unsigned long counter;
60 dma_addr_t dma_status_page;
66 int use_mi_batchbuffer_start;
68 wait_queue_head_t irq_queue;
69 atomic_t irq_received;
72 int tex_lru_log_granularity;
73 int allow_batchbuffer;
74 struct mem_block *agp_heap;
78 extern int i915_dma_init(DRM_IOCTL_ARGS);
79 extern int i915_dma_cleanup(drm_device_t * dev);
80 extern int i915_flush_ioctl(DRM_IOCTL_ARGS);
81 extern int i915_batchbuffer(DRM_IOCTL_ARGS);
82 extern int i915_flip_bufs(DRM_IOCTL_ARGS);
83 extern int i915_getparam(DRM_IOCTL_ARGS);
84 extern int i915_setparam(DRM_IOCTL_ARGS);
85 extern int i915_cmdbuffer(DRM_IOCTL_ARGS);
86 extern void i915_kernel_lost_context(drm_device_t * dev);
87 extern void i915_driver_pretakedown(drm_device_t * dev);
88 extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
91 extern int i915_irq_emit(DRM_IOCTL_ARGS);
92 extern int i915_irq_wait(DRM_IOCTL_ARGS);
93 extern int i915_wait_irq(drm_device_t * dev, int irq_nr);
94 extern int i915_emit_irq(drm_device_t * dev);
96 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
97 extern void i915_driver_irq_preinstall(drm_device_t * dev);
98 extern void i915_driver_irq_postinstall(drm_device_t * dev);
99 extern void i915_driver_irq_uninstall(drm_device_t * dev);
102 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
103 extern int i915_mem_free(DRM_IOCTL_ARGS);
104 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
105 extern void i915_mem_takedown(struct mem_block **heap);
106 extern void i915_mem_release(drm_device_t * dev,
107 DRMFILE filp, struct mem_block *heap);
109 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
110 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
111 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
112 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
114 #define I915_VERBOSE 0
116 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
119 #define BEGIN_LP_RING(n) do { \
121 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
123 if (dev_priv->ring.space < n*4) \
124 i915_wait_ring(dev, n*4, __FUNCTION__); \
126 outring = dev_priv->ring.tail; \
127 ringmask = dev_priv->ring.tail_mask; \
128 virt = dev_priv->ring.virtual_start; \
131 #define OUT_RING(n) do { \
132 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
133 *(volatile unsigned int *)(virt + outring) = n; \
136 outring &= ringmask; \
139 #define ADVANCE_LP_RING() do { \
140 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
141 dev_priv->ring.tail = outring; \
142 dev_priv->ring.space -= outcount * 4; \
143 I915_WRITE(LP_RING + RING_TAIL, outring); \
146 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
148 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
149 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
150 #define CMD_REPORT_HEAD (7<<23)
151 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
152 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
154 #define INST_PARSER_CLIENT 0x00000000
155 #define INST_OP_FLUSH 0x02000000
156 #define INST_FLUSH_MAP_CACHE 0x00000001
158 #define BB1_START_ADDR_MASK (~0x7)
159 #define BB1_PROTECTED (1<<0)
160 #define BB1_UNPROTECTED (0<<0)
161 #define BB2_END_ADDR_MASK (~0x7)
163 #define I915REG_HWSTAM 0x02098
164 #define I915REG_INT_IDENTITY_R 0x020a4
165 #define I915REG_INT_MASK_R 0x020a8
166 #define I915REG_INT_ENABLE_R 0x020a0
168 #define SRX_INDEX 0x3c4
169 #define SRX_DATA 0x3c5
171 #define SR01_SCREEN_OFF (1<<5)
174 #define PPCR_ON (1<<0)
177 #define ADPA_DPMS_MASK (~(3<<10))
178 #define ADPA_DPMS_ON (0<<10)
179 #define ADPA_DPMS_SUSPEND (1<<10)
180 #define ADPA_DPMS_STANDBY (2<<10)
181 #define ADPA_DPMS_OFF (3<<10)
184 #define LP_RING 0x2030
185 #define HP_RING 0x2040
186 #define RING_TAIL 0x00
187 #define TAIL_ADDR 0x001FFFF8
188 #define RING_HEAD 0x04
189 #define HEAD_WRAP_COUNT 0xFFE00000
190 #define HEAD_WRAP_ONE 0x00200000
191 #define HEAD_ADDR 0x001FFFFC
192 #define RING_START 0x08
193 #define START_ADDR 0x0xFFFFF000
194 #define RING_LEN 0x0C
195 #define RING_NR_PAGES 0x001FF000
196 #define RING_REPORT_MASK 0x00000006
197 #define RING_REPORT_64K 0x00000002
198 #define RING_REPORT_128K 0x00000004
199 #define RING_NO_REPORT 0x00000000
200 #define RING_VALID_MASK 0x00000001
201 #define RING_VALID 0x00000001
202 #define RING_INVALID 0x00000000
204 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
205 #define SC_UPDATE_SCISSOR (0x1<<1)
206 #define SC_ENABLE_MASK (0x1<<0)
207 #define SC_ENABLE (0x1<<0)
209 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
210 #define SCI_YMIN_MASK (0xffff<<16)
211 #define SCI_XMIN_MASK (0xffff<<0)
212 #define SCI_YMAX_MASK (0xffff<<16)
213 #define SCI_XMAX_MASK (0xffff<<0)
215 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
216 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
217 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
218 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
219 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
220 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
221 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
223 #define MI_BATCH_BUFFER ((0x30<<23)|1)
224 #define MI_BATCH_BUFFER_START (0x31<<23)
225 #define MI_BATCH_BUFFER_END (0xA<<23)
226 #define MI_BATCH_NON_SECURE (1)
228 #define MI_WAIT_FOR_EVENT ((0x3<<23))
229 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
230 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
232 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
234 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235 #define ASYNC_FLIP (1<<22)
237 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)