shared-core/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 /* General customization:
  34  */
  35
  36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  37
  38 #define DRIVER_NAME             "i915"
  39 #define DRIVER_DESC             "Intel Graphics"
  40 #define DRIVER_DATE             "20060119"
  41
  42 /* Interface history:
  43  *
  44  * 1.1: Original.
  45  * 1.2: Add Power Management
  46  * 1.3: Add vblank support
  47  * 1.4: Fix cmdbuffer path, add heap destroy
  48  * 1.5: Add vblank pipe configuration
  49  */
  50 #define DRIVER_MAJOR            1
  51 #define DRIVER_MINOR            5
  52 #define DRIVER_PATCHLEVEL       0
  53
  54 #if defined(__linux__)
  55 #define I915_HAVE_FENCE
  56 #define I915_HAVE_BUFFER
  57 #endif
  58
  59 typedef struct _drm_i915_ring_buffer {
  60         int tail_mask;
  61         unsigned long Start;
  62         unsigned long End;
  63         unsigned long Size;
  64         u8 *virtual_start;
  65         int head;
  66         int tail;
  67         int space;
  68         drm_local_map_t map;
  69 } drm_i915_ring_buffer_t;
  70
  71 struct mem_block {
  72         struct mem_block *next;
  73         struct mem_block *prev;
  74         int start;
  75         int size;
  76         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  77 };
  78
  79 typedef struct drm_i915_private {
  80         drm_local_map_t *sarea;
  81         drm_local_map_t *mmio_map;
  82
  83         drm_i915_sarea_t *sarea_priv;
  84         drm_i915_ring_buffer_t ring;
  85
  86         drm_dma_handle_t *status_page_dmah;
  87         void *hw_status_page;
  88         dma_addr_t dma_status_page;
  89         uint32_t counter;
  90
  91         int back_offset;
  92         int front_offset;
  93         int current_page;
  94         int page_flipping;
  95         int use_mi_batchbuffer_start;
  96
  97         wait_queue_head_t irq_queue;
  98         atomic_t irq_received;
  99         atomic_t irq_emitted;
 100
 101         int tex_lru_log_granularity;
 102         int allow_batchbuffer;
 103         struct mem_block *agp_heap;
 104         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 105         int vblank_pipe;
 106         spinlock_t user_irq_lock;
 107         int user_irq_refcount;
 108         int fence_irq_on;
 109         uint32_t irq_enable_reg;
 110         int irq_enabled;
 111
 112 #ifdef I915_HAVE_FENCE
 113         uint32_t flush_sequence;
 114         uint32_t flush_flags;
 115         uint32_t flush_pending;
 116         uint32_t saved_flush_status;
 117 #endif
 118
 119 } drm_i915_private_t;
 120
 121 extern drm_ioctl_desc_t i915_ioctls[];
 122 extern int i915_max_ioctl;
 123
 124                                 /* i915_dma.c */
 125 extern void i915_kernel_lost_context(drm_device_t * dev);
 126 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 127 extern void i915_driver_lastclose(drm_device_t * dev);
 128 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
 129 extern int i915_driver_device_is_agp(drm_device_t * dev);
 130 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 131                               unsigned long arg);
 132 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
 133
 134
 135 /* i915_irq.c */
 136 extern int i915_irq_emit(DRM_IOCTL_ARGS);
 137 extern int i915_irq_wait(DRM_IOCTL_ARGS);
 138
 139 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
 140 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 141 extern void i915_driver_irq_preinstall(drm_device_t * dev);
 142 extern void i915_driver_irq_postinstall(drm_device_t * dev);
 143 extern void i915_driver_irq_uninstall(drm_device_t * dev);
 144 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
 145 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
 146 extern int i915_emit_irq(drm_device_t * dev);
 147 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
 148 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
 149
 150 /* i915_mem.c */
 151 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 152 extern int i915_mem_free(DRM_IOCTL_ARGS);
 153 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 154 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
 155 extern void i915_mem_takedown(struct mem_block **heap);
 156 extern void i915_mem_release(drm_device_t * dev,
 157                              DRMFILE filp, struct mem_block *heap);
 158 #ifdef I915_HAVE_FENCE
 159 /* i915_fence.c */
 160
 161
 162 extern void i915_fence_handler(drm_device_t *dev);
 163 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t flags,
 164                                     uint32_t *sequence,
 165                                     uint32_t *native_type);
 166 extern void i915_poke_flush(drm_device_t *dev);
 167 extern void i915_sync_flush(drm_device_t *dev);
 168 #endif
 169
 170 #ifdef I915_HAVE_BUFFER
 171 /* i915_buffer.c */
 172 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev,
 173         int cached);
 174 extern int i915_fence_types(uint32_t buffer_flags, uint32_t *class, uint32_t *type);
 175 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
 176 #endif
 177
 178 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 179 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 180 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 181 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 182
 183 #define I915_VERBOSE 0
 184
 185 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 186                         volatile char *virt;
 187
 188 #define BEGIN_LP_RING(n) do {                           \
 189         if (I915_VERBOSE)                               \
 190                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 191                                  (n), __FUNCTION__);           \
 192         if (dev_priv->ring.space < (n)*4)                      \
 193                 i915_wait_ring(dev, (n)*4, __FUNCTION__);      \
 194         outcount = 0;                                   \
 195         outring = dev_priv->ring.tail;                  \
 196         ringmask = dev_priv->ring.tail_mask;            \
 197         virt = dev_priv->ring.virtual_start;            \
 198 } while (0)
 199
 200 #define OUT_RING(n) do {                                        \
 201         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 202         *(volatile unsigned int *)(virt + outring) = (n);               \
 203         outcount++;                                             \
 204         outring += 4;                                           \
 205         outring &= ringmask;                                    \
 206 } while (0)
 207
 208 #define ADVANCE_LP_RING() do {                                          \
 209         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 210         dev_priv->ring.tail = outring;                                  \
 211         dev_priv->ring.space -= outcount * 4;                           \
 212         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 213 } while(0)
 214
 215 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 216
 217 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 218 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 219 #define CMD_REPORT_HEAD                 (7<<23)
 220 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 221 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 222
 223 #define INST_PARSER_CLIENT   0x00000000
 224 #define INST_OP_FLUSH        0x02000000
 225 #define INST_FLUSH_MAP_CACHE 0x00000001
 226
 227 #define CMD_MI_FLUSH         (0x04 << 23)
 228 #define MI_NO_WRITE_FLUSH    (1 << 2)
 229 #define MI_READ_FLUSH        (1 << 0)
 230 #define MI_EXE_FLUSH         (1 << 1)
 231
 232 #define BB1_START_ADDR_MASK   (~0x7)
 233 #define BB1_PROTECTED         (1<<0)
 234 #define BB1_UNPROTECTED       (0<<0)
 235 #define BB2_END_ADDR_MASK     (~0x7)
 236
 237 #define I915REG_HWSTAM          0x02098
 238 #define I915REG_INT_IDENTITY_R  0x020a4
 239 #define I915REG_INT_MASK_R      0x020a8
 240 #define I915REG_INT_ENABLE_R    0x020a0
 241 #define I915REG_INSTPM          0x020c0
 242
 243 #define SRX_INDEX               0x3c4
 244 #define SRX_DATA                0x3c5
 245 #define SR01                    1
 246 #define SR01_SCREEN_OFF         (1<<5)
 247
 248 #define PPCR                    0x61204
 249 #define PPCR_ON                 (1<<0)
 250
 251 #define DVOB                    0x61140
 252 #define DVOB_ON                 (1<<31)
 253 #define DVOC                    0x61160
 254 #define DVOC_ON                 (1<<31)
 255 #define LVDS                    0x61180
 256 #define LVDS_ON                 (1<<31)
 257
 258 #define ADPA                    0x61100
 259 #define ADPA_DPMS_MASK          (~(3<<10))
 260 #define ADPA_DPMS_ON            (0<<10)
 261 #define ADPA_DPMS_SUSPEND       (1<<10)
 262 #define ADPA_DPMS_STANDBY       (2<<10)
 263 #define ADPA_DPMS_OFF           (3<<10)
 264
 265 #define NOPID                   0x2094
 266 #define LP_RING                 0x2030
 267 #define HP_RING                 0x2040
 268 #define RING_TAIL               0x00
 269 #define TAIL_ADDR               0x001FFFF8
 270 #define RING_HEAD               0x04
 271 #define HEAD_WRAP_COUNT         0xFFE00000
 272 #define HEAD_WRAP_ONE           0x00200000
 273 #define HEAD_ADDR               0x001FFFFC
 274 #define RING_START              0x08
 275 #define START_ADDR              0x0xFFFFF000
 276 #define RING_LEN                0x0C
 277 #define RING_NR_PAGES           0x001FF000
 278 #define RING_REPORT_MASK        0x00000006
 279 #define RING_REPORT_64K         0x00000002
 280 #define RING_REPORT_128K        0x00000004
 281 #define RING_NO_REPORT          0x00000000
 282 #define RING_VALID_MASK         0x00000001
 283 #define RING_VALID              0x00000001
 284 #define RING_INVALID            0x00000000
 285
 286 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 287 #define SC_UPDATE_SCISSOR       (0x1<<1)
 288 #define SC_ENABLE_MASK          (0x1<<0)
 289 #define SC_ENABLE               (0x1<<0)
 290
 291 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 292 #define SCI_YMIN_MASK      (0xffff<<16)
 293 #define SCI_XMIN_MASK      (0xffff<<0)
 294 #define SCI_YMAX_MASK      (0xffff<<16)
 295 #define SCI_XMAX_MASK      (0xffff<<0)
 296
 297 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 298 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 299 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 300 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 301 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 302 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 303 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 304
 305 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
 306
 307 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 308 #define MI_BATCH_BUFFER_START   (0x31<<23)
 309 #define MI_BATCH_BUFFER_END     (0xA<<23)
 310 #define MI_BATCH_NON_SECURE     (1)
 311
 312 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 313 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 314 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 315
 316 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 317
 318 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 319 #define ASYNC_FLIP                (1<<22)
 320
 321 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 322
 323 #define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
 324 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 325 #endif