shared-core/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 /* General customization:
  34  */
  35
  36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  37
  38 #define DRIVER_NAME             "i915"
  39 #define DRIVER_DESC             "Intel Graphics"
  40 #define DRIVER_DATE             "20060929"
  41
  42 /* Interface history:
  43  *
  44  * 1.1: Original.
  45  * 1.2: Add Power Management
  46  * 1.3: Add vblank support
  47  * 1.4: Fix cmdbuffer path, add heap destroy
  48  * 1.5: Add vblank pipe configuration
  49  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  50  *      - Support vertical blank on secondary display pipe
  51  * 1.8: New ioctl for ARB_Occlusion_Query
  52  */
  53 #define DRIVER_MAJOR            1
  54 #define DRIVER_MINOR            8
  55 #define DRIVER_PATCHLEVEL       0
  56
  57 #if defined(__linux__)
  58 #define I915_HAVE_FENCE
  59 #define I915_HAVE_BUFFER
  60 #endif
  61
  62 typedef struct _drm_i915_ring_buffer {
  63         int tail_mask;
  64         unsigned long Start;
  65         unsigned long End;
  66         unsigned long Size;
  67         u8 *virtual_start;
  68         int head;
  69         int tail;
  70         int space;
  71         drm_local_map_t map;
  72 } drm_i915_ring_buffer_t;
  73
  74 struct mem_block {
  75         struct mem_block *next;
  76         struct mem_block *prev;
  77         int start;
  78         int size;
  79         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  80 };
  81
  82 typedef struct _drm_i915_vbl_swap {
  83         struct list_head head;
  84         drm_drawable_t drw_id;
  85         unsigned int pipe;
  86         unsigned int sequence;
  87 } drm_i915_vbl_swap_t;
  88
  89 typedef struct drm_i915_private {
  90         drm_local_map_t *sarea;
  91         drm_local_map_t *mmio_map;
  92
  93         drm_i915_sarea_t *sarea_priv;
  94         drm_i915_ring_buffer_t ring;
  95
  96         drm_dma_handle_t *status_page_dmah;
  97         void *hw_status_page;
  98         dma_addr_t dma_status_page;
  99         uint32_t counter;
 100
 101         unsigned int cpp;
 102         int back_offset;
 103         int front_offset;
 104         int current_page;
 105         int page_flipping;
 106         int use_mi_batchbuffer_start;
 107
 108         wait_queue_head_t irq_queue;
 109         atomic_t irq_received;
 110         atomic_t irq_emitted;
 111
 112         int tex_lru_log_granularity;
 113         int allow_batchbuffer;
 114         struct mem_block *agp_heap;
 115         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 116         int vblank_pipe;
 117         spinlock_t user_irq_lock;
 118         int user_irq_refcount;
 119         int fence_irq_on;
 120         uint32_t irq_enable_reg;
 121         int irq_enabled;
 122
 123 #ifdef I915_HAVE_FENCE
 124         uint32_t flush_sequence;
 125         uint32_t flush_flags;
 126         uint32_t flush_pending;
 127         uint32_t saved_flush_status;
 128 #endif
 129
 130         spinlock_t swaps_lock;
 131         drm_i915_vbl_swap_t vbl_swaps;
 132         unsigned int swaps_pending;
 133 } drm_i915_private_t;
 134
 135 extern drm_ioctl_desc_t i915_ioctls[];
 136 extern int i915_max_ioctl;
 137
 138                                 /* i915_dma.c */
 139 extern void i915_kernel_lost_context(drm_device_t * dev);
 140 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 141 extern void i915_driver_lastclose(drm_device_t * dev);
 142 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
 143 extern int i915_driver_device_is_agp(drm_device_t * dev);
 144 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 145                               unsigned long arg);
 146 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
 147
 148
 149 /* i915_irq.c */
 150 extern int i915_irq_emit(DRM_IOCTL_ARGS);
 151 extern int i915_irq_wait(DRM_IOCTL_ARGS);
 152
 153 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
 154 extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);
 155 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 156 extern void i915_driver_irq_preinstall(drm_device_t * dev);
 157 extern void i915_driver_irq_postinstall(drm_device_t * dev);
 158 extern void i915_driver_irq_uninstall(drm_device_t * dev);
 159 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
 160 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
 161 extern int i915_emit_irq(drm_device_t * dev);
 162 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
 163 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
 164 extern int i915_vblank_swap(DRM_IOCTL_ARGS);
 165
 166 /* i915_mem.c */
 167 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 168 extern int i915_mem_free(DRM_IOCTL_ARGS);
 169 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 170 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
 171 extern void i915_mem_takedown(struct mem_block **heap);
 172 extern void i915_mem_release(drm_device_t * dev,
 173                              DRMFILE filp, struct mem_block *heap);
 174 #ifdef I915_HAVE_FENCE
 175 /* i915_fence.c */
 176
 177
 178 extern void i915_fence_handler(drm_device_t *dev);
 179 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t flags,
 180                                     uint32_t *sequence,
 181                                     uint32_t *native_type);
 182 extern void i915_poke_flush(drm_device_t *dev);
 183 #endif
 184
 185 #ifdef I915_HAVE_BUFFER
 186 /* i915_buffer.c */
 187 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev);
 188 extern int i915_fence_types(uint32_t buffer_flags, uint32_t *class, uint32_t *type);
 189 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
 190 #endif
 191
 192 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 193 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 194 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 195 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 196
 197 #define I915_VERBOSE 0
 198
 199 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 200                         volatile char *virt;
 201
 202 #define BEGIN_LP_RING(n) do {                           \
 203         if (I915_VERBOSE)                               \
 204                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 205                                  (n), __FUNCTION__);           \
 206         if (dev_priv->ring.space < (n)*4)                      \
 207                 i915_wait_ring(dev, (n)*4, __FUNCTION__);      \
 208         outcount = 0;                                   \
 209         outring = dev_priv->ring.tail;                  \
 210         ringmask = dev_priv->ring.tail_mask;            \
 211         virt = dev_priv->ring.virtual_start;            \
 212 } while (0)
 213
 214 #define OUT_RING(n) do {                                        \
 215         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 216         *(volatile unsigned int *)(virt + outring) = (n);               \
 217         outcount++;                                             \
 218         outring += 4;                                           \
 219         outring &= ringmask;                                    \
 220 } while (0)
 221
 222 #define ADVANCE_LP_RING() do {                                          \
 223         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 224         dev_priv->ring.tail = outring;                                  \
 225         dev_priv->ring.space -= outcount * 4;                           \
 226         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 227 } while(0)
 228
 229 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 230
 231 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 232 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 233 #define CMD_REPORT_HEAD                 (7<<23)
 234 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 235 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 236
 237 #define INST_PARSER_CLIENT   0x00000000
 238 #define INST_OP_FLUSH        0x02000000
 239 #define INST_FLUSH_MAP_CACHE 0x00000001
 240
 241 #define CMD_MI_FLUSH         (0x04 << 23)
 242 #define MI_NO_WRITE_FLUSH    (1 << 2)
 243 #define MI_READ_FLUSH        (1 << 0)
 244 #define MI_EXE_FLUSH         (1 << 1)
 245
 246 #define BB1_START_ADDR_MASK   (~0x7)
 247 #define BB1_PROTECTED         (1<<0)
 248 #define BB1_UNPROTECTED       (0<<0)
 249 #define BB2_END_ADDR_MASK     (~0x7)
 250
 251 #define I915REG_HWSTAM          0x02098
 252 #define I915REG_INT_IDENTITY_R  0x020a4
 253 #define I915REG_INT_MASK_R      0x020a8
 254 #define I915REG_INT_ENABLE_R    0x020a0
 255 #define I915REG_INSTPM          0x020c0
 256
 257 #define I915REG_PIPEASTAT       0x70024
 258 #define I915REG_PIPEBSTAT       0x71024
 259
 260 #define I915_VBLANK_INTERRUPT_ENABLE    (1UL<<17)
 261 #define I915_VBLANK_CLEAR               (1UL<<1)
 262
 263 #define SRX_INDEX               0x3c4
 264 #define SRX_DATA                0x3c5
 265 #define SR01                    1
 266 #define SR01_SCREEN_OFF         (1<<5)
 267
 268 #define PPCR                    0x61204
 269 #define PPCR_ON                 (1<<0)
 270
 271 #define DVOB                    0x61140
 272 #define DVOB_ON                 (1<<31)
 273 #define DVOC                    0x61160
 274 #define DVOC_ON                 (1<<31)
 275 #define LVDS                    0x61180
 276 #define LVDS_ON                 (1<<31)
 277
 278 #define ADPA                    0x61100
 279 #define ADPA_DPMS_MASK          (~(3<<10))
 280 #define ADPA_DPMS_ON            (0<<10)
 281 #define ADPA_DPMS_SUSPEND       (1<<10)
 282 #define ADPA_DPMS_STANDBY       (2<<10)
 283 #define ADPA_DPMS_OFF           (3<<10)
 284
 285 #define NOPID                   0x2094
 286 #define LP_RING                 0x2030
 287 #define HP_RING                 0x2040
 288 #define RING_TAIL               0x00
 289 #define TAIL_ADDR               0x001FFFF8
 290 #define RING_HEAD               0x04
 291 #define HEAD_WRAP_COUNT         0xFFE00000
 292 #define HEAD_WRAP_ONE           0x00200000
 293 #define HEAD_ADDR               0x001FFFFC
 294 #define RING_START              0x08
 295 #define START_ADDR              0x0xFFFFF000
 296 #define RING_LEN                0x0C
 297 #define RING_NR_PAGES           0x001FF000
 298 #define RING_REPORT_MASK        0x00000006
 299 #define RING_REPORT_64K         0x00000002
 300 #define RING_REPORT_128K        0x00000004
 301 #define RING_NO_REPORT          0x00000000
 302 #define RING_VALID_MASK         0x00000001
 303 #define RING_VALID              0x00000001
 304 #define RING_INVALID            0x00000000
 305
 306 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 307 #define SC_UPDATE_SCISSOR       (0x1<<1)
 308 #define SC_ENABLE_MASK          (0x1<<0)
 309 #define SC_ENABLE               (0x1<<0)
 310
 311 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 312 #define SCI_YMIN_MASK      (0xffff<<16)
 313 #define SCI_XMIN_MASK      (0xffff<<0)
 314 #define SCI_YMAX_MASK      (0xffff<<16)
 315 #define SCI_XMAX_MASK      (0xffff<<0)
 316
 317 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 318 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 319 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 320 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 321 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 322 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 323 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 324
 325 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
 326
 327 #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
 328 #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
 329 #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
 330
 331 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 332 #define MI_BATCH_BUFFER_START   (0x31<<23)
 333 #define MI_BATCH_BUFFER_END     (0xA<<23)
 334 #define MI_BATCH_NON_SECURE     (1)
 335
 336 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 337 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 338 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 339
 340 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 341
 342 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 343 #define ASYNC_FLIP                (1<<22)
 344
 345 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 346
 347 #define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
 348 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 349 #endif