shared-core/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 /* General customization:
  34  */
  35
  36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  37
  38 #define DRIVER_NAME             "i915"
  39 #define DRIVER_DESC             "Intel Graphics"
  40 #define DRIVER_DATE             "20060929"
  41
  42 /* Interface history:
  43  *
  44  * 1.1: Original.
  45  * 1.2: Add Power Management
  46  * 1.3: Add vblank support
  47  * 1.4: Fix cmdbuffer path, add heap destroy
  48  * 1.5: Add vblank pipe configuration
  49  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  50  *      - Support vertical blank on secondary display pipe
  51  * 1.8: New ioctl for ARB_Occlusion_Query
  52  */
  53 #define DRIVER_MAJOR            1
  54 #define DRIVER_MINOR            8
  55 #define DRIVER_PATCHLEVEL       0
  56
  57 #if defined(__linux__)
  58 #define I915_HAVE_FENCE
  59 #define I915_HAVE_BUFFER
  60 #endif
  61
  62 typedef struct _drm_i915_ring_buffer {
  63         int tail_mask;
  64         unsigned long Start;
  65         unsigned long End;
  66         unsigned long Size;
  67         u8 *virtual_start;
  68         int head;
  69         int tail;
  70         int space;
  71         drm_local_map_t map;
  72 } drm_i915_ring_buffer_t;
  73
  74 struct mem_block {
  75         struct mem_block *next;
  76         struct mem_block *prev;
  77         int start;
  78         int size;
  79         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  80 };
  81
  82 typedef struct _drm_i915_vbl_swap {
  83         struct list_head head;
  84         drm_drawable_t drw_id;
  85         unsigned int pipe;
  86         unsigned int sequence;
  87 } drm_i915_vbl_swap_t;
  88
  89 typedef struct drm_i915_private {
  90         drm_local_map_t *sarea;
  91         drm_local_map_t *mmio_map;
  92
  93         drm_i915_sarea_t *sarea_priv;
  94         drm_i915_ring_buffer_t ring;
  95
  96         drm_dma_handle_t *status_page_dmah;
  97         void *hw_status_page;
  98         dma_addr_t dma_status_page;
  99         uint32_t counter;
 100
 101         unsigned int cpp;
 102         int back_offset;
 103         int front_offset;
 104         int current_page;
 105         int page_flipping;
 106         int use_mi_batchbuffer_start;
 107
 108         wait_queue_head_t irq_queue;
 109         atomic_t irq_received;
 110         atomic_t irq_emitted;
 111
 112         int tex_lru_log_granularity;
 113         int allow_batchbuffer;
 114         struct mem_block *agp_heap;
 115         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 116         int vblank_pipe;
 117         spinlock_t user_irq_lock;
 118         int user_irq_refcount;
 119         int fence_irq_on;
 120         uint32_t irq_enable_reg;
 121         int irq_enabled;
 122
 123 #ifdef I915_HAVE_FENCE
 124         uint32_t flush_sequence;
 125         uint32_t flush_flags;
 126         uint32_t flush_pending;
 127         uint32_t saved_flush_status;
 128 #endif
 129 #ifdef I915_HAVE_BUFFER
 130         void *agp_iomap;
 131 #endif
 132         spinlock_t swaps_lock;
 133         drm_i915_vbl_swap_t vbl_swaps;
 134         unsigned int swaps_pending;
 135 } drm_i915_private_t;
 136
 137 extern drm_ioctl_desc_t i915_ioctls[];
 138 extern int i915_max_ioctl;
 139
 140                                 /* i915_dma.c */
 141 extern void i915_kernel_lost_context(drm_device_t * dev);
 142 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 143 extern void i915_driver_lastclose(drm_device_t * dev);
 144 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
 145 extern int i915_driver_device_is_agp(drm_device_t * dev);
 146 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 147                               unsigned long arg);
 148 extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
 149
 150
 151 /* i915_irq.c */
 152 extern int i915_irq_emit(DRM_IOCTL_ARGS);
 153 extern int i915_irq_wait(DRM_IOCTL_ARGS);
 154
 155 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
 156 extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);
 157 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 158 extern void i915_driver_irq_preinstall(drm_device_t * dev);
 159 extern void i915_driver_irq_postinstall(drm_device_t * dev);
 160 extern void i915_driver_irq_uninstall(drm_device_t * dev);
 161 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
 162 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
 163 extern int i915_emit_irq(drm_device_t * dev);
 164 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
 165 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
 166 extern int i915_vblank_swap(DRM_IOCTL_ARGS);
 167
 168 /* i915_mem.c */
 169 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 170 extern int i915_mem_free(DRM_IOCTL_ARGS);
 171 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 172 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
 173 extern void i915_mem_takedown(struct mem_block **heap);
 174 extern void i915_mem_release(drm_device_t * dev,
 175                              DRMFILE filp, struct mem_block *heap);
 176 #ifdef I915_HAVE_FENCE
 177 /* i915_fence.c */
 178
 179
 180 extern void i915_fence_handler(drm_device_t *dev);
 181 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t flags,
 182                                     uint32_t *sequence,
 183                                     uint32_t *native_type);
 184 extern void i915_poke_flush(drm_device_t *dev);
 185 #endif
 186
 187 #ifdef I915_HAVE_BUFFER
 188 /* i915_buffer.c */
 189 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev);
 190 extern int i915_fence_types(uint32_t buffer_flags, uint32_t *class, uint32_t *type);
 191 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
 192 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type,
 193                                drm_mem_type_manager_t *man);
 194 extern uint32_t i915_evict_flags(drm_device_t *dev, uint32_t type);
 195 extern int i915_move(drm_buffer_object_t *bo, int evict,
 196                 int no_wait, drm_bo_mem_reg_t *new_mem);
 197
 198 #endif
 199
 200 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 201 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 202 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 203 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 204
 205 #define I915_VERBOSE 0
 206
 207 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 208                         volatile char *virt;
 209
 210 #define BEGIN_LP_RING(n) do {                           \
 211         if (I915_VERBOSE)                               \
 212                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 213                                  (n), __FUNCTION__);           \
 214         if (dev_priv->ring.space < (n)*4)                      \
 215                 i915_wait_ring(dev, (n)*4, __FUNCTION__);      \
 216         outcount = 0;                                   \
 217         outring = dev_priv->ring.tail;                  \
 218         ringmask = dev_priv->ring.tail_mask;            \
 219         virt = dev_priv->ring.virtual_start;            \
 220 } while (0)
 221
 222 #define OUT_RING(n) do {                                        \
 223         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 224         *(volatile unsigned int *)(virt + outring) = (n);               \
 225         outcount++;                                             \
 226         outring += 4;                                           \
 227         outring &= ringmask;                                    \
 228 } while (0)
 229
 230 #define ADVANCE_LP_RING() do {                                          \
 231         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 232         dev_priv->ring.tail = outring;                                  \
 233         dev_priv->ring.space -= outcount * 4;                           \
 234         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 235 } while(0)
 236
 237 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 238
 239 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 240 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 241 #define CMD_REPORT_HEAD                 (7<<23)
 242 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 243 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 244
 245 #define INST_PARSER_CLIENT   0x00000000
 246 #define INST_OP_FLUSH        0x02000000
 247 #define INST_FLUSH_MAP_CACHE 0x00000001
 248
 249 #define CMD_MI_FLUSH         (0x04 << 23)
 250 #define MI_NO_WRITE_FLUSH    (1 << 2)
 251 #define MI_READ_FLUSH        (1 << 0)
 252 #define MI_EXE_FLUSH         (1 << 1)
 253
 254 #define BB1_START_ADDR_MASK   (~0x7)
 255 #define BB1_PROTECTED         (1<<0)
 256 #define BB1_UNPROTECTED       (0<<0)
 257 #define BB2_END_ADDR_MASK     (~0x7)
 258
 259 #define I915REG_HWSTAM          0x02098
 260 #define I915REG_INT_IDENTITY_R  0x020a4
 261 #define I915REG_INT_MASK_R      0x020a8
 262 #define I915REG_INT_ENABLE_R    0x020a0
 263 #define I915REG_INSTPM          0x020c0
 264
 265 #define I915REG_PIPEASTAT       0x70024
 266 #define I915REG_PIPEBSTAT       0x71024
 267
 268 #define I915_VBLANK_INTERRUPT_ENABLE    (1UL<<17)
 269 #define I915_VBLANK_CLEAR               (1UL<<1)
 270
 271 #define SRX_INDEX               0x3c4
 272 #define SRX_DATA                0x3c5
 273 #define SR01                    1
 274 #define SR01_SCREEN_OFF         (1<<5)
 275
 276 #define PPCR                    0x61204
 277 #define PPCR_ON                 (1<<0)
 278
 279 #define DVOB                    0x61140
 280 #define DVOB_ON                 (1<<31)
 281 #define DVOC                    0x61160
 282 #define DVOC_ON                 (1<<31)
 283 #define LVDS                    0x61180
 284 #define LVDS_ON                 (1<<31)
 285
 286 #define ADPA                    0x61100
 287 #define ADPA_DPMS_MASK          (~(3<<10))
 288 #define ADPA_DPMS_ON            (0<<10)
 289 #define ADPA_DPMS_SUSPEND       (1<<10)
 290 #define ADPA_DPMS_STANDBY       (2<<10)
 291 #define ADPA_DPMS_OFF           (3<<10)
 292
 293 #define NOPID                   0x2094
 294 #define LP_RING                 0x2030
 295 #define HP_RING                 0x2040
 296 #define RING_TAIL               0x00
 297 #define TAIL_ADDR               0x001FFFF8
 298 #define RING_HEAD               0x04
 299 #define HEAD_WRAP_COUNT         0xFFE00000
 300 #define HEAD_WRAP_ONE           0x00200000
 301 #define HEAD_ADDR               0x001FFFFC
 302 #define RING_START              0x08
 303 #define START_ADDR              0x0xFFFFF000
 304 #define RING_LEN                0x0C
 305 #define RING_NR_PAGES           0x001FF000
 306 #define RING_REPORT_MASK        0x00000006
 307 #define RING_REPORT_64K         0x00000002
 308 #define RING_REPORT_128K        0x00000004
 309 #define RING_NO_REPORT          0x00000000
 310 #define RING_VALID_MASK         0x00000001
 311 #define RING_VALID              0x00000001
 312 #define RING_INVALID            0x00000000
 313
 314 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 315 #define SC_UPDATE_SCISSOR       (0x1<<1)
 316 #define SC_ENABLE_MASK          (0x1<<0)
 317 #define SC_ENABLE               (0x1<<0)
 318
 319 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 320 #define SCI_YMIN_MASK      (0xffff<<16)
 321 #define SCI_XMIN_MASK      (0xffff<<0)
 322 #define SCI_YMAX_MASK      (0xffff<<16)
 323 #define SCI_XMAX_MASK      (0xffff<<0)
 324
 325 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 326 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 327 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 328 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 329 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 330 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 331 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 332
 333 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
 334
 335 #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
 336 #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
 337 #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
 338 #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
 339
 340 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 341 #define MI_BATCH_BUFFER_START   (0x31<<23)
 342 #define MI_BATCH_BUFFER_END     (0xA<<23)
 343 #define MI_BATCH_NON_SECURE     (1)
 344
 345 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 346 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 347 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 348
 349 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 350
 351 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 352 #define ASYNC_FLIP                (1<<22)
 353
 354 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 355
 356 #define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
 357 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 358 #endif