shared-core/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /**************************************************************************
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  **************************************************************************/
   9
  10 #ifndef _I915_DRV_H_
  11 #define _I915_DRV_H_
  12
  13 /* General customization:
  14  */
  15
  16 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  17
  18 #define DRIVER_NAME             "i915"
  19 #define DRIVER_DESC             "Intel Graphics"
  20 #define DRIVER_DATE             "20041217"
  21
  22 /* Interface history:
  23  *
  24  * 1.1: Original.
  25  * 1.2: Add Power Management
  26  */
  27 #define DRIVER_MAJOR            1
  28 #define DRIVER_MINOR            2
  29 #define DRIVER_PATCHLEVEL       0
  30
  31 typedef struct _drm_i915_ring_buffer {
  32         int tail_mask;
  33         unsigned long Start;
  34         unsigned long End;
  35         unsigned long Size;
  36         u8 *virtual_start;
  37         int head;
  38         int tail;
  39         int space;
  40         drm_local_map_t map;
  41 } drm_i915_ring_buffer_t;
  42
  43 struct mem_block {
  44         struct mem_block *next;
  45         struct mem_block *prev;
  46         int start;
  47         int size;
  48         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  49 };
  50
  51 typedef struct drm_i915_private {
  52         drm_local_map_t *sarea;
  53         drm_local_map_t *mmio_map;
  54
  55         drm_i915_sarea_t *sarea_priv;
  56         drm_i915_ring_buffer_t ring;
  57
  58         drm_dma_handle_t *status_page_dmah;
  59         void *hw_status_page;
  60         dma_addr_t dma_status_page;
  61         unsigned long counter;
  62
  63         int back_offset;
  64         int front_offset;
  65         int current_page;
  66         int page_flipping;
  67         int use_mi_batchbuffer_start;
  68
  69         wait_queue_head_t irq_queue;
  70         atomic_t irq_received;
  71         atomic_t irq_emitted;
  72
  73         int tex_lru_log_granularity;
  74         int allow_batchbuffer;
  75         struct mem_block *agp_heap;
  76         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  77 } drm_i915_private_t;
  78
  79                                 /* i915_dma.c */
  80 extern void i915_kernel_lost_context(drm_device_t * dev);
  81 extern void i915_driver_pretakedown(drm_device_t * dev);
  82 extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
  83 extern int i915_driver_device_is_agp(drm_device_t * dev);
  84
  85 /* i915_irq.c */
  86 extern int i915_irq_emit(DRM_IOCTL_ARGS);
  87 extern int i915_irq_wait(DRM_IOCTL_ARGS);
  88
  89 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  90 extern void i915_driver_irq_preinstall(drm_device_t * dev);
  91 extern void i915_driver_irq_postinstall(drm_device_t * dev);
  92 extern void i915_driver_irq_uninstall(drm_device_t * dev);
  93
  94 /* i915_pm.c */
  95 extern int i915_suspend(struct pci_dev *pdev, u32 state);
  96 extern int i915_resume(struct pci_dev *pdev);
  97 extern int i915_power(drm_device_t *dev, unsigned int state);
  98
  99 /* i915_mem.c */
 100 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 101 extern int i915_mem_free(DRM_IOCTL_ARGS);
 102 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 103 extern void i915_mem_takedown(struct mem_block **heap);
 104 extern void i915_mem_release(drm_device_t * dev,
 105                              DRMFILE filp, struct mem_block *heap);
 106
 107 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 108 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 109 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 110 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 111
 112 #define I915_VERBOSE 0
 113
 114 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 115                         volatile char *virt;
 116
 117 #define BEGIN_LP_RING(n) do {                           \
 118         if (I915_VERBOSE)                               \
 119                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 120                           n, __FUNCTION__);             \
 121         if (dev_priv->ring.space < n*4)                 \
 122                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 123         outcount = 0;                                   \
 124         outring = dev_priv->ring.tail;                  \
 125         ringmask = dev_priv->ring.tail_mask;            \
 126         virt = dev_priv->ring.virtual_start;            \
 127 } while (0)
 128
 129 #define OUT_RING(n) do {                                        \
 130         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 131         *(volatile unsigned int *)(virt + outring) = n;         \
 132         outcount++;                                             \
 133         outring += 4;                                           \
 134         outring &= ringmask;                                    \
 135 } while (0)
 136
 137 #define ADVANCE_LP_RING() do {                                          \
 138         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 139         dev_priv->ring.tail = outring;                                  \
 140         dev_priv->ring.space -= outcount * 4;                           \
 141         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 142 } while(0)
 143
 144 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 145
 146 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 147 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 148 #define CMD_REPORT_HEAD                 (7<<23)
 149 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 150 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 151
 152 #define INST_PARSER_CLIENT   0x00000000
 153 #define INST_OP_FLUSH        0x02000000
 154 #define INST_FLUSH_MAP_CACHE 0x00000001
 155
 156 #define BB1_START_ADDR_MASK   (~0x7)
 157 #define BB1_PROTECTED         (1<<0)
 158 #define BB1_UNPROTECTED       (0<<0)
 159 #define BB2_END_ADDR_MASK     (~0x7)
 160
 161 #define I915REG_HWSTAM          0x02098
 162 #define I915REG_INT_IDENTITY_R  0x020a4
 163 #define I915REG_INT_MASK_R      0x020a8
 164 #define I915REG_INT_ENABLE_R    0x020a0
 165
 166 #define SRX_INDEX               0x3c4
 167 #define SRX_DATA                0x3c5
 168 #define SR01                    1
 169 #define SR01_SCREEN_OFF         (1<<5)
 170
 171 #define PPCR                    0x61204
 172 #define PPCR_ON                 (1<<0)
 173
 174 #define DVOB                    0x61140
 175 #define DVOB_ON                 (1<<31)
 176 #define DVOC                    0x61160
 177 #define DVOC_ON                 (1<<31)
 178 #define LVDS                    0x61180
 179 #define LVDS_ON                 (1<<31)
 180
 181 #define ADPA                    0x61100
 182 #define ADPA_DPMS_MASK          (~(3<<10))
 183 #define ADPA_DPMS_ON            (0<<10)
 184 #define ADPA_DPMS_SUSPEND       (1<<10)
 185 #define ADPA_DPMS_STANDBY       (2<<10)
 186 #define ADPA_DPMS_OFF           (3<<10)
 187
 188 #define NOPID                   0x2094
 189 #define LP_RING                 0x2030
 190 #define HP_RING                 0x2040
 191 #define RING_TAIL               0x00
 192 #define TAIL_ADDR               0x001FFFF8
 193 #define RING_HEAD               0x04
 194 #define HEAD_WRAP_COUNT         0xFFE00000
 195 #define HEAD_WRAP_ONE           0x00200000
 196 #define HEAD_ADDR               0x001FFFFC
 197 #define RING_START              0x08
 198 #define START_ADDR              0x0xFFFFF000
 199 #define RING_LEN                0x0C
 200 #define RING_NR_PAGES           0x001FF000
 201 #define RING_REPORT_MASK        0x00000006
 202 #define RING_REPORT_64K         0x00000002
 203 #define RING_REPORT_128K        0x00000004
 204 #define RING_NO_REPORT          0x00000000
 205 #define RING_VALID_MASK         0x00000001
 206 #define RING_VALID              0x00000001
 207 #define RING_INVALID            0x00000000
 208
 209 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 210 #define SC_UPDATE_SCISSOR       (0x1<<1)
 211 #define SC_ENABLE_MASK          (0x1<<0)
 212 #define SC_ENABLE               (0x1<<0)
 213
 214 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 215 #define SCI_YMIN_MASK      (0xffff<<16)
 216 #define SCI_XMIN_MASK      (0xffff<<0)
 217 #define SCI_YMAX_MASK      (0xffff<<16)
 218 #define SCI_XMAX_MASK      (0xffff<<0)
 219
 220 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 221 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 222 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 223 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 224 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 225 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 226 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 227
 228 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 229 #define MI_BATCH_BUFFER_START   (0x31<<23)
 230 #define MI_BATCH_BUFFER_END     (0xA<<23)
 231 #define MI_BATCH_NON_SECURE     (1)
 232
 233 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 234 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 235 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 236
 237 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 238
 239 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 240 #define ASYNC_FLIP                (1<<22)
 241
 242 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 243
 244 #endif