shared-core/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /**************************************************************************
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  **************************************************************************/
   9
  10 #ifndef _I915_DRV_H_
  11 #define _I915_DRV_H_
  12
  13 /* General customization:
  14  */
  15
  16 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  17
  18 #define DRIVER_NAME             "i915"
  19 #define DRIVER_DESC             "Intel Graphics"
  20 #define DRIVER_DATE             "20041217"
  21
  22 /* Interface history:
  23  *
  24  * 1.1: Original.
  25  * 1.2: Add Power Management
  26  */
  27 #define DRIVER_MAJOR            1
  28 #define DRIVER_MINOR            2
  29 #define DRIVER_PATCHLEVEL       0
  30
  31 typedef struct _drm_i915_ring_buffer {
  32         int tail_mask;
  33         unsigned long Start;
  34         unsigned long End;
  35         unsigned long Size;
  36         u8 *virtual_start;
  37         int head;
  38         int tail;
  39         int space;
  40         drm_local_map_t map;
  41 } drm_i915_ring_buffer_t;
  42
  43 struct mem_block {
  44         struct mem_block *next;
  45         struct mem_block *prev;
  46         int start;
  47         int size;
  48         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  49 };
  50
  51 typedef struct drm_i915_private {
  52         drm_local_map_t *sarea;
  53         drm_local_map_t *mmio_map;
  54
  55         drm_i915_sarea_t *sarea_priv;
  56         drm_i915_ring_buffer_t ring;
  57
  58         void *hw_status_page;
  59         unsigned long counter;
  60         dma_addr_t dma_status_page;
  61
  62         int back_offset;
  63         int front_offset;
  64         int current_page;
  65         int page_flipping;
  66         int use_mi_batchbuffer_start;
  67
  68         wait_queue_head_t irq_queue;
  69         atomic_t irq_received;
  70         atomic_t irq_emitted;
  71
  72         int tex_lru_log_granularity;
  73         int allow_batchbuffer;
  74         struct mem_block *agp_heap;
  75 } drm_i915_private_t;
  76
  77                                 /* i915_dma.c */
  78 extern void i915_kernel_lost_context(drm_device_t * dev);
  79 extern void i915_driver_pretakedown(drm_device_t * dev);
  80 extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp);
  81
  82 /* i915_irq.c */
  83 extern int i915_irq_emit(DRM_IOCTL_ARGS);
  84 extern int i915_irq_wait(DRM_IOCTL_ARGS);
  85
  86 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  87 extern void i915_driver_irq_preinstall(drm_device_t * dev);
  88 extern void i915_driver_irq_postinstall(drm_device_t * dev);
  89 extern void i915_driver_irq_uninstall(drm_device_t * dev);
  90
  91 /* i915_mem.c */
  92 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
  93 extern int i915_mem_free(DRM_IOCTL_ARGS);
  94 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
  95 extern void i915_mem_takedown(struct mem_block **heap);
  96 extern void i915_mem_release(drm_device_t * dev,
  97                              DRMFILE filp, struct mem_block *heap);
  98
  99 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, reg)
 100 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, reg, val)
 101 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, reg)
 102 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, reg, val)
 103
 104 #define I915_VERBOSE 0
 105
 106 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 107                         volatile char *virt;
 108
 109 #define BEGIN_LP_RING(n) do {                           \
 110         if (I915_VERBOSE)                               \
 111                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 112                           n, __FUNCTION__);             \
 113         if (dev_priv->ring.space < n*4)                 \
 114                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 115         outcount = 0;                                   \
 116         outring = dev_priv->ring.tail;                  \
 117         ringmask = dev_priv->ring.tail_mask;            \
 118         virt = dev_priv->ring.virtual_start;            \
 119 } while (0)
 120
 121 #define OUT_RING(n) do {                                        \
 122         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 123         *(volatile unsigned int *)(virt + outring) = n;         \
 124         outcount++;                                             \
 125         outring += 4;                                           \
 126         outring &= ringmask;                                    \
 127 } while (0)
 128
 129 #define ADVANCE_LP_RING() do {                                          \
 130         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 131         dev_priv->ring.tail = outring;                                  \
 132         dev_priv->ring.space -= outcount * 4;                           \
 133         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 134 } while(0)
 135
 136 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 137
 138 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 139 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 140 #define CMD_REPORT_HEAD                 (7<<23)
 141 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 142 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 143
 144 #define INST_PARSER_CLIENT   0x00000000
 145 #define INST_OP_FLUSH        0x02000000
 146 #define INST_FLUSH_MAP_CACHE 0x00000001
 147
 148 #define BB1_START_ADDR_MASK   (~0x7)
 149 #define BB1_PROTECTED         (1<<0)
 150 #define BB1_UNPROTECTED       (0<<0)
 151 #define BB2_END_ADDR_MASK     (~0x7)
 152
 153 #define I915REG_HWSTAM          0x02098
 154 #define I915REG_INT_IDENTITY_R  0x020a4
 155 #define I915REG_INT_MASK_R      0x020a8
 156 #define I915REG_INT_ENABLE_R    0x020a0
 157
 158 #define SRX_INDEX               0x3c4
 159 #define SRX_DATA                0x3c5
 160 #define SR01                    1
 161 #define SR01_SCREEN_OFF         (1<<5)
 162
 163 #define PPCR                    0x61204
 164 #define PPCR_ON                 (1<<0)
 165
 166 #define ADPA                    0x61100
 167 #define ADPA_DPMS_MASK          (~(3<<10))
 168 #define ADPA_DPMS_ON            (0<<10)
 169 #define ADPA_DPMS_SUSPEND       (1<<10)
 170 #define ADPA_DPMS_STANDBY       (2<<10)
 171 #define ADPA_DPMS_OFF           (3<<10)
 172
 173 #define NOPID                   0x2094
 174 #define LP_RING                 0x2030
 175 #define HP_RING                 0x2040
 176 #define RING_TAIL               0x00
 177 #define TAIL_ADDR               0x001FFFF8
 178 #define RING_HEAD               0x04
 179 #define HEAD_WRAP_COUNT         0xFFE00000
 180 #define HEAD_WRAP_ONE           0x00200000
 181 #define HEAD_ADDR               0x001FFFFC
 182 #define RING_START              0x08
 183 #define START_ADDR              0x0xFFFFF000
 184 #define RING_LEN                0x0C
 185 #define RING_NR_PAGES           0x001FF000
 186 #define RING_REPORT_MASK        0x00000006
 187 #define RING_REPORT_64K         0x00000002
 188 #define RING_REPORT_128K        0x00000004
 189 #define RING_NO_REPORT          0x00000000
 190 #define RING_VALID_MASK         0x00000001
 191 #define RING_VALID              0x00000001
 192 #define RING_INVALID            0x00000000
 193
 194 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 195 #define SC_UPDATE_SCISSOR       (0x1<<1)
 196 #define SC_ENABLE_MASK          (0x1<<0)
 197 #define SC_ENABLE               (0x1<<0)
 198
 199 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 200 #define SCI_YMIN_MASK      (0xffff<<16)
 201 #define SCI_XMIN_MASK      (0xffff<<0)
 202 #define SCI_YMAX_MASK      (0xffff<<16)
 203 #define SCI_XMAX_MASK      (0xffff<<0)
 204
 205 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 206 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 207 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 208 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 209 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 210 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 211 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 212
 213 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 214 #define MI_BATCH_BUFFER_START   (0x31<<23)
 215 #define MI_BATCH_BUFFER_END     (0xA<<23)
 216 #define MI_BATCH_NON_SECURE     (1)
 217
 218 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 219 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 220 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 221
 222 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 223
 224 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 225 #define ASYNC_FLIP                (1<<22)
 226
 227 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 228
 229 #endif