1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 /* General customization:
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20070209"
42 #if defined(__linux__)
43 #define I915_HAVE_FENCE
44 #define I915_HAVE_BUFFER
50 * 1.2: Add Power Management
51 * 1.3: Add vblank support
52 * 1.4: Fix cmdbuffer path, add heap destroy
53 * 1.5: Add vblank pipe configuration
54 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
55 * - Support vertical blank on secondary display pipe
56 * 1.8: New ioctl for ARB_Occlusion_Query
57 * 1.9: Usable page flipping and triple buffering
58 * 1.10: Plane/pipe disentangling
59 * 1.11: TTM superioctl
61 #define DRIVER_MAJOR 1
62 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
63 #define DRIVER_MINOR 11
65 #define DRIVER_MINOR 6
67 #define DRIVER_PATCHLEVEL 0
69 #ifdef I915_HAVE_BUFFER
70 #define I915_MAX_VALIDATE_BUFFERS 4096
73 typedef struct _drm_i915_ring_buffer {
83 } drm_i915_ring_buffer_t;
86 struct mem_block *next;
87 struct mem_block *prev;
90 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
93 typedef struct _drm_i915_vbl_swap {
94 struct list_head head;
95 drm_drawable_t drw_id;
97 unsigned int sequence;
99 } drm_i915_vbl_swap_t;
101 typedef struct drm_i915_private {
102 drm_local_map_t *sarea;
103 drm_local_map_t *mmio_map;
105 drm_i915_sarea_t *sarea_priv;
106 drm_i915_ring_buffer_t ring;
108 drm_dma_handle_t *status_page_dmah;
109 void *hw_status_page;
110 dma_addr_t dma_status_page;
112 unsigned int status_gfx_addr;
113 drm_local_map_t hws_map;
116 int use_mi_batchbuffer_start;
118 wait_queue_head_t irq_queue;
119 atomic_t irq_received;
120 atomic_t irq_emitted;
122 int tex_lru_log_granularity;
123 int allow_batchbuffer;
124 struct mem_block *agp_heap;
125 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
127 DRM_SPINTYPE user_irq_lock;
128 int user_irq_refcount;
130 uint32_t irq_enable_reg;
133 #ifdef I915_HAVE_FENCE
134 uint32_t flush_sequence;
135 uint32_t flush_flags;
136 uint32_t flush_pending;
137 uint32_t saved_flush_status;
139 #ifdef I915_HAVE_BUFFER
141 unsigned int max_validate_buffers;
142 struct mutex cmdbuf_mutex;
145 DRM_SPINTYPE swaps_lock;
146 drm_i915_vbl_swap_t vbl_swaps;
147 unsigned int swaps_pending;
174 u32 savePFIT_PGM_RATIOS;
176 u32 saveBLC_PWM_CTL2;
194 u32 saveVCLK_DIVISOR_VGA0;
195 u32 saveVCLK_DIVISOR_VGA1;
196 u32 saveVCLK_POST_DIV;
209 u32 savePFIT_CONTROL;
210 u32 save_palette_a[256];
211 u32 save_palette_b[256];
212 u32 saveFBC_CFB_BASE;
215 u32 saveFBC_CONTROL2;
225 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
227 } drm_i915_private_t;
229 enum intel_chip_family {
236 extern struct drm_ioctl_desc i915_ioctls[];
237 extern int i915_max_ioctl;
240 extern void i915_kernel_lost_context(struct drm_device * dev);
241 extern int i915_driver_load(struct drm_device *, unsigned long flags);
242 extern int i915_driver_unload(struct drm_device *);
243 extern void i915_driver_lastclose(struct drm_device * dev);
244 extern void i915_driver_preclose(struct drm_device *dev,
245 struct drm_file *file_priv);
246 extern int i915_driver_device_is_agp(struct drm_device * dev);
247 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
249 extern void i915_emit_breadcrumb(struct drm_device *dev);
250 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
251 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
252 extern int i915_driver_firstopen(struct drm_device *dev);
255 extern int i915_irq_emit(struct drm_device *dev, void *data,
256 struct drm_file *file_priv);
257 extern int i915_irq_wait(struct drm_device *dev, void *data,
258 struct drm_file *file_priv);
260 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
261 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
262 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
263 extern void i915_driver_irq_preinstall(struct drm_device * dev);
264 extern void i915_driver_irq_postinstall(struct drm_device * dev);
265 extern void i915_driver_irq_uninstall(struct drm_device * dev);
266 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
267 struct drm_file *file_priv);
268 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
269 struct drm_file *file_priv);
270 extern int i915_emit_irq(struct drm_device * dev);
271 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
272 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
273 extern int i915_vblank_swap(struct drm_device *dev, void *data,
274 struct drm_file *file_priv);
277 extern int i915_mem_alloc(struct drm_device *dev, void *data,
278 struct drm_file *file_priv);
279 extern int i915_mem_free(struct drm_device *dev, void *data,
280 struct drm_file *file_priv);
281 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
282 struct drm_file *file_priv);
283 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
284 struct drm_file *file_priv);
285 extern void i915_mem_takedown(struct mem_block **heap);
286 extern void i915_mem_release(struct drm_device * dev,
287 struct drm_file *file_priv,
288 struct mem_block *heap);
289 #ifdef I915_HAVE_FENCE
293 extern void i915_fence_handler(struct drm_device *dev);
294 extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
297 uint32_t *native_type);
298 extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
299 extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
302 #ifdef I915_HAVE_BUFFER
304 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
305 extern int i915_fence_types(struct drm_buffer_object *bo, uint32_t *fclass,
307 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
308 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
309 struct drm_mem_type_manager *man);
310 extern uint32_t i915_evict_mask(struct drm_buffer_object *bo);
311 extern int i915_move(struct drm_buffer_object *bo, int evict,
312 int no_wait, struct drm_bo_mem_reg *new_mem);
316 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
317 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
318 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
319 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
321 #define I915_VERBOSE 0
323 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
326 #define BEGIN_LP_RING(n) do { \
328 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
329 (n), __FUNCTION__); \
330 if (dev_priv->ring.space < (n)*4) \
331 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
333 outring = dev_priv->ring.tail; \
334 ringmask = dev_priv->ring.tail_mask; \
335 virt = dev_priv->ring.virtual_start; \
338 #define OUT_RING(n) do { \
339 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
340 *(volatile unsigned int *)(virt + outring) = (n); \
343 outring &= ringmask; \
346 #define ADVANCE_LP_RING() do { \
347 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
348 dev_priv->ring.tail = outring; \
349 dev_priv->ring.space -= outcount * 4; \
350 I915_WRITE(LP_RING + RING_TAIL, outring); \
353 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
355 /* Extended config space */
360 #define VGA_ST01_MDA 0x3ba
361 #define VGA_ST01_CGA 0x3da
363 #define VGA_MSR_WRITE 0x3c2
364 #define VGA_MSR_READ 0x3cc
365 #define VGA_MSR_MEM_EN (1<<1)
366 #define VGA_MSR_CGA_MODE (1<<0)
368 #define VGA_SR_INDEX 0x3c4
369 #define VGA_SR_DATA 0x3c5
371 #define VGA_AR_INDEX 0x3c0
372 #define VGA_AR_VID_EN (1<<5)
373 #define VGA_AR_DATA_WRITE 0x3c0
374 #define VGA_AR_DATA_READ 0x3c1
376 #define VGA_GR_INDEX 0x3ce
377 #define VGA_GR_DATA 0x3cf
379 #define VGA_GR_MEM_READ_MODE_SHIFT 3
380 #define VGA_GR_MEM_READ_MODE_PLANE 1
382 #define VGA_GR_MEM_MODE_MASK 0xc
383 #define VGA_GR_MEM_MODE_SHIFT 2
384 #define VGA_GR_MEM_A0000_AFFFF 0
385 #define VGA_GR_MEM_A0000_BFFFF 1
386 #define VGA_GR_MEM_B0000_B7FFF 2
387 #define VGA_GR_MEM_B0000_BFFFF 3
389 #define VGA_DACMASK 0x3c6
390 #define VGA_DACRX 0x3c7
391 #define VGA_DACWX 0x3c8
392 #define VGA_DACDATA 0x3c9
394 #define VGA_CR_INDEX_MDA 0x3b4
395 #define VGA_CR_DATA_MDA 0x3b5
396 #define VGA_CR_INDEX_CGA 0x3d4
397 #define VGA_CR_DATA_CGA 0x3d5
399 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
400 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
401 #define CMD_REPORT_HEAD (7<<23)
402 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
403 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
405 #define CMD_MI_FLUSH (0x04 << 23)
406 #define MI_NO_WRITE_FLUSH (1 << 2)
407 #define MI_READ_FLUSH (1 << 0)
408 #define MI_EXE_FLUSH (1 << 1)
409 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
410 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
412 /* Packet to load a register value from the ring/batch command stream:
414 #define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
416 #define BB1_START_ADDR_MASK (~0x7)
417 #define BB1_PROTECTED (1<<0)
418 #define BB1_UNPROTECTED (0<<0)
419 #define BB2_END_ADDR_MASK (~0x7)
421 /* Framebuffer compression */
422 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
423 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
424 #define FBC_CONTROL 0x03208
425 #define FBC_CTL_EN (1<<31)
426 #define FBC_CTL_PERIODIC (1<<30)
427 #define FBC_CTL_INTERVAL_SHIFT (16)
428 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
429 #define FBC_CTL_STRIDE_SHIFT (5)
430 #define FBC_CTL_FENCENO (1<<0)
431 #define FBC_COMMAND 0x0320c
432 #define FBC_CMD_COMPRESS (1<<0)
433 #define FBC_STATUS 0x03210
434 #define FBC_STAT_COMPRESSING (1<<31)
435 #define FBC_STAT_COMPRESSED (1<<30)
436 #define FBC_STAT_MODIFIED (1<<29)
437 #define FBC_STAT_CURRENT_LINE (1<<0)
438 #define FBC_CONTROL2 0x03214
439 #define FBC_CTL_FENCE_DBL (0<<4)
440 #define FBC_CTL_IDLE_IMM (0<<2)
441 #define FBC_CTL_IDLE_FULL (1<<2)
442 #define FBC_CTL_IDLE_LINE (2<<2)
443 #define FBC_CTL_IDLE_DEBUG (3<<2)
444 #define FBC_CTL_CPU_FENCE (1<<1)
445 #define FBC_CTL_PLANEA (0<<0)
446 #define FBC_CTL_PLANEB (1<<0)
447 #define FBC_FENCE_OFF 0x0321b
449 #define FBC_LL_SIZE (1536)
450 #define FBC_LL_PAD (32)
454 #define USER_INT_FLAG (1<<1)
455 #define VSYNC_PIPEB_FLAG (1<<5)
456 #define VSYNC_PIPEA_FLAG (1<<7)
457 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */
459 #define I915REG_HWSTAM 0x02098
460 #define I915REG_INT_IDENTITY_R 0x020a4
461 #define I915REG_INT_MASK_R 0x020a8
462 #define I915REG_INT_ENABLE_R 0x020a0
463 #define I915REG_INSTPM 0x020c0
465 #define I915REG_PIPEASTAT 0x70024
466 #define I915REG_PIPEBSTAT 0x71024
468 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
469 #define I915_VBLANK_CLEAR (1UL<<1)
471 #define SRX_INDEX 0x3c4
472 #define SRX_DATA 0x3c5
474 #define SR01_SCREEN_OFF (1<<5)
477 #define PPCR_ON (1<<0)
480 #define DVOB_ON (1<<31)
482 #define DVOC_ON (1<<31)
484 #define LVDS_ON (1<<31)
487 #define ADPA_DPMS_MASK (~(3<<10))
488 #define ADPA_DPMS_ON (0<<10)
489 #define ADPA_DPMS_SUSPEND (1<<10)
490 #define ADPA_DPMS_STANDBY (2<<10)
491 #define ADPA_DPMS_OFF (3<<10)
494 #define LP_RING 0x2030
495 #define HP_RING 0x2040
496 /* The binner has its own ring buffer:
498 #define HWB_RING 0x2400
500 #define RING_TAIL 0x00
501 #define TAIL_ADDR 0x001FFFF8
502 #define RING_HEAD 0x04
503 #define HEAD_WRAP_COUNT 0xFFE00000
504 #define HEAD_WRAP_ONE 0x00200000
505 #define HEAD_ADDR 0x001FFFFC
506 #define RING_START 0x08
507 #define START_ADDR 0x0xFFFFF000
508 #define RING_LEN 0x0C
509 #define RING_NR_PAGES 0x001FF000
510 #define RING_REPORT_MASK 0x00000006
511 #define RING_REPORT_64K 0x00000002
512 #define RING_REPORT_128K 0x00000004
513 #define RING_NO_REPORT 0x00000000
514 #define RING_VALID_MASK 0x00000001
515 #define RING_VALID 0x00000001
516 #define RING_INVALID 0x00000000
518 /* Instruction parser error reg:
522 /* Scratch pad debug 0 reg:
530 /* Secondary DMA fetch address debug reg:
532 #define DMA_FADD_S 0x20d4
535 * - Manipulating render cache behaviour is central
536 * to the concept of zone rendering, tuning this reg can help avoid
537 * unnecessary render cache reads and even writes (for z/stencil)
538 * at beginning and end of scene.
540 * - To change a bit, write to this reg with a mask bit set and the
541 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
543 #define Cache_Mode_0 0x2120
544 #define CM0_MASK_SHIFT 16
545 #define CM0_IZ_OPT_DISABLE (1<<6)
546 #define CM0_ZR_OPT_DISABLE (1<<5)
547 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
548 #define CM0_COLOR_EVICT_DISABLE (1<<3)
549 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
550 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
553 /* Graphics flush control. A CPU write flushes the GWB of all writes.
554 * The data is discarded.
556 #define GFX_FLSH_CNTL 0x2170
558 /* Binner control. Defines the location of the bin pointer list:
560 #define BINCTL 0x2420
561 #define BC_MASK (1 << 9)
563 /* Binned scene info.
565 #define BINSCENE 0x2428
566 #define BS_OP_LOAD (1 << 8)
567 #define BS_MASK (1 << 22)
569 /* Bin command parser debug reg:
573 /* Bin memory control debug reg:
577 /* Bin data cache debug reg:
581 /* Binner pointer cache debug reg:
585 /* Binner scratch pad debug reg:
587 #define BINSKPD 0x24f0
589 /* HWB scratch pad debug reg:
591 #define HWBSKPD 0x24f4
593 /* Binner memory pool reg:
595 #define BMP_BUFFER 0x2430
596 #define BMP_PAGE_SIZE_4K (0 << 10)
597 #define BMP_BUFFER_SIZE_SHIFT 1
598 #define BMP_ENABLE (1 << 0)
600 /* Get/put memory from the binner memory pool:
602 #define BMP_GET 0x2438
603 #define BMP_PUT 0x2440
604 #define BMP_OFFSET_SHIFT 5
608 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
610 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
611 #define SC_UPDATE_SCISSOR (0x1<<1)
612 #define SC_ENABLE_MASK (0x1<<0)
613 #define SC_ENABLE (0x1<<0)
615 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
617 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
618 #define SCI_YMIN_MASK (0xffff<<16)
619 #define SCI_XMIN_MASK (0xffff<<0)
620 #define SCI_YMAX_MASK (0xffff<<16)
621 #define SCI_XMAX_MASK (0xffff<<0)
623 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
624 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
625 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
626 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
627 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
628 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
629 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
631 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
633 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
634 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
635 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
636 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
638 #define MI_BATCH_BUFFER ((0x30<<23)|1)
639 #define MI_BATCH_BUFFER_START (0x31<<23)
640 #define MI_BATCH_BUFFER_END (0xA<<23)
641 #define MI_BATCH_NON_SECURE (1)
643 #define MI_BATCH_NON_SECURE_I965 (1<<8)
645 #define MI_WAIT_FOR_EVENT ((0x3<<23))
646 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
647 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
648 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
650 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
652 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
653 #define ASYNC_FLIP (1<<22)
654 #define DISPLAY_PLANE_A (0<<20)
655 #define DISPLAY_PLANE_B (1<<20)
658 #define DSPACNTR 0x70180
659 #define DSPBCNTR 0x71180
660 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
662 /* Define the region of interest for the binner:
664 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
666 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
668 #define BREADCRUMB_BITS 31
669 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
671 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
672 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
674 #define BLC_PWM_CTL 0x61254
675 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
677 #define BLC_PWM_CTL2 0x61250
679 * This is the most significant 15 bits of the number of backlight cycles in a
680 * complete cycle of the modulated backlight control.
682 * The actual value is this field multiplied by two.
684 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
685 #define BLM_LEGACY_MODE (1 << 16)
687 * This is the number of cycles out of the backlight modulation cycle for which
688 * the backlight is on.
690 * This field must be no greater than the number of cycles in the complete
691 * backlight modulation cycle.
693 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
694 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
696 #define I915_GCFGC 0xf0
697 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
698 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
699 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
700 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
702 #define I855_HPLLCC 0xc0
703 #define I855_CLOCK_CONTROL_MASK (3 << 0)
704 #define I855_CLOCK_133_200 (0 << 0)
705 #define I855_CLOCK_100_200 (1 << 0)
706 #define I855_CLOCK_100_133 (2 << 0)
707 #define I855_CLOCK_166_250 (3 << 0)
711 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
712 #define VCLK2_VCO_N 0x600a
713 #define VCLK2_VCO_DIV_SEL 0x6012
715 #define VCLK_DIVISOR_VGA0 0x6000
716 #define VCLK_DIVISOR_VGA1 0x6004
717 #define VCLK_POST_DIV 0x6010
718 /** Selects a post divisor of 4 instead of 2. */
719 # define VGA1_PD_P2_DIV_4 (1 << 15)
720 /** Overrides the p2 post divisor field */
721 # define VGA1_PD_P1_DIV_2 (1 << 13)
722 # define VGA1_PD_P1_SHIFT 8
723 /** P1 value is 2 greater than this field */
724 # define VGA1_PD_P1_MASK (0x1f << 8)
725 /** Selects a post divisor of 4 instead of 2. */
726 # define VGA0_PD_P2_DIV_4 (1 << 7)
727 /** Overrides the p2 post divisor field */
728 # define VGA0_PD_P1_DIV_2 (1 << 5)
729 # define VGA0_PD_P1_SHIFT 0
730 /** P1 value is 2 greater than this field */
731 # define VGA0_PD_P1_MASK (0x1f << 0)
733 /* I830 CRTC registers */
734 #define HTOTAL_A 0x60000
735 #define HBLANK_A 0x60004
736 #define HSYNC_A 0x60008
737 #define VTOTAL_A 0x6000c
738 #define VBLANK_A 0x60010
739 #define VSYNC_A 0x60014
740 #define PIPEASRC 0x6001c
741 #define BCLRPAT_A 0x60020
742 #define VSYNCSHIFT_A 0x60028
744 #define HTOTAL_B 0x61000
745 #define HBLANK_B 0x61004
746 #define HSYNC_B 0x61008
747 #define VTOTAL_B 0x6100c
748 #define VBLANK_B 0x61010
749 #define VSYNC_B 0x61014
750 #define PIPEBSRC 0x6101c
751 #define BCLRPAT_B 0x61020
752 #define VSYNCSHIFT_B 0x61028
754 #define PP_STATUS 0x61200
755 # define PP_ON (1 << 31)
757 * Indicates that all dependencies of the panel are on:
761 * - LVDS/DVOB/DVOC on
763 # define PP_READY (1 << 30)
764 # define PP_SEQUENCE_NONE (0 << 28)
765 # define PP_SEQUENCE_ON (1 << 28)
766 # define PP_SEQUENCE_OFF (2 << 28)
767 # define PP_SEQUENCE_MASK 0x30000000
768 #define PP_CONTROL 0x61204
769 # define POWER_TARGET_ON (1 << 0)
771 #define LVDSPP_ON 0x61208
772 #define LVDSPP_OFF 0x6120c
773 #define PP_CYCLE 0x61210
775 #define PFIT_CONTROL 0x61230
776 # define PFIT_ENABLE (1 << 31)
777 # define PFIT_PIPE_MASK (3 << 29)
778 # define PFIT_PIPE_SHIFT 29
779 # define VERT_INTERP_DISABLE (0 << 10)
780 # define VERT_INTERP_BILINEAR (1 << 10)
781 # define VERT_INTERP_MASK (3 << 10)
782 # define VERT_AUTO_SCALE (1 << 9)
783 # define HORIZ_INTERP_DISABLE (0 << 6)
784 # define HORIZ_INTERP_BILINEAR (1 << 6)
785 # define HORIZ_INTERP_MASK (3 << 6)
786 # define HORIZ_AUTO_SCALE (1 << 5)
787 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
789 #define PFIT_PGM_RATIOS 0x61234
790 # define PFIT_VERT_SCALE_MASK 0xfff00000
791 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
793 #define PFIT_AUTO_RATIOS 0x61238
796 #define DPLL_A 0x06014
797 #define DPLL_B 0x06018
798 # define DPLL_VCO_ENABLE (1 << 31)
799 # define DPLL_DVO_HIGH_SPEED (1 << 30)
800 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
801 # define DPLL_VGA_MODE_DIS (1 << 28)
802 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
803 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
804 # define DPLL_MODE_MASK (3 << 26)
805 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
806 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
807 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
808 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
809 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
810 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
812 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
813 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
815 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
817 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
818 * this field (only one bit may be set).
820 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
821 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
822 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
823 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
824 # define PLL_REF_INPUT_DREFCLK (0 << 13)
825 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
826 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
827 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
828 # define PLL_REF_INPUT_MASK (3 << 13)
829 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
831 * Parallel to Serial Load Pulse phase selection.
832 * Selects the phase for the 10X DPLL clock for the PCIe
833 * digital display port. The range is 4 to 13; 10 or more
834 * is just a flip delay. The default is 6
836 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
837 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
840 * SDVO multiplier for 945G/GM. Not used on 965.
842 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
844 # define SDVO_MULTIPLIER_MASK 0x000000ff
845 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
846 # define SDVO_MULTIPLIER_SHIFT_VGA 0
848 /** @defgroup DPLL_MD
851 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
852 #define DPLL_A_MD 0x0601c
853 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
854 #define DPLL_B_MD 0x06020
856 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
858 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
860 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
861 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
862 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
863 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
864 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
866 * SDVO/UDI pixel multiplier.
868 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
869 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
870 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
871 * dummy bytes in the datastream at an increased clock rate, with both sides of
872 * the link knowing how many bytes are fill.
874 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
875 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
876 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
877 * through an SDVO command.
879 * This register field has values of multiplication factor minus 1, with
880 * a maximum multiplier of 5 for SDVO.
882 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
883 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
884 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
885 * This best be set to the default value (3) or the CRT won't work. No,
886 * I don't entirely understand what this does...
888 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
889 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
892 #define DPLL_TEST 0x606c
893 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
894 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
895 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
896 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
897 # define DPLLB_TEST_N_BYPASS (1 << 19)
898 # define DPLLB_TEST_M_BYPASS (1 << 18)
899 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
900 # define DPLLA_TEST_N_BYPASS (1 << 3)
901 # define DPLLA_TEST_M_BYPASS (1 << 2)
902 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
905 #define ADPA_DAC_ENABLE (1<<31)
906 #define ADPA_DAC_DISABLE 0
907 #define ADPA_PIPE_SELECT_MASK (1<<30)
908 #define ADPA_PIPE_A_SELECT 0
909 #define ADPA_PIPE_B_SELECT (1<<30)
910 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
911 #define ADPA_SETS_HVPOLARITY 0
912 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
913 #define ADPA_VSYNC_CNTL_ENABLE 0
914 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
915 #define ADPA_HSYNC_CNTL_ENABLE 0
916 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
917 #define ADPA_VSYNC_ACTIVE_LOW 0
918 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
919 #define ADPA_HSYNC_ACTIVE_LOW 0
925 # define FP_N_DIV_MASK 0x003f0000
926 # define FP_N_DIV_SHIFT 16
927 # define FP_M1_DIV_MASK 0x00003f00
928 # define FP_M1_DIV_SHIFT 8
929 # define FP_M2_DIV_MASK 0x0000003f
930 # define FP_M2_DIV_SHIFT 0
933 #define PORT_HOTPLUG_EN 0x61110
934 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
935 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
936 # define TV_HOTPLUG_INT_EN (1 << 18)
937 # define CRT_HOTPLUG_INT_EN (1 << 9)
938 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
940 #define PORT_HOTPLUG_STAT 0x61114
941 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
942 # define TV_HOTPLUG_INT_STATUS (1 << 10)
943 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
944 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
945 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
946 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
947 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
948 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
950 #define SDVOB 0x61140
951 #define SDVOC 0x61160
952 #define SDVO_ENABLE (1 << 31)
953 #define SDVO_PIPE_B_SELECT (1 << 30)
954 #define SDVO_STALL_SELECT (1 << 29)
955 #define SDVO_INTERRUPT_ENABLE (1 << 26)
957 * 915G/GM SDVO pixel multiplier.
959 * Programmed value is multiplier - 1, up to 5x.
961 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
963 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
964 #define SDVO_PORT_MULTIPLY_SHIFT 23
965 #define SDVO_PHASE_SELECT_MASK (15 << 19)
966 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
967 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
968 #define SDVOC_GANG_MODE (1 << 16)
969 #define SDVO_BORDER_ENABLE (1 << 7)
970 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
971 #define SDVO_DETECTED (1 << 2)
972 /* Bits to be preserved when writing */
973 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
974 #define SDVOC_PRESERVE_MASK (1 << 17)
980 * This register controls the LVDS output enable, pipe selection, and data
983 * All of the clock/data pairs are force powered down by power sequencing.
987 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
988 * the DPLL semantics change when the LVDS is assigned to that pipe.
990 # define LVDS_PORT_EN (1 << 31)
991 /** Selects pipe B for LVDS data. Must be set on pre-965. */
992 # define LVDS_PIPEB_SELECT (1 << 30)
995 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
998 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
999 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1000 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1002 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1003 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1006 # define LVDS_A3_POWER_MASK (3 << 6)
1007 # define LVDS_A3_POWER_DOWN (0 << 6)
1008 # define LVDS_A3_POWER_UP (3 << 6)
1010 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1013 # define LVDS_CLKB_POWER_MASK (3 << 4)
1014 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1015 # define LVDS_CLKB_POWER_UP (3 << 4)
1018 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1019 * setting for whether we are in dual-channel mode. The B3 pair will
1020 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1022 # define LVDS_B0B3_POWER_MASK (3 << 2)
1023 # define LVDS_B0B3_POWER_DOWN (0 << 2)
1024 # define LVDS_B0B3_POWER_UP (3 << 2)
1026 #define PIPEACONF 0x70008
1027 #define PIPEACONF_ENABLE (1<<31)
1028 #define PIPEACONF_DISABLE 0
1029 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1030 #define I965_PIPECONF_ACTIVE (1<<30)
1031 #define PIPEACONF_SINGLE_WIDE 0
1032 #define PIPEACONF_PIPE_UNLOCKED 0
1033 #define PIPEACONF_PIPE_LOCKED (1<<25)
1034 #define PIPEACONF_PALETTE 0
1035 #define PIPEACONF_GAMMA (1<<24)
1036 #define PIPECONF_FORCE_BORDER (1<<25)
1037 #define PIPECONF_PROGRESSIVE (0 << 21)
1038 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1039 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1041 #define PIPEBCONF 0x71008
1042 #define PIPEBCONF_ENABLE (1<<31)
1043 #define PIPEBCONF_DISABLE 0
1044 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
1045 #define PIPEBCONF_DISABLE 0
1046 #define PIPEBCONF_GAMMA (1<<24)
1047 #define PIPEBCONF_PALETTE 0
1049 #define PIPEBGCMAXRED 0x71010
1050 #define PIPEBGCMAXGREEN 0x71014
1051 #define PIPEBGCMAXBLUE 0x71018
1052 #define PIPEBSTAT 0x71024
1053 #define PIPEBFRAMEHIGH 0x71040
1054 #define PIPEBFRAMEPIXEL 0x71044
1056 #define DSPACNTR 0x70180
1057 #define DSPBCNTR 0x71180
1058 #define DISPLAY_PLANE_ENABLE (1<<31)
1059 #define DISPLAY_PLANE_DISABLE 0
1060 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1061 #define DISPPLANE_GAMMA_DISABLE 0
1062 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1063 #define DISPPLANE_8BPP (0x2<<26)
1064 #define DISPPLANE_15_16BPP (0x4<<26)
1065 #define DISPPLANE_16BPP (0x5<<26)
1066 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1067 #define DISPPLANE_32BPP (0x7<<26)
1068 #define DISPPLANE_STEREO_ENABLE (1<<25)
1069 #define DISPPLANE_STEREO_DISABLE 0
1070 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1071 #define DISPPLANE_SEL_PIPE_A 0
1072 #define DISPPLANE_SEL_PIPE_B (1<<24)
1073 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1074 #define DISPPLANE_SRC_KEY_DISABLE 0
1075 #define DISPPLANE_LINE_DOUBLE (1<<20)
1076 #define DISPPLANE_NO_LINE_DOUBLE 0
1077 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1078 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1080 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1081 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1082 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1083 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1085 #define DSPABASE 0x70184
1086 #define DSPASTRIDE 0x70188
1088 #define DSPBBASE 0x71184
1089 #define DSPBADDR DSPBBASE
1090 #define DSPBSTRIDE 0x71188
1092 #define DSPAKEYVAL 0x70194
1093 #define DSPAKEYMASK 0x70198
1095 #define DSPAPOS 0x7018C /* reserved */
1096 #define DSPASIZE 0x70190
1097 #define DSPBPOS 0x7118C
1098 #define DSPBSIZE 0x71190
1100 #define DSPASURF 0x7019C
1101 #define DSPATILEOFF 0x701A4
1103 #define DSPBSURF 0x7119C
1104 #define DSPBTILEOFF 0x711A4
1106 #define VGACNTRL 0x71400
1107 # define VGA_DISP_DISABLE (1 << 31)
1108 # define VGA_2X_MODE (1 << 30)
1109 # define VGA_PIPE_B_SELECT (1 << 29)
1112 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1113 * of video memory available to the BIOS in SWF1.
1116 #define SWF0 0x71410
1119 * 855 scratch registers.
1121 #define SWF10 0x70410
1123 #define SWF30 0x72414
1126 * Overlay registers. These are overlay registers accessed via MMIO.
1127 * Those loaded via the overlay register page are defined in i830_video.c.
1129 #define OVADD 0x30000
1131 #define DOVSTA 0x30008
1132 #define OC_BUF (0x3<<20)
1134 #define OGAMC5 0x30010
1135 #define OGAMC4 0x30014
1136 #define OGAMC3 0x30018
1137 #define OGAMC2 0x3001c
1138 #define OGAMC1 0x30020
1139 #define OGAMC0 0x30024
1143 #define PALETTE_A 0x0a000
1144 #define PALETTE_B 0x0a800
1146 #define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
1147 #define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG)
1148 #define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
1149 #define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
1150 #define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG)
1152 #define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
1153 #define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG)
1154 #define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG)
1155 #define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG)
1157 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1158 (dev)->pci_device == 0x2982 || \
1159 (dev)->pci_device == 0x2992 || \
1160 (dev)->pci_device == 0x29A2 || \
1161 (dev)->pci_device == 0x2A02 || \
1162 (dev)->pci_device == 0x2A12)
1164 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1166 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1167 (dev)->pci_device == 0x29B2 || \
1168 (dev)->pci_device == 0x29D2)
1170 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1171 IS_I945GM(dev) || IS_I965G(dev))
1173 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1174 IS_I945GM(dev) || IS_I965GM(dev))
1176 #define PRIMARY_RINGBUFFER_SIZE (128*1024)