shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2)
  38
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 10000; i++) {
  53                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  54                 ring->space = ring->head - (ring->tail + 8);
  55                 if (ring->space < 0)
  56                         ring->space += ring->Size;
  57                 if (ring->space >= n)
  58                         return 0;
  59
  60                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61
  62                 if (ring->head != last_head)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66         }
  67
  68         return DRM_ERR(EBUSY);
  69 }
  70
  71 void i915_kernel_lost_context(drm_device_t * dev)
  72 {
  73         drm_i915_private_t *dev_priv = dev->dev_private;
  74         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  75
  76         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  77         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  78         ring->space = ring->head - (ring->tail + 8);
  79         if (ring->space < 0)
  80                 ring->space += ring->Size;
  81
  82         if (ring->head == ring->tail)
  83                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  84 }
  85
  86 static int i915_dma_cleanup(drm_device_t * dev)
  87 {
  88         /* Make sure interrupts are disabled here because the uninstall ioctl
  89          * may not have been called from userspace and after dev_private
  90          * is freed, it's too late.
  91          */
  92         if (dev->irq)
  93                 drm_irq_uninstall(dev);
  94
  95         if (dev->dev_private) {
  96                 drm_i915_private_t *dev_priv =
  97                     (drm_i915_private_t *) dev->dev_private;
  98
  99                 if (dev_priv->ring.virtual_start) {
 100                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 101                 }
 102
 103                 if (dev_priv->status_page_dmah) {
 104                         drm_pci_free(dev, dev_priv->status_page_dmah);
 105                         /* Need to rewrite hardware status page */
 106                         I915_WRITE(0x02080, 0x1ffff000);
 107                 }
 108
 109                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 110                          DRM_MEM_DRIVER);
 111
 112                 dev->dev_private = NULL;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int i915_initialize(drm_device_t * dev,
 119                            drm_i915_private_t * dev_priv,
 120                            drm_i915_init_t * init)
 121 {
 122         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 123
 124         DRM_GETSAREA();
 125         if (!dev_priv->sarea) {
 126                 DRM_ERROR("can not find sarea!\n");
 127                 dev->dev_private = (void *)dev_priv;
 128                 i915_dma_cleanup(dev);
 129                 return DRM_ERR(EINVAL);
 130         }
 131
 132         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 133         if (!dev_priv->mmio_map) {
 134                 dev->dev_private = (void *)dev_priv;
 135                 i915_dma_cleanup(dev);
 136                 DRM_ERROR("can not find mmio map!\n");
 137                 return DRM_ERR(EINVAL);
 138         }
 139
 140         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 141             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 142
 143         dev_priv->ring.Start = init->ring_start;
 144         dev_priv->ring.End = init->ring_end;
 145         dev_priv->ring.Size = init->ring_size;
 146         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 147
 148         dev_priv->ring.map.offset = init->ring_start;
 149         dev_priv->ring.map.size = init->ring_size;
 150         dev_priv->ring.map.type = 0;
 151         dev_priv->ring.map.flags = 0;
 152         dev_priv->ring.map.mtrr = 0;
 153
 154         drm_core_ioremap(&dev_priv->ring.map, dev);
 155
 156         if (dev_priv->ring.map.handle == NULL) {
 157                 dev->dev_private = (void *)dev_priv;
 158                 i915_dma_cleanup(dev);
 159                 DRM_ERROR("can not ioremap virtual address for"
 160                           " ring buffer\n");
 161                 return DRM_ERR(ENOMEM);
 162         }
 163
 164         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 165
 166         dev_priv->cpp = init->cpp;
 167         dev_priv->back_offset = init->back_offset;
 168         dev_priv->front_offset = init->front_offset;
 169         dev_priv->current_page = 0;
 170         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 171
 172         /* We are using separate values as placeholders for mechanisms for
 173          * private backbuffer/depthbuffer usage.
 174          */
 175         dev_priv->use_mi_batchbuffer_start = 0;
 176
 177         /* Allow hardware batchbuffers unless told otherwise.
 178          */
 179         dev_priv->allow_batchbuffer = 1;
 180
 181         /* Program Hardware Status Page */
 182         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 183             0xffffffff);
 184
 185         if (!dev_priv->status_page_dmah) {
 186                 dev->dev_private = (void *)dev_priv;
 187                 i915_dma_cleanup(dev);
 188                 DRM_ERROR("Can not allocate hardware status page\n");
 189                 return DRM_ERR(ENOMEM);
 190         }
 191         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 192         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 193
 194         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 195         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 196
 197         I915_WRITE(0x02080, dev_priv->dma_status_page);
 198         DRM_DEBUG("Enabled hardware status page\n");
 199         dev->dev_private = (void *)dev_priv;
 200 #ifdef I915_HAVE_BUFFER
 201         drm_bo_driver_init(dev);
 202 #endif
 203         return 0;
 204 }
 205
 206 static int i915_dma_resume(drm_device_t * dev)
 207 {
 208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 209
 210         DRM_DEBUG("%s\n", __FUNCTION__);
 211
 212         if (!dev_priv->sarea) {
 213                 DRM_ERROR("can not find sarea!\n");
 214                 return DRM_ERR(EINVAL);
 215         }
 216
 217         if (!dev_priv->mmio_map) {
 218                 DRM_ERROR("can not find mmio map!\n");
 219                 return DRM_ERR(EINVAL);
 220         }
 221
 222         if (dev_priv->ring.map.handle == NULL) {
 223                 DRM_ERROR("can not ioremap virtual address for"
 224                           " ring buffer\n");
 225                 return DRM_ERR(ENOMEM);
 226         }
 227
 228         /* Program Hardware Status Page */
 229         if (!dev_priv->hw_status_page) {
 230                 DRM_ERROR("Can not find hardware status page\n");
 231                 return DRM_ERR(EINVAL);
 232         }
 233         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 234
 235         I915_WRITE(0x02080, dev_priv->dma_status_page);
 236         DRM_DEBUG("Enabled hardware status page\n");
 237
 238         return 0;
 239 }
 240
 241 static int i915_dma_init(DRM_IOCTL_ARGS)
 242 {
 243         DRM_DEVICE;
 244         drm_i915_private_t *dev_priv;
 245         drm_i915_init_t init;
 246         int retcode = 0;
 247
 248         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 249                                  sizeof(init));
 250
 251         switch (init.func) {
 252         case I915_INIT_DMA:
 253                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 254                                      DRM_MEM_DRIVER);
 255                 if (dev_priv == NULL)
 256                         return DRM_ERR(ENOMEM);
 257                 retcode = i915_initialize(dev, dev_priv, &init);
 258                 break;
 259         case I915_CLEANUP_DMA:
 260                 retcode = i915_dma_cleanup(dev);
 261                 break;
 262         case I915_RESUME_DMA:
 263                 retcode = i915_dma_resume(dev);
 264                 break;
 265         default:
 266                 retcode = DRM_ERR(EINVAL);
 267                 break;
 268         }
 269
 270         return retcode;
 271 }
 272
 273 /* Implement basically the same security restrictions as hardware does
 274  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 275  *
 276  * Most of the calculations below involve calculating the size of a
 277  * particular instruction.  It's important to get the size right as
 278  * that tells us where the next instruction to check is.  Any illegal
 279  * instruction detected will be given a size of zero, which is a
 280  * signal to abort the rest of the buffer.
 281  */
 282 static int do_validate_cmd(int cmd)
 283 {
 284         switch (((cmd >> 29) & 0x7)) {
 285         case 0x0:
 286                 switch ((cmd >> 23) & 0x3f) {
 287                 case 0x0:
 288                         return 1;       /* MI_NOOP */
 289                 case 0x4:
 290                         return 1;       /* MI_FLUSH */
 291                 default:
 292                         return 0;       /* disallow everything else */
 293                 }
 294                 break;
 295         case 0x1:
 296                 return 0;       /* reserved */
 297         case 0x2:
 298                 return (cmd & 0xff) + 2;        /* 2d commands */
 299         case 0x3:
 300                 if (((cmd >> 24) & 0x1f) <= 0x18)
 301                         return 1;
 302
 303                 switch ((cmd >> 24) & 0x1f) {
 304                 case 0x1c:
 305                         return 1;
 306                 case 0x1d:
 307                         switch ((cmd >> 16) & 0xff) {
 308                         case 0x3:
 309                                 return (cmd & 0x1f) + 2;
 310                         case 0x4:
 311                                 return (cmd & 0xf) + 2;
 312                         default:
 313                                 return (cmd & 0xffff) + 2;
 314                         }
 315                 case 0x1e:
 316                         if (cmd & (1 << 23))
 317                                 return (cmd & 0xffff) + 1;
 318                         else
 319                                 return 1;
 320                 case 0x1f:
 321                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 322                                 return (cmd & 0x1ffff) + 2;
 323                         else if (cmd & (1 << 17))       /* indirect random */
 324                                 if ((cmd & 0xffff) == 0)
 325                                         return 0;       /* unknown length, too hard */
 326                                 else
 327                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 328                         else
 329                                 return 2;       /* indirect sequential */
 330                 default:
 331                         return 0;
 332                 }
 333         default:
 334                 return 0;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int validate_cmd(int cmd)
 341 {
 342         int ret = do_validate_cmd(cmd);
 343
 344 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 345
 346         return ret;
 347 }
 348
 349 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i;
 353         RING_LOCALS;
 354
 355         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 356                 return DRM_ERR(EINVAL);
 357
 358         BEGIN_LP_RING((dwords+1)&~1);
 359
 360         for (i = 0; i < dwords;) {
 361                 int cmd, sz;
 362
 363                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 364                         return DRM_ERR(EINVAL);
 365
 366                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 367                         return DRM_ERR(EINVAL);
 368
 369                 OUT_RING(cmd);
 370
 371                 while (++i, --sz) {
 372                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 373                                                          sizeof(cmd))) {
 374                                 return DRM_ERR(EINVAL);
 375                         }
 376                         OUT_RING(cmd);
 377                 }
 378         }
 379
 380         if (dwords & 1)
 381                 OUT_RING(0);
 382
 383         ADVANCE_LP_RING();
 384
 385         return 0;
 386 }
 387
 388 static int i915_emit_box(drm_device_t * dev,
 389                          drm_clip_rect_t __user * boxes,
 390                          int i, int DR1, int DR4)
 391 {
 392         drm_i915_private_t *dev_priv = dev->dev_private;
 393         drm_clip_rect_t box;
 394         RING_LOCALS;
 395
 396         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 397                 return DRM_ERR(EFAULT);
 398         }
 399
 400         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 401                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 402                           box.x1, box.y1, box.x2, box.y2);
 403                 return DRM_ERR(EINVAL);
 404         }
 405
 406         if (IS_I965G(dev)) {
 407                 BEGIN_LP_RING(4);
 408                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 409                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 410                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 411                 OUT_RING(DR4);
 412                 ADVANCE_LP_RING();
 413         } else {
 414                 BEGIN_LP_RING(6);
 415                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 416                 OUT_RING(DR1);
 417                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 418                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 419                 OUT_RING(DR4);
 420                 OUT_RING(0);
 421                 ADVANCE_LP_RING();
 422         }
 423
 424         return 0;
 425 }
 426
 427 /* XXX: Emitting the counter should really be moved to part of the IRQ
 428  * emit.  For now, do it in both places:
 429  */
 430
 431 static void i915_emit_breadcrumb(drm_device_t *dev)
 432 {
 433         drm_i915_private_t *dev_priv = dev->dev_private;
 434         RING_LOCALS;
 435
 436         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 437
 438         BEGIN_LP_RING(4);
 439         OUT_RING(CMD_STORE_DWORD_IDX);
 440         OUT_RING(20);
 441         OUT_RING(dev_priv->counter);
 442         OUT_RING(0);
 443         ADVANCE_LP_RING();
 444 #ifdef I915_HAVE_FENCE
 445         drm_fence_flush_old(dev, dev_priv->counter);
 446 #endif
 447 }
 448
 449
 450 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 451 {
 452         drm_i915_private_t *dev_priv = dev->dev_private;
 453         uint32_t flush_cmd = CMD_MI_FLUSH;
 454         RING_LOCALS;
 455
 456         flush_cmd |= flush;
 457
 458         i915_kernel_lost_context(dev);
 459
 460         BEGIN_LP_RING(4);
 461         OUT_RING(flush_cmd);
 462         OUT_RING(0);
 463         OUT_RING(0);
 464         OUT_RING(0);
 465         ADVANCE_LP_RING();
 466
 467         return 0;
 468 }
 469
 470
 471 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 472                                    drm_i915_cmdbuffer_t * cmd)
 473 {
 474         int nbox = cmd->num_cliprects;
 475         int i = 0, count, ret;
 476
 477         if (cmd->sz & 0x3) {
 478                 DRM_ERROR("alignment");
 479                 return DRM_ERR(EINVAL);
 480         }
 481
 482         i915_kernel_lost_context(dev);
 483
 484         count = nbox ? nbox : 1;
 485
 486         for (i = 0; i < count; i++) {
 487                 if (i < nbox) {
 488                         ret = i915_emit_box(dev, cmd->cliprects, i,
 489                                             cmd->DR1, cmd->DR4);
 490                         if (ret)
 491                                 return ret;
 492                 }
 493
 494                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 495                 if (ret)
 496                         return ret;
 497         }
 498
 499         i915_emit_breadcrumb( dev );
 500         return 0;
 501 }
 502
 503 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 504                                      drm_i915_batchbuffer_t * batch)
 505 {
 506         drm_i915_private_t *dev_priv = dev->dev_private;
 507         drm_clip_rect_t __user *boxes = batch->cliprects;
 508         int nbox = batch->num_cliprects;
 509         int i = 0, count;
 510         RING_LOCALS;
 511
 512         if ((batch->start | batch->used) & 0x7) {
 513                 DRM_ERROR("alignment");
 514                 return DRM_ERR(EINVAL);
 515         }
 516
 517         i915_kernel_lost_context(dev);
 518
 519         count = nbox ? nbox : 1;
 520
 521         for (i = 0; i < count; i++) {
 522                 if (i < nbox) {
 523                         int ret = i915_emit_box(dev, boxes, i,
 524                                                 batch->DR1, batch->DR4);
 525                         if (ret)
 526                                 return ret;
 527                 }
 528
 529                 if (dev_priv->use_mi_batchbuffer_start) {
 530                         BEGIN_LP_RING(2);
 531                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 532                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 533                         ADVANCE_LP_RING();
 534                 } else {
 535                         BEGIN_LP_RING(4);
 536                         OUT_RING(MI_BATCH_BUFFER);
 537                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 538                         OUT_RING(batch->start + batch->used - 4);
 539                         OUT_RING(0);
 540                         ADVANCE_LP_RING();
 541                 }
 542         }
 543
 544         i915_emit_breadcrumb( dev );
 545         return 0;
 546 }
 547
 548 static int i915_dispatch_flip(drm_device_t * dev)
 549 {
 550         drm_i915_private_t *dev_priv = dev->dev_private;
 551         RING_LOCALS;
 552
 553         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 554                   __FUNCTION__,
 555                   dev_priv->current_page,
 556                   dev_priv->sarea_priv->pf_current_page);
 557
 558         i915_kernel_lost_context(dev);
 559
 560         BEGIN_LP_RING(2);
 561         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 562         OUT_RING(0);
 563         ADVANCE_LP_RING();
 564
 565         BEGIN_LP_RING(6);
 566         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 567         OUT_RING(0);
 568         if (dev_priv->current_page == 0) {
 569                 OUT_RING(dev_priv->back_offset);
 570                 dev_priv->current_page = 1;
 571         } else {
 572                 OUT_RING(dev_priv->front_offset);
 573                 dev_priv->current_page = 0;
 574         }
 575         OUT_RING(0);
 576         ADVANCE_LP_RING();
 577
 578         BEGIN_LP_RING(2);
 579         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 580         OUT_RING(0);
 581         ADVANCE_LP_RING();
 582
 583         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 584
 585         BEGIN_LP_RING(4);
 586         OUT_RING(CMD_STORE_DWORD_IDX);
 587         OUT_RING(20);
 588         OUT_RING(dev_priv->counter);
 589         OUT_RING(0);
 590         ADVANCE_LP_RING();
 591 #ifdef I915_HAVE_FENCE
 592         drm_fence_flush_old(dev, dev_priv->counter);
 593 #endif
 594         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 595         return 0;
 596 }
 597
 598 static int i915_quiescent(drm_device_t * dev)
 599 {
 600         drm_i915_private_t *dev_priv = dev->dev_private;
 601
 602         i915_kernel_lost_context(dev);
 603         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 604 }
 605
 606 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 607 {
 608         DRM_DEVICE;
 609
 610         LOCK_TEST_WITH_RETURN(dev, filp);
 611
 612         return i915_quiescent(dev);
 613 }
 614
 615 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 616 {
 617         DRM_DEVICE;
 618         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 619         u32 *hw_status = dev_priv->hw_status_page;
 620         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 621             dev_priv->sarea_priv;
 622         drm_i915_batchbuffer_t batch;
 623         int ret;
 624
 625         if (!dev_priv->allow_batchbuffer) {
 626                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 627                 return DRM_ERR(EINVAL);
 628         }
 629
 630         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 631                                  sizeof(batch));
 632
 633         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 634                   batch.start, batch.used, batch.num_cliprects);
 635
 636         LOCK_TEST_WITH_RETURN(dev, filp);
 637
 638         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 639                                                        batch.num_cliprects *
 640                                                        sizeof(drm_clip_rect_t)))
 641                 return DRM_ERR(EFAULT);
 642
 643         ret = i915_dispatch_batchbuffer(dev, &batch);
 644
 645         sarea_priv->last_dispatch = (int)hw_status[5];
 646         return ret;
 647 }
 648
 649 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 650 {
 651         DRM_DEVICE;
 652         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 653         u32 *hw_status = dev_priv->hw_status_page;
 654         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 655             dev_priv->sarea_priv;
 656         drm_i915_cmdbuffer_t cmdbuf;
 657         int ret;
 658
 659         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 660                                  sizeof(cmdbuf));
 661
 662         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 663                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 664
 665         LOCK_TEST_WITH_RETURN(dev, filp);
 666
 667         if (cmdbuf.num_cliprects &&
 668             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 669                                 cmdbuf.num_cliprects *
 670                                 sizeof(drm_clip_rect_t))) {
 671                 DRM_ERROR("Fault accessing cliprects\n");
 672                 return DRM_ERR(EFAULT);
 673         }
 674
 675         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 676         if (ret) {
 677                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 678                 return ret;
 679         }
 680
 681         sarea_priv->last_dispatch = (int)hw_status[5];
 682         return 0;
 683 }
 684
 685 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 686 {
 687         drm_i915_private_t *dev_priv = dev->dev_private;
 688
 689         DRM_DEBUG("%s\n", __FUNCTION__);
 690         if (dev_priv->current_page != 0)
 691                 i915_dispatch_flip(dev);
 692
 693         return 0;
 694 }
 695
 696 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 697 {
 698         DRM_DEVICE;
 699
 700         DRM_DEBUG("%s\n", __FUNCTION__);
 701
 702         LOCK_TEST_WITH_RETURN(dev, filp);
 703
 704         return i915_dispatch_flip(dev);
 705 }
 706
 707
 708 static int i915_getparam(DRM_IOCTL_ARGS)
 709 {
 710         DRM_DEVICE;
 711         drm_i915_private_t *dev_priv = dev->dev_private;
 712         drm_i915_getparam_t param;
 713         int value;
 714
 715         if (!dev_priv) {
 716                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 717                 return DRM_ERR(EINVAL);
 718         }
 719
 720         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 721                                  sizeof(param));
 722
 723         switch (param.param) {
 724         case I915_PARAM_IRQ_ACTIVE:
 725                 value = dev->irq ? 1 : 0;
 726                 break;
 727         case I915_PARAM_ALLOW_BATCHBUFFER:
 728                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 729                 break;
 730         case I915_PARAM_LAST_DISPATCH:
 731                 value = READ_BREADCRUMB(dev_priv);
 732                 break;
 733         default:
 734                 DRM_ERROR("Unknown parameter %d\n", param.param);
 735                 return DRM_ERR(EINVAL);
 736         }
 737
 738         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 739                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 740                 return DRM_ERR(EFAULT);
 741         }
 742
 743         return 0;
 744 }
 745
 746 static int i915_setparam(DRM_IOCTL_ARGS)
 747 {
 748         DRM_DEVICE;
 749         drm_i915_private_t *dev_priv = dev->dev_private;
 750         drm_i915_setparam_t param;
 751
 752         if (!dev_priv) {
 753                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 754                 return DRM_ERR(EINVAL);
 755         }
 756
 757         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 758                                  sizeof(param));
 759
 760         switch (param.param) {
 761         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 762                 dev_priv->use_mi_batchbuffer_start = param.value;
 763                 break;
 764         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 765                 dev_priv->tex_lru_log_granularity = param.value;
 766                 break;
 767         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 768                 dev_priv->allow_batchbuffer = param.value;
 769                 break;
 770         default:
 771                 DRM_ERROR("unknown parameter %d\n", param.param);
 772                 return DRM_ERR(EINVAL);
 773         }
 774
 775         return 0;
 776 }
 777
 778 drm_i915_mmio_entry_t mmio_table[] = {
 779         [MMIO_REGS_PS_DEPTH_COUNT] = {
 780                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 781                 0x2350,
 782                 8
 783         }
 784 };
 785
 786 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 787
 788 static int i915_mmio(DRM_IOCTL_ARGS)
 789 {
 790         char buf[32];
 791         DRM_DEVICE;
 792         drm_i915_private_t *dev_priv = dev->dev_private;
 793         drm_i915_mmio_entry_t *e;
 794         drm_i915_mmio_t mmio;
 795         void __iomem *base;
 796         if (!dev_priv) {
 797                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 798                 return DRM_ERR(EINVAL);
 799         }
 800         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data,
 801                                  sizeof(mmio));
 802
 803         if (mmio.reg >= mmio_table_size)
 804                 return DRM_ERR(EINVAL);
 805
 806         e = &mmio_table[mmio.reg];
 807         base = dev_priv->mmio_map->handle + e->offset;
 808
 809         switch (mmio.read_write) {
 810                 case I915_MMIO_READ:
 811                         if (!(e->flag & I915_MMIO_MAY_READ))
 812                                 return DRM_ERR(EINVAL);
 813                         memcpy_fromio(buf, base, e->size);
 814                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 815                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 816                                 return DRM_ERR(EFAULT);
 817                         }
 818                         break;
 819
 820                 case I915_MMIO_WRITE:
 821                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 822                                 return DRM_ERR(EINVAL);
 823                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 824                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 825                                 return DRM_ERR(EFAULT);
 826                         }
 827                         memcpy_toio(base, buf, e->size);
 828                         break;
 829         }
 830         return 0;
 831 }
 832
 833 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 834 {
 835         /* i915 has 4 more counters */
 836         dev->counters += 4;
 837         dev->types[6] = _DRM_STAT_IRQ;
 838         dev->types[7] = _DRM_STAT_PRIMARY;
 839         dev->types[8] = _DRM_STAT_SECONDARY;
 840         dev->types[9] = _DRM_STAT_DMA;
 841
 842         return 0;
 843 }
 844
 845 void i915_driver_lastclose(drm_device_t * dev)
 846 {
 847         if (dev->dev_private) {
 848                 drm_i915_private_t *dev_priv = dev->dev_private;
 849                 i915_mem_takedown(&(dev_priv->agp_heap));
 850         }
 851         i915_dma_cleanup(dev);
 852 }
 853
 854 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 855 {
 856         if (dev->dev_private) {
 857                 drm_i915_private_t *dev_priv = dev->dev_private;
 858                 if (dev_priv->page_flipping) {
 859                         i915_do_cleanup_pageflip(dev);
 860                 }
 861                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 862         }
 863 }
 864
 865 drm_ioctl_desc_t i915_ioctls[] = {
 866         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 867         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 868         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 869         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 870         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 871         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 872         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 873         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 874         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 875         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 876         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 877         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 878         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 879         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 880         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 881         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 882         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 883 };
 884
 885 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 886
 887 /**
 888  * Determine if the device really is AGP or not.
 889  *
 890  * All Intel graphics chipsets are treated as AGP, even if they are really
 891  * PCI-e.
 892  *
 893  * \param dev   The device to be tested.
 894  *
 895  * \returns
 896  * A value of 1 is always retured to indictate every i9x5 is AGP.
 897  */
 898 int i915_driver_device_is_agp(drm_device_t * dev)
 899 {
 900         return 1;
 901 }