1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2)
40 /* Really want an OS-independent resettable timer. Would like to have
41 * this loop run for (eg) 3 sec, but have the timer reset every time
42 * the head pointer changes, so that EBUSY only happens if the ring
43 * actually stalls for (eg) 3 seconds.
45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
47 drm_i915_private_t *dev_priv = dev->dev_private;
48 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
49 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
52 for (i = 0; i < 10000; i++) {
53 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
54 ring->space = ring->head - (ring->tail + 8);
56 ring->space += ring->Size;
60 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
62 if (ring->head != last_head)
65 last_head = ring->head;
68 return DRM_ERR(EBUSY);
71 void i915_kernel_lost_context(drm_device_t * dev)
73 drm_i915_private_t *dev_priv = dev->dev_private;
74 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
76 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
77 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
78 ring->space = ring->head - (ring->tail + 8);
80 ring->space += ring->Size;
82 if (ring->head == ring->tail)
83 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
86 static int i915_dma_cleanup(drm_device_t * dev)
88 /* Make sure interrupts are disabled here because the uninstall ioctl
89 * may not have been called from userspace and after dev_private
90 * is freed, it's too late.
93 drm_irq_uninstall(dev);
95 if (dev->dev_private) {
96 drm_i915_private_t *dev_priv =
97 (drm_i915_private_t *) dev->dev_private;
99 if (dev_priv->ring.virtual_start) {
100 drm_core_ioremapfree(&dev_priv->ring.map, dev);
103 if (dev_priv->status_page_dmah) {
104 drm_pci_free(dev, dev_priv->status_page_dmah);
105 /* Need to rewrite hardware status page */
106 I915_WRITE(0x02080, 0x1ffff000);
109 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
112 dev->dev_private = NULL;
118 static int i915_initialize(drm_device_t * dev,
119 drm_i915_private_t * dev_priv,
120 drm_i915_init_t * init)
122 memset(dev_priv, 0, sizeof(drm_i915_private_t));
125 if (!dev_priv->sarea) {
126 DRM_ERROR("can not find sarea!\n");
127 dev->dev_private = (void *)dev_priv;
128 i915_dma_cleanup(dev);
129 return DRM_ERR(EINVAL);
132 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
133 if (!dev_priv->mmio_map) {
134 dev->dev_private = (void *)dev_priv;
135 i915_dma_cleanup(dev);
136 DRM_ERROR("can not find mmio map!\n");
137 return DRM_ERR(EINVAL);
140 dev_priv->sarea_priv = (drm_i915_sarea_t *)
141 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
143 dev_priv->ring.Start = init->ring_start;
144 dev_priv->ring.End = init->ring_end;
145 dev_priv->ring.Size = init->ring_size;
146 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
148 dev_priv->ring.map.offset = init->ring_start;
149 dev_priv->ring.map.size = init->ring_size;
150 dev_priv->ring.map.type = 0;
151 dev_priv->ring.map.flags = 0;
152 dev_priv->ring.map.mtrr = 0;
154 drm_core_ioremap(&dev_priv->ring.map, dev);
156 if (dev_priv->ring.map.handle == NULL) {
157 dev->dev_private = (void *)dev_priv;
158 i915_dma_cleanup(dev);
159 DRM_ERROR("can not ioremap virtual address for"
161 return DRM_ERR(ENOMEM);
164 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
166 dev_priv->cpp = init->cpp;
167 dev_priv->back_offset = init->back_offset;
168 dev_priv->front_offset = init->front_offset;
169 dev_priv->current_page = 0;
170 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
172 /* We are using separate values as placeholders for mechanisms for
173 * private backbuffer/depthbuffer usage.
175 dev_priv->use_mi_batchbuffer_start = 0;
177 /* Allow hardware batchbuffers unless told otherwise.
179 dev_priv->allow_batchbuffer = 1;
181 /* Program Hardware Status Page */
182 dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
185 if (!dev_priv->status_page_dmah) {
186 dev->dev_private = (void *)dev_priv;
187 i915_dma_cleanup(dev);
188 DRM_ERROR("Can not allocate hardware status page\n");
189 return DRM_ERR(ENOMEM);
191 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
192 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
194 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
195 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
197 I915_WRITE(0x02080, dev_priv->dma_status_page);
198 DRM_DEBUG("Enabled hardware status page\n");
199 dev->dev_private = (void *)dev_priv;
200 #ifdef I915_HAVE_BUFFER
201 drm_bo_driver_init(dev);
206 static int i915_dma_resume(drm_device_t * dev)
208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
210 DRM_DEBUG("%s\n", __FUNCTION__);
212 if (!dev_priv->sarea) {
213 DRM_ERROR("can not find sarea!\n");
214 return DRM_ERR(EINVAL);
217 if (!dev_priv->mmio_map) {
218 DRM_ERROR("can not find mmio map!\n");
219 return DRM_ERR(EINVAL);
222 if (dev_priv->ring.map.handle == NULL) {
223 DRM_ERROR("can not ioremap virtual address for"
225 return DRM_ERR(ENOMEM);
228 /* Program Hardware Status Page */
229 if (!dev_priv->hw_status_page) {
230 DRM_ERROR("Can not find hardware status page\n");
231 return DRM_ERR(EINVAL);
233 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
235 I915_WRITE(0x02080, dev_priv->dma_status_page);
236 DRM_DEBUG("Enabled hardware status page\n");
241 static int i915_dma_init(DRM_IOCTL_ARGS)
244 drm_i915_private_t *dev_priv;
245 drm_i915_init_t init;
248 DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
253 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
255 if (dev_priv == NULL)
256 return DRM_ERR(ENOMEM);
257 retcode = i915_initialize(dev, dev_priv, &init);
259 case I915_CLEANUP_DMA:
260 retcode = i915_dma_cleanup(dev);
262 case I915_RESUME_DMA:
263 retcode = i915_dma_resume(dev);
266 retcode = DRM_ERR(EINVAL);
273 /* Implement basically the same security restrictions as hardware does
274 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
276 * Most of the calculations below involve calculating the size of a
277 * particular instruction. It's important to get the size right as
278 * that tells us where the next instruction to check is. Any illegal
279 * instruction detected will be given a size of zero, which is a
280 * signal to abort the rest of the buffer.
282 static int do_validate_cmd(int cmd)
284 switch (((cmd >> 29) & 0x7)) {
286 switch ((cmd >> 23) & 0x3f) {
288 return 1; /* MI_NOOP */
290 return 1; /* MI_FLUSH */
292 return 0; /* disallow everything else */
296 return 0; /* reserved */
298 return (cmd & 0xff) + 2; /* 2d commands */
300 if (((cmd >> 24) & 0x1f) <= 0x18)
303 switch ((cmd >> 24) & 0x1f) {
307 switch ((cmd >> 16) & 0xff) {
309 return (cmd & 0x1f) + 2;
311 return (cmd & 0xf) + 2;
313 return (cmd & 0xffff) + 2;
317 return (cmd & 0xffff) + 1;
321 if ((cmd & (1 << 23)) == 0) /* inline vertices */
322 return (cmd & 0x1ffff) + 2;
323 else if (cmd & (1 << 17)) /* indirect random */
324 if ((cmd & 0xffff) == 0)
325 return 0; /* unknown length, too hard */
327 return (((cmd & 0xffff) + 1) / 2) + 1;
329 return 2; /* indirect sequential */
340 static int validate_cmd(int cmd)
342 int ret = do_validate_cmd(cmd);
344 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
349 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
351 drm_i915_private_t *dev_priv = dev->dev_private;
355 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
356 return DRM_ERR(EINVAL);
358 BEGIN_LP_RING((dwords+1)&~1);
360 for (i = 0; i < dwords;) {
363 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
364 return DRM_ERR(EINVAL);
366 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
367 return DRM_ERR(EINVAL);
372 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
374 return DRM_ERR(EINVAL);
388 static int i915_emit_box(drm_device_t * dev,
389 drm_clip_rect_t __user * boxes,
390 int i, int DR1, int DR4)
392 drm_i915_private_t *dev_priv = dev->dev_private;
396 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
397 return DRM_ERR(EFAULT);
400 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
401 DRM_ERROR("Bad box %d,%d..%d,%d\n",
402 box.x1, box.y1, box.x2, box.y2);
403 return DRM_ERR(EINVAL);
408 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
409 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
410 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
415 OUT_RING(GFX_OP_DRAWRECT_INFO);
417 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
418 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
427 /* XXX: Emitting the counter should really be moved to part of the IRQ
428 * emit. For now, do it in both places:
431 static void i915_emit_breadcrumb(drm_device_t *dev)
433 drm_i915_private_t *dev_priv = dev->dev_private;
436 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
439 OUT_RING(CMD_STORE_DWORD_IDX);
441 OUT_RING(dev_priv->counter);
444 #ifdef I915_HAVE_FENCE
445 drm_fence_flush_old(dev, dev_priv->counter);
450 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
452 drm_i915_private_t *dev_priv = dev->dev_private;
453 uint32_t flush_cmd = CMD_MI_FLUSH;
458 i915_kernel_lost_context(dev);
471 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
472 drm_i915_cmdbuffer_t * cmd)
474 int nbox = cmd->num_cliprects;
475 int i = 0, count, ret;
478 DRM_ERROR("alignment");
479 return DRM_ERR(EINVAL);
482 i915_kernel_lost_context(dev);
484 count = nbox ? nbox : 1;
486 for (i = 0; i < count; i++) {
488 ret = i915_emit_box(dev, cmd->cliprects, i,
494 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
499 i915_emit_breadcrumb( dev );
503 static int i915_dispatch_batchbuffer(drm_device_t * dev,
504 drm_i915_batchbuffer_t * batch)
506 drm_i915_private_t *dev_priv = dev->dev_private;
507 drm_clip_rect_t __user *boxes = batch->cliprects;
508 int nbox = batch->num_cliprects;
512 if ((batch->start | batch->used) & 0x7) {
513 DRM_ERROR("alignment");
514 return DRM_ERR(EINVAL);
517 i915_kernel_lost_context(dev);
519 count = nbox ? nbox : 1;
521 for (i = 0; i < count; i++) {
523 int ret = i915_emit_box(dev, boxes, i,
524 batch->DR1, batch->DR4);
529 if (dev_priv->use_mi_batchbuffer_start) {
531 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
532 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
536 OUT_RING(MI_BATCH_BUFFER);
537 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
538 OUT_RING(batch->start + batch->used - 4);
544 i915_emit_breadcrumb( dev );
548 static int i915_dispatch_flip(drm_device_t * dev)
550 drm_i915_private_t *dev_priv = dev->dev_private;
553 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
555 dev_priv->current_page,
556 dev_priv->sarea_priv->pf_current_page);
558 i915_kernel_lost_context(dev);
561 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
566 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
568 if (dev_priv->current_page == 0) {
569 OUT_RING(dev_priv->back_offset);
570 dev_priv->current_page = 1;
572 OUT_RING(dev_priv->front_offset);
573 dev_priv->current_page = 0;
579 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
583 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
586 OUT_RING(CMD_STORE_DWORD_IDX);
588 OUT_RING(dev_priv->counter);
591 #ifdef I915_HAVE_FENCE
592 drm_fence_flush_old(dev, dev_priv->counter);
594 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
598 static int i915_quiescent(drm_device_t * dev)
600 drm_i915_private_t *dev_priv = dev->dev_private;
602 i915_kernel_lost_context(dev);
603 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
606 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
610 LOCK_TEST_WITH_RETURN(dev, filp);
612 return i915_quiescent(dev);
615 static int i915_batchbuffer(DRM_IOCTL_ARGS)
618 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
619 u32 *hw_status = dev_priv->hw_status_page;
620 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
621 dev_priv->sarea_priv;
622 drm_i915_batchbuffer_t batch;
625 if (!dev_priv->allow_batchbuffer) {
626 DRM_ERROR("Batchbuffer ioctl disabled\n");
627 return DRM_ERR(EINVAL);
630 DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
633 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
634 batch.start, batch.used, batch.num_cliprects);
636 LOCK_TEST_WITH_RETURN(dev, filp);
638 if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
639 batch.num_cliprects *
640 sizeof(drm_clip_rect_t)))
641 return DRM_ERR(EFAULT);
643 ret = i915_dispatch_batchbuffer(dev, &batch);
645 sarea_priv->last_dispatch = (int)hw_status[5];
649 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
652 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
653 u32 *hw_status = dev_priv->hw_status_page;
654 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
655 dev_priv->sarea_priv;
656 drm_i915_cmdbuffer_t cmdbuf;
659 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
662 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
663 cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
665 LOCK_TEST_WITH_RETURN(dev, filp);
667 if (cmdbuf.num_cliprects &&
668 DRM_VERIFYAREA_READ(cmdbuf.cliprects,
669 cmdbuf.num_cliprects *
670 sizeof(drm_clip_rect_t))) {
671 DRM_ERROR("Fault accessing cliprects\n");
672 return DRM_ERR(EFAULT);
675 ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
677 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
681 sarea_priv->last_dispatch = (int)hw_status[5];
685 static int i915_do_cleanup_pageflip(drm_device_t * dev)
687 drm_i915_private_t *dev_priv = dev->dev_private;
689 DRM_DEBUG("%s\n", __FUNCTION__);
690 if (dev_priv->current_page != 0)
691 i915_dispatch_flip(dev);
696 static int i915_flip_bufs(DRM_IOCTL_ARGS)
700 DRM_DEBUG("%s\n", __FUNCTION__);
702 LOCK_TEST_WITH_RETURN(dev, filp);
704 return i915_dispatch_flip(dev);
708 static int i915_getparam(DRM_IOCTL_ARGS)
711 drm_i915_private_t *dev_priv = dev->dev_private;
712 drm_i915_getparam_t param;
716 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
717 return DRM_ERR(EINVAL);
720 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
723 switch (param.param) {
724 case I915_PARAM_IRQ_ACTIVE:
725 value = dev->irq ? 1 : 0;
727 case I915_PARAM_ALLOW_BATCHBUFFER:
728 value = dev_priv->allow_batchbuffer ? 1 : 0;
730 case I915_PARAM_LAST_DISPATCH:
731 value = READ_BREADCRUMB(dev_priv);
734 DRM_ERROR("Unknown parameter %d\n", param.param);
735 return DRM_ERR(EINVAL);
738 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
739 DRM_ERROR("DRM_COPY_TO_USER failed\n");
740 return DRM_ERR(EFAULT);
746 static int i915_setparam(DRM_IOCTL_ARGS)
749 drm_i915_private_t *dev_priv = dev->dev_private;
750 drm_i915_setparam_t param;
753 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
754 return DRM_ERR(EINVAL);
757 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
760 switch (param.param) {
761 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
762 dev_priv->use_mi_batchbuffer_start = param.value;
764 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
765 dev_priv->tex_lru_log_granularity = param.value;
767 case I915_SETPARAM_ALLOW_BATCHBUFFER:
768 dev_priv->allow_batchbuffer = param.value;
771 DRM_ERROR("unknown parameter %d\n", param.param);
772 return DRM_ERR(EINVAL);
778 drm_i915_mmio_entry_t mmio_table[] = {
779 [MMIO_REGS_PS_DEPTH_COUNT] = {
780 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
786 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
788 static int i915_mmio(DRM_IOCTL_ARGS)
792 drm_i915_private_t *dev_priv = dev->dev_private;
793 drm_i915_mmio_entry_t *e;
794 drm_i915_mmio_t mmio;
797 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
798 return DRM_ERR(EINVAL);
800 DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data,
803 if (mmio.reg >= mmio_table_size)
804 return DRM_ERR(EINVAL);
806 e = &mmio_table[mmio.reg];
807 base = dev_priv->mmio_map->handle + e->offset;
809 switch (mmio.read_write) {
811 if (!(e->flag & I915_MMIO_MAY_READ))
812 return DRM_ERR(EINVAL);
813 memcpy_fromio(buf, base, e->size);
814 if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
815 DRM_ERROR("DRM_COPY_TO_USER failed\n");
816 return DRM_ERR(EFAULT);
820 case I915_MMIO_WRITE:
821 if (!(e->flag & I915_MMIO_MAY_WRITE))
822 return DRM_ERR(EINVAL);
823 if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
824 DRM_ERROR("DRM_COPY_TO_USER failed\n");
825 return DRM_ERR(EFAULT);
827 memcpy_toio(base, buf, e->size);
833 int i915_driver_load(drm_device_t *dev, unsigned long flags)
835 /* i915 has 4 more counters */
837 dev->types[6] = _DRM_STAT_IRQ;
838 dev->types[7] = _DRM_STAT_PRIMARY;
839 dev->types[8] = _DRM_STAT_SECONDARY;
840 dev->types[9] = _DRM_STAT_DMA;
845 void i915_driver_lastclose(drm_device_t * dev)
847 if (dev->dev_private) {
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 i915_mem_takedown(&(dev_priv->agp_heap));
851 i915_dma_cleanup(dev);
854 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
856 if (dev->dev_private) {
857 drm_i915_private_t *dev_priv = dev->dev_private;
858 if (dev_priv->page_flipping) {
859 i915_do_cleanup_pageflip(dev);
861 i915_mem_release(dev, filp, dev_priv->agp_heap);
865 drm_ioctl_desc_t i915_ioctls[] = {
866 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
867 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
868 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
869 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
870 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
871 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
872 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
873 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
874 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
875 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
876 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
877 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
878 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
879 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
880 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
881 [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
882 [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
885 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
888 * Determine if the device really is AGP or not.
890 * All Intel graphics chipsets are treated as AGP, even if they are really
893 * \param dev The device to be tested.
896 * A value of 1 is always retured to indictate every i9x5 is AGP.
898 int i915_driver_device_is_agp(drm_device_t * dev)