1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2 || \
38 dev->pci_device == 0x2A02)
41 /* Really want an OS-independent resettable timer. Would like to have
42 * this loop run for (eg) 3 sec, but have the timer reset every time
43 * the head pointer changes, so that EBUSY only happens if the ring
44 * actually stalls for (eg) 3 seconds.
46 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
48 drm_i915_private_t *dev_priv = dev->dev_private;
49 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
50 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
53 for (i = 0; i < 10000; i++) {
54 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
55 ring->space = ring->head - (ring->tail + 8);
57 ring->space += ring->Size;
61 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
63 if (ring->head != last_head)
66 last_head = ring->head;
70 return DRM_ERR(EBUSY);
73 void i915_kernel_lost_context(drm_device_t * dev)
75 drm_i915_private_t *dev_priv = dev->dev_private;
76 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
78 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
79 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
80 ring->space = ring->head - (ring->tail + 8);
82 ring->space += ring->Size;
84 if (ring->head == ring->tail)
85 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
88 static int i915_dma_cleanup(drm_device_t * dev)
90 /* Make sure interrupts are disabled here because the uninstall ioctl
91 * may not have been called from userspace and after dev_private
92 * is freed, it's too late.
95 drm_irq_uninstall(dev);
97 if (dev->dev_private) {
98 drm_i915_private_t *dev_priv =
99 (drm_i915_private_t *) dev->dev_private;
101 if (dev_priv->ring.virtual_start) {
102 drm_core_ioremapfree(&dev_priv->ring.map, dev);
105 if (dev_priv->status_page_dmah) {
106 drm_pci_free(dev, dev_priv->status_page_dmah);
107 /* Need to rewrite hardware status page */
108 I915_WRITE(0x02080, 0x1ffff000);
111 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
114 dev->dev_private = NULL;
120 static int i915_initialize(drm_device_t * dev,
121 drm_i915_private_t * dev_priv,
122 drm_i915_init_t * init)
124 memset(dev_priv, 0, sizeof(drm_i915_private_t));
126 dev_priv->sarea = drm_getsarea(dev);
127 if (!dev_priv->sarea) {
128 DRM_ERROR("can not find sarea!\n");
129 dev->dev_private = (void *)dev_priv;
130 i915_dma_cleanup(dev);
131 return DRM_ERR(EINVAL);
134 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
135 if (!dev_priv->mmio_map) {
136 dev->dev_private = (void *)dev_priv;
137 i915_dma_cleanup(dev);
138 DRM_ERROR("can not find mmio map!\n");
139 return DRM_ERR(EINVAL);
142 dev_priv->sarea_priv = (drm_i915_sarea_t *)
143 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
145 dev_priv->ring.Start = init->ring_start;
146 dev_priv->ring.End = init->ring_end;
147 dev_priv->ring.Size = init->ring_size;
148 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
150 dev_priv->ring.map.offset = init->ring_start;
151 dev_priv->ring.map.size = init->ring_size;
152 dev_priv->ring.map.type = 0;
153 dev_priv->ring.map.flags = 0;
154 dev_priv->ring.map.mtrr = 0;
156 drm_core_ioremap(&dev_priv->ring.map, dev);
158 if (dev_priv->ring.map.handle == NULL) {
159 dev->dev_private = (void *)dev_priv;
160 i915_dma_cleanup(dev);
161 DRM_ERROR("can not ioremap virtual address for"
163 return DRM_ERR(ENOMEM);
166 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
168 dev_priv->cpp = init->cpp;
169 dev_priv->sarea_priv->pf_current_page = 0;
171 /* We are using separate values as placeholders for mechanisms for
172 * private backbuffer/depthbuffer usage.
174 dev_priv->use_mi_batchbuffer_start = 0;
176 /* Allow hardware batchbuffers unless told otherwise.
178 dev_priv->allow_batchbuffer = 1;
180 /* Enable vblank on pipe A for older X servers
182 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
184 /* Program Hardware Status Page */
185 dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
188 if (!dev_priv->status_page_dmah) {
189 dev->dev_private = (void *)dev_priv;
190 i915_dma_cleanup(dev);
191 DRM_ERROR("Can not allocate hardware status page\n");
192 return DRM_ERR(ENOMEM);
194 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
195 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
197 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
198 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
200 I915_WRITE(0x02080, dev_priv->dma_status_page);
201 DRM_DEBUG("Enabled hardware status page\n");
202 dev->dev_private = (void *)dev_priv;
206 static int i915_dma_resume(drm_device_t * dev)
208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
210 DRM_DEBUG("%s\n", __FUNCTION__);
212 if (!dev_priv->sarea) {
213 DRM_ERROR("can not find sarea!\n");
214 return DRM_ERR(EINVAL);
217 if (!dev_priv->mmio_map) {
218 DRM_ERROR("can not find mmio map!\n");
219 return DRM_ERR(EINVAL);
222 if (dev_priv->ring.map.handle == NULL) {
223 DRM_ERROR("can not ioremap virtual address for"
225 return DRM_ERR(ENOMEM);
228 /* Program Hardware Status Page */
229 if (!dev_priv->hw_status_page) {
230 DRM_ERROR("Can not find hardware status page\n");
231 return DRM_ERR(EINVAL);
233 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
235 I915_WRITE(0x02080, dev_priv->dma_status_page);
236 DRM_DEBUG("Enabled hardware status page\n");
241 static int i915_dma_init(DRM_IOCTL_ARGS)
244 drm_i915_private_t *dev_priv;
245 drm_i915_init_t init;
248 DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
253 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
255 if (dev_priv == NULL)
256 return DRM_ERR(ENOMEM);
257 retcode = i915_initialize(dev, dev_priv, &init);
259 case I915_CLEANUP_DMA:
260 retcode = i915_dma_cleanup(dev);
262 case I915_RESUME_DMA:
263 retcode = i915_dma_resume(dev);
266 retcode = DRM_ERR(EINVAL);
273 /* Implement basically the same security restrictions as hardware does
274 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
276 * Most of the calculations below involve calculating the size of a
277 * particular instruction. It's important to get the size right as
278 * that tells us where the next instruction to check is. Any illegal
279 * instruction detected will be given a size of zero, which is a
280 * signal to abort the rest of the buffer.
282 static int do_validate_cmd(int cmd)
284 switch (((cmd >> 29) & 0x7)) {
286 switch ((cmd >> 23) & 0x3f) {
288 return 1; /* MI_NOOP */
290 return 1; /* MI_FLUSH */
292 return 0; /* disallow everything else */
296 return 0; /* reserved */
298 return (cmd & 0xff) + 2; /* 2d commands */
300 if (((cmd >> 24) & 0x1f) <= 0x18)
303 switch ((cmd >> 24) & 0x1f) {
307 switch ((cmd >> 16) & 0xff) {
309 return (cmd & 0x1f) + 2;
311 return (cmd & 0xf) + 2;
313 return (cmd & 0xffff) + 2;
317 return (cmd & 0xffff) + 1;
321 if ((cmd & (1 << 23)) == 0) /* inline vertices */
322 return (cmd & 0x1ffff) + 2;
323 else if (cmd & (1 << 17)) /* indirect random */
324 if ((cmd & 0xffff) == 0)
325 return 0; /* unknown length, too hard */
327 return (((cmd & 0xffff) + 1) / 2) + 1;
329 return 2; /* indirect sequential */
340 static int validate_cmd(int cmd)
342 int ret = do_validate_cmd(cmd);
344 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
349 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
351 drm_i915_private_t *dev_priv = dev->dev_private;
355 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
356 return DRM_ERR(EINVAL);
358 BEGIN_LP_RING((dwords+1)&~1);
360 for (i = 0; i < dwords;) {
363 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
364 return DRM_ERR(EINVAL);
366 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
367 return DRM_ERR(EINVAL);
372 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
374 return DRM_ERR(EINVAL);
388 static int i915_emit_box(drm_device_t * dev,
389 drm_clip_rect_t __user * boxes,
390 int i, int DR1, int DR4)
392 drm_i915_private_t *dev_priv = dev->dev_private;
396 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
397 return DRM_ERR(EFAULT);
400 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
401 DRM_ERROR("Bad box %d,%d..%d,%d\n",
402 box.x1, box.y1, box.x2, box.y2);
403 return DRM_ERR(EINVAL);
408 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
409 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
410 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
415 OUT_RING(GFX_OP_DRAWRECT_INFO);
417 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
418 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
427 /* XXX: Emitting the counter should really be moved to part of the IRQ
428 * emit. For now, do it in both places:
431 void i915_emit_breadcrumb(drm_device_t *dev)
433 drm_i915_private_t *dev_priv = dev->dev_private;
436 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
438 if (dev_priv->counter > 0x7FFFFFFFUL)
439 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
442 OUT_RING(CMD_STORE_DWORD_IDX);
444 OUT_RING(dev_priv->counter);
450 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
452 drm_i915_private_t *dev_priv = dev->dev_private;
453 uint32_t flush_cmd = CMD_MI_FLUSH;
458 i915_kernel_lost_context(dev);
471 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
472 drm_i915_cmdbuffer_t * cmd)
474 drm_i915_private_t *dev_priv = dev->dev_private;
475 int nbox = cmd->num_cliprects;
476 int i = 0, count, ret;
479 DRM_ERROR("alignment");
480 return DRM_ERR(EINVAL);
483 i915_kernel_lost_context(dev);
485 count = nbox ? nbox : 1;
487 for (i = 0; i < count; i++) {
489 ret = i915_emit_box(dev, cmd->cliprects, i,
495 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
500 i915_emit_breadcrumb( dev );
501 #ifdef I915_HAVE_FENCE
502 drm_fence_flush_old(dev, 0, dev_priv->counter);
507 static int i915_dispatch_batchbuffer(drm_device_t * dev,
508 drm_i915_batchbuffer_t * batch)
510 drm_i915_private_t *dev_priv = dev->dev_private;
511 drm_clip_rect_t __user *boxes = batch->cliprects;
512 int nbox = batch->num_cliprects;
516 if ((batch->start | batch->used) & 0x7) {
517 DRM_ERROR("alignment");
518 return DRM_ERR(EINVAL);
521 i915_kernel_lost_context(dev);
523 count = nbox ? nbox : 1;
525 for (i = 0; i < count; i++) {
527 int ret = i915_emit_box(dev, boxes, i,
528 batch->DR1, batch->DR4);
533 if (dev_priv->use_mi_batchbuffer_start) {
535 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
536 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
540 OUT_RING(MI_BATCH_BUFFER);
541 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
542 OUT_RING(batch->start + batch->used - 4);
548 i915_emit_breadcrumb( dev );
549 #ifdef I915_HAVE_FENCE
550 drm_fence_flush_old(dev, 0, dev_priv->counter);
555 static void i915_do_dispatch_flip(drm_device_t * dev, int pipe, int sync)
557 drm_i915_private_t *dev_priv = dev->dev_private;
558 u32 num_pages, current_page, next_page, dspbase;
559 int shift = 2 * pipe, x, y;
562 /* Calculate display base offset */
563 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
564 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
565 next_page = (current_page + 1) % num_pages;
570 dspbase = dev_priv->sarea_priv->front_offset;
573 dspbase = dev_priv->sarea_priv->back_offset;
576 dspbase = dev_priv->sarea_priv->third_offset;
581 x = dev_priv->sarea_priv->pipeA_x;
582 y = dev_priv->sarea_priv->pipeA_y;
584 x = dev_priv->sarea_priv->pipeB_x;
585 y = dev_priv->sarea_priv->pipeB_y;
588 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
590 DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page,
595 (MI_WAIT_FOR_EVENT | (pipe ? MI_WAIT_FOR_PLANE_B_FLIP :
596 MI_WAIT_FOR_PLANE_A_FLIP)));
597 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
598 (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
599 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
603 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
604 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
607 void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync)
609 drm_i915_private_t *dev_priv = dev->dev_private;
612 DRM_DEBUG("%s: pipes=0x%x pfCurrentPage=%d\n",
614 pipes, dev_priv->sarea_priv->pf_current_page);
616 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
618 for (i = 0; i < 2; i++)
619 if (pipes & (1 << i))
620 i915_do_dispatch_flip(dev, i, sync);
622 i915_emit_breadcrumb(dev);
623 #ifdef I915_HAVE_FENCE
625 drm_fence_flush_old(dev, 0, dev_priv->counter);
629 static int i915_quiescent(drm_device_t * dev)
631 drm_i915_private_t *dev_priv = dev->dev_private;
633 i915_kernel_lost_context(dev);
634 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
637 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
641 LOCK_TEST_WITH_RETURN(dev, filp);
643 return i915_quiescent(dev);
646 static int i915_batchbuffer(DRM_IOCTL_ARGS)
649 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
650 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
651 dev_priv->sarea_priv;
652 drm_i915_batchbuffer_t batch;
655 if (!dev_priv->allow_batchbuffer) {
656 DRM_ERROR("Batchbuffer ioctl disabled\n");
657 return DRM_ERR(EINVAL);
660 DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
663 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
664 batch.start, batch.used, batch.num_cliprects);
666 LOCK_TEST_WITH_RETURN(dev, filp);
668 if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
669 batch.num_cliprects *
670 sizeof(drm_clip_rect_t)))
671 return DRM_ERR(EFAULT);
673 ret = i915_dispatch_batchbuffer(dev, &batch);
675 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
679 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
682 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
683 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
684 dev_priv->sarea_priv;
685 drm_i915_cmdbuffer_t cmdbuf;
688 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
691 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
692 cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
694 LOCK_TEST_WITH_RETURN(dev, filp);
696 if (cmdbuf.num_cliprects &&
697 DRM_VERIFYAREA_READ(cmdbuf.cliprects,
698 cmdbuf.num_cliprects *
699 sizeof(drm_clip_rect_t))) {
700 DRM_ERROR("Fault accessing cliprects\n");
701 return DRM_ERR(EFAULT);
704 ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
706 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
710 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
714 static int i915_do_cleanup_pageflip(drm_device_t * dev)
716 drm_i915_private_t *dev_priv = dev->dev_private;
717 int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
719 DRM_DEBUG("%s\n", __FUNCTION__);
721 for (i = 0, pipes = 0; i < 2; i++)
722 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
723 dev_priv->sarea_priv->pf_current_page =
724 (dev_priv->sarea_priv->pf_current_page &
725 ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
731 i915_dispatch_flip(dev, pipes, 0);
736 static int i915_flip_bufs(DRM_IOCTL_ARGS)
739 drm_i915_flip_t param;
741 DRM_DEBUG("%s\n", __FUNCTION__);
743 LOCK_TEST_WITH_RETURN(dev, filp);
745 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data,
748 if (param.pipes & ~0x3) {
749 DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n",
751 return DRM_ERR(EINVAL);
754 i915_dispatch_flip(dev, param.pipes, 0);
760 static int i915_getparam(DRM_IOCTL_ARGS)
763 drm_i915_private_t *dev_priv = dev->dev_private;
764 drm_i915_getparam_t param;
768 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
769 return DRM_ERR(EINVAL);
772 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
775 switch (param.param) {
776 case I915_PARAM_IRQ_ACTIVE:
777 value = dev->irq ? 1 : 0;
779 case I915_PARAM_ALLOW_BATCHBUFFER:
780 value = dev_priv->allow_batchbuffer ? 1 : 0;
782 case I915_PARAM_LAST_DISPATCH:
783 value = READ_BREADCRUMB(dev_priv);
786 DRM_ERROR("Unknown parameter %d\n", param.param);
787 return DRM_ERR(EINVAL);
790 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
791 DRM_ERROR("DRM_COPY_TO_USER failed\n");
792 return DRM_ERR(EFAULT);
798 static int i915_setparam(DRM_IOCTL_ARGS)
801 drm_i915_private_t *dev_priv = dev->dev_private;
802 drm_i915_setparam_t param;
805 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
806 return DRM_ERR(EINVAL);
809 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
812 switch (param.param) {
813 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
814 dev_priv->use_mi_batchbuffer_start = param.value;
816 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
817 dev_priv->tex_lru_log_granularity = param.value;
819 case I915_SETPARAM_ALLOW_BATCHBUFFER:
820 dev_priv->allow_batchbuffer = param.value;
823 DRM_ERROR("unknown parameter %d\n", param.param);
824 return DRM_ERR(EINVAL);
830 drm_i915_mmio_entry_t mmio_table[] = {
831 [MMIO_REGS_PS_DEPTH_COUNT] = {
832 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
838 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
840 static int i915_mmio(DRM_IOCTL_ARGS)
844 drm_i915_private_t *dev_priv = dev->dev_private;
845 drm_i915_mmio_entry_t *e;
846 drm_i915_mmio_t mmio;
849 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
850 return DRM_ERR(EINVAL);
852 DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
855 if (mmio.reg >= mmio_table_size)
856 return DRM_ERR(EINVAL);
858 e = &mmio_table[mmio.reg];
859 base = dev_priv->mmio_map->handle + e->offset;
861 switch (mmio.read_write) {
863 if (!(e->flag & I915_MMIO_MAY_READ))
864 return DRM_ERR(EINVAL);
865 memcpy_fromio(buf, base, e->size);
866 if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
867 DRM_ERROR("DRM_COPY_TO_USER failed\n");
868 return DRM_ERR(EFAULT);
872 case I915_MMIO_WRITE:
873 if (!(e->flag & I915_MMIO_MAY_WRITE))
874 return DRM_ERR(EINVAL);
875 if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
876 DRM_ERROR("DRM_COPY_TO_USER failed\n");
877 return DRM_ERR(EFAULT);
879 memcpy_toio(base, buf, e->size);
885 int i915_driver_load(drm_device_t *dev, unsigned long flags)
887 /* i915 has 4 more counters */
889 dev->types[6] = _DRM_STAT_IRQ;
890 dev->types[7] = _DRM_STAT_PRIMARY;
891 dev->types[8] = _DRM_STAT_SECONDARY;
892 dev->types[9] = _DRM_STAT_DMA;
897 void i915_driver_lastclose(drm_device_t * dev)
899 if (dev->dev_private) {
900 drm_i915_private_t *dev_priv = dev->dev_private;
901 i915_do_cleanup_pageflip(dev);
902 i915_mem_takedown(&(dev_priv->agp_heap));
904 i915_dma_cleanup(dev);
907 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
909 if (dev->dev_private) {
910 drm_i915_private_t *dev_priv = dev->dev_private;
911 i915_mem_release(dev, filp, dev_priv->agp_heap);
915 drm_ioctl_desc_t i915_ioctls[] = {
916 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
917 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
918 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
919 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
920 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
921 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
922 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
923 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
924 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
925 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
926 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
927 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
928 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
929 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
930 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
931 [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
932 [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
935 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
938 * Determine if the device really is AGP or not.
940 * All Intel graphics chipsets are treated as AGP, even if they are really
943 * \param dev The device to be tested.
946 * A value of 1 is always retured to indictate every i9x5 is AGP.
948 int i915_driver_device_is_agp(drm_device_t * dev)
953 int i915_driver_firstopen(struct drm_device *dev)
955 #ifdef I915_HAVE_BUFFER
956 drm_bo_driver_init(dev);