shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2)
  38
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 10000; i++) {
  53                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  54                 ring->space = ring->head - (ring->tail + 8);
  55                 if (ring->space < 0)
  56                         ring->space += ring->Size;
  57                 if (ring->space >= n)
  58                         return 0;
  59
  60                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61
  62                 if (ring->head != last_head)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66         }
  67
  68         return DRM_ERR(EBUSY);
  69 }
  70
  71 void i915_kernel_lost_context(drm_device_t * dev)
  72 {
  73         drm_i915_private_t *dev_priv = dev->dev_private;
  74         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  75
  76         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  77         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  78         ring->space = ring->head - (ring->tail + 8);
  79         if (ring->space < 0)
  80                 ring->space += ring->Size;
  81
  82         if (ring->head == ring->tail)
  83                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  84 }
  85
  86 static int i915_dma_cleanup(drm_device_t * dev)
  87 {
  88         /* Make sure interrupts are disabled here because the uninstall ioctl
  89          * may not have been called from userspace and after dev_private
  90          * is freed, it's too late.
  91          */
  92         if (dev->irq)
  93                 drm_irq_uninstall(dev);
  94
  95         if (dev->dev_private) {
  96                 drm_i915_private_t *dev_priv =
  97                     (drm_i915_private_t *) dev->dev_private;
  98
  99                 if (dev_priv->ring.virtual_start) {
 100                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 101                 }
 102
 103                 if (dev_priv->status_page_dmah) {
 104                         drm_pci_free(dev, dev_priv->status_page_dmah);
 105                         /* Need to rewrite hardware status page */
 106                         I915_WRITE(0x02080, 0x1ffff000);
 107                 }
 108
 109                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 110                          DRM_MEM_DRIVER);
 111
 112                 dev->dev_private = NULL;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int i915_initialize(drm_device_t * dev,
 119                            drm_i915_private_t * dev_priv,
 120                            drm_i915_init_t * init)
 121 {
 122         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 123
 124         DRM_GETSAREA();
 125         if (!dev_priv->sarea) {
 126                 DRM_ERROR("can not find sarea!\n");
 127                 dev->dev_private = (void *)dev_priv;
 128                 i915_dma_cleanup(dev);
 129                 return DRM_ERR(EINVAL);
 130         }
 131
 132         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 133         if (!dev_priv->mmio_map) {
 134                 dev->dev_private = (void *)dev_priv;
 135                 i915_dma_cleanup(dev);
 136                 DRM_ERROR("can not find mmio map!\n");
 137                 return DRM_ERR(EINVAL);
 138         }
 139
 140         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 141             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 142
 143         dev_priv->ring.Start = init->ring_start;
 144         dev_priv->ring.End = init->ring_end;
 145         dev_priv->ring.Size = init->ring_size;
 146         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 147
 148         dev_priv->ring.map.offset = init->ring_start;
 149         dev_priv->ring.map.size = init->ring_size;
 150         dev_priv->ring.map.type = 0;
 151         dev_priv->ring.map.flags = 0;
 152         dev_priv->ring.map.mtrr = 0;
 153
 154         drm_core_ioremap(&dev_priv->ring.map, dev);
 155
 156         if (dev_priv->ring.map.handle == NULL) {
 157                 dev->dev_private = (void *)dev_priv;
 158                 i915_dma_cleanup(dev);
 159                 DRM_ERROR("can not ioremap virtual address for"
 160                           " ring buffer\n");
 161                 return DRM_ERR(ENOMEM);
 162         }
 163
 164         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 165
 166         dev_priv->cpp = init->cpp;
 167         dev_priv->back_offset = init->back_offset;
 168         dev_priv->front_offset = init->front_offset;
 169         dev_priv->current_page = 0;
 170         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 171
 172         /* We are using separate values as placeholders for mechanisms for
 173          * private backbuffer/depthbuffer usage.
 174          */
 175         dev_priv->use_mi_batchbuffer_start = 0;
 176
 177         /* Allow hardware batchbuffers unless told otherwise.
 178          */
 179         dev_priv->allow_batchbuffer = 1;
 180
 181         /* Program Hardware Status Page */
 182         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 183             0xffffffff);
 184
 185         if (!dev_priv->status_page_dmah) {
 186                 dev->dev_private = (void *)dev_priv;
 187                 i915_dma_cleanup(dev);
 188                 DRM_ERROR("Can not allocate hardware status page\n");
 189                 return DRM_ERR(ENOMEM);
 190         }
 191         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 192         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 193
 194         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 195         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 196
 197         I915_WRITE(0x02080, dev_priv->dma_status_page);
 198         DRM_DEBUG("Enabled hardware status page\n");
 199         dev->dev_private = (void *)dev_priv;
 200 #ifdef I915_HAVE_BUFFER
 201         drm_bo_driver_init(dev);
 202 #endif
 203         return 0;
 204 }
 205
 206 static int i915_dma_resume(drm_device_t * dev)
 207 {
 208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 209
 210         DRM_DEBUG("%s\n", __FUNCTION__);
 211
 212         if (!dev_priv->sarea) {
 213                 DRM_ERROR("can not find sarea!\n");
 214                 return DRM_ERR(EINVAL);
 215         }
 216
 217         if (!dev_priv->mmio_map) {
 218                 DRM_ERROR("can not find mmio map!\n");
 219                 return DRM_ERR(EINVAL);
 220         }
 221
 222         if (dev_priv->ring.map.handle == NULL) {
 223                 DRM_ERROR("can not ioremap virtual address for"
 224                           " ring buffer\n");
 225                 return DRM_ERR(ENOMEM);
 226         }
 227
 228         /* Program Hardware Status Page */
 229         if (!dev_priv->hw_status_page) {
 230                 DRM_ERROR("Can not find hardware status page\n");
 231                 return DRM_ERR(EINVAL);
 232         }
 233         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 234
 235         I915_WRITE(0x02080, dev_priv->dma_status_page);
 236         DRM_DEBUG("Enabled hardware status page\n");
 237
 238         return 0;
 239 }
 240
 241 static int i915_dma_init(DRM_IOCTL_ARGS)
 242 {
 243         DRM_DEVICE;
 244         drm_i915_private_t *dev_priv;
 245         drm_i915_init_t init;
 246         int retcode = 0;
 247
 248         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 249                                  sizeof(init));
 250
 251         switch (init.func) {
 252         case I915_INIT_DMA:
 253                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 254                                      DRM_MEM_DRIVER);
 255                 if (dev_priv == NULL)
 256                         return DRM_ERR(ENOMEM);
 257                 retcode = i915_initialize(dev, dev_priv, &init);
 258                 break;
 259         case I915_CLEANUP_DMA:
 260                 retcode = i915_dma_cleanup(dev);
 261                 break;
 262         case I915_RESUME_DMA:
 263                 retcode = i915_dma_resume(dev);
 264                 break;
 265         default:
 266                 retcode = -EINVAL;
 267                 break;
 268         }
 269
 270         return retcode;
 271 }
 272
 273 /* Implement basically the same security restrictions as hardware does
 274  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 275  *
 276  * Most of the calculations below involve calculating the size of a
 277  * particular instruction.  It's important to get the size right as
 278  * that tells us where the next instruction to check is.  Any illegal
 279  * instruction detected will be given a size of zero, which is a
 280  * signal to abort the rest of the buffer.
 281  */
 282 static int do_validate_cmd(int cmd)
 283 {
 284         switch (((cmd >> 29) & 0x7)) {
 285         case 0x0:
 286                 switch ((cmd >> 23) & 0x3f) {
 287                 case 0x0:
 288                         return 1;       /* MI_NOOP */
 289                 case 0x4:
 290                         return 1;       /* MI_FLUSH */
 291                 default:
 292                         return 0;       /* disallow everything else */
 293                 }
 294                 break;
 295         case 0x1:
 296                 return 0;       /* reserved */
 297         case 0x2:
 298                 return (cmd & 0xff) + 2;        /* 2d commands */
 299         case 0x3:
 300                 if (((cmd >> 24) & 0x1f) <= 0x18)
 301                         return 1;
 302
 303                 switch ((cmd >> 24) & 0x1f) {
 304                 case 0x1c:
 305                         return 1;
 306                 case 0x1d:
 307                         switch ((cmd >> 16) & 0xff) {
 308                         case 0x3:
 309                                 return (cmd & 0x1f) + 2;
 310                         case 0x4:
 311                                 return (cmd & 0xf) + 2;
 312                         default:
 313                                 return (cmd & 0xffff) + 2;
 314                         }
 315                 case 0x1e:
 316                         if (cmd & (1 << 23))
 317                                 return (cmd & 0xffff) + 1;
 318                         else
 319                                 return 1;
 320                 case 0x1f:
 321                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 322                                 return (cmd & 0x1ffff) + 2;
 323                         else if (cmd & (1 << 17))       /* indirect random */
 324                                 if ((cmd & 0xffff) == 0)
 325                                         return 0;       /* unknown length, too hard */
 326                                 else
 327                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 328                         else
 329                                 return 2;       /* indirect sequential */
 330                 default:
 331                         return 0;
 332                 }
 333         default:
 334                 return 0;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int validate_cmd(int cmd)
 341 {
 342         int ret = do_validate_cmd(cmd);
 343
 344 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 345
 346         return ret;
 347 }
 348
 349 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i;
 353         RING_LOCALS;
 354
 355         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 356                 return DRM_ERR(EINVAL);
 357
 358         BEGIN_LP_RING((dwords+1)&~1);
 359
 360         for (i = 0; i < dwords;) {
 361                 int cmd, sz;
 362
 363              if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) {
 364
 365                         return DRM_ERR(EINVAL);
 366               }
 367                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 368                         return DRM_ERR(EINVAL);
 369
 370                 OUT_RING(cmd);
 371
 372                 while (++i, --sz) {
 373                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 374                                                          sizeof(cmd))) {
 375                                 return DRM_ERR(EINVAL);
 376                         }
 377                         OUT_RING(cmd);
 378                 }
 379         }
 380
 381         if (dwords & 1)
 382                 OUT_RING(0);
 383
 384         ADVANCE_LP_RING();
 385
 386         return 0;
 387 }
 388
 389 static int i915_emit_box(drm_device_t * dev,
 390                          drm_clip_rect_t __user * boxes,
 391                          int i, int DR1, int DR4)
 392 {
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         drm_clip_rect_t box;
 395         RING_LOCALS;
 396
 397         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 398                 return EFAULT;
 399         }
 400
 401         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 402                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 403                           box.x1, box.y1, box.x2, box.y2);
 404                 return DRM_ERR(EINVAL);
 405         }
 406
 407         if (IS_I965G(dev)) {
 408                 BEGIN_LP_RING(4);
 409                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 410                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 411                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 412                 OUT_RING(DR4);
 413                 ADVANCE_LP_RING();
 414         } else {
 415                 BEGIN_LP_RING(6);
 416                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 417                 OUT_RING(DR1);
 418                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 419                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 420                 OUT_RING(DR4);
 421                 OUT_RING(0);
 422                 ADVANCE_LP_RING();
 423         }
 424
 425         return 0;
 426 }
 427
 428 /* XXX: Emitting the counter should really be moved to part of the IRQ
 429  * emit.  For now, do it in both places:
 430  */
 431
 432 static void i915_emit_breadcrumb(drm_device_t *dev)
 433 {
 434         drm_i915_private_t *dev_priv = dev->dev_private;
 435         RING_LOCALS;
 436
 437         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 438
 439         BEGIN_LP_RING(4);
 440         OUT_RING(CMD_STORE_DWORD_IDX);
 441         OUT_RING(20);
 442         OUT_RING(dev_priv->counter);
 443         OUT_RING(0);
 444         ADVANCE_LP_RING();
 445 #ifdef I915_HAVE_FENCE
 446         drm_fence_flush_old(dev, dev_priv->counter);
 447 #endif
 448 }
 449
 450
 451 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 452 {
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454         uint32_t flush_cmd = CMD_MI_FLUSH;
 455         RING_LOCALS;
 456
 457         flush_cmd |= flush;
 458
 459         i915_kernel_lost_context(dev);
 460
 461         BEGIN_LP_RING(4);
 462         OUT_RING(flush_cmd);
 463         OUT_RING(0);
 464         OUT_RING(0);
 465         OUT_RING(0);
 466         ADVANCE_LP_RING();
 467
 468         return 0;
 469 }
 470
 471
 472 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 473                                    drm_i915_cmdbuffer_t * cmd)
 474 {
 475         int nbox = cmd->num_cliprects;
 476         int i = 0, count, ret;
 477
 478         if (cmd->sz & 0x3) {
 479                 DRM_ERROR("alignment");
 480                 return DRM_ERR(EINVAL);
 481         }
 482
 483         i915_kernel_lost_context(dev);
 484
 485         count = nbox ? nbox : 1;
 486
 487         for (i = 0; i < count; i++) {
 488                 if (i < nbox) {
 489                         ret = i915_emit_box(dev, cmd->cliprects, i,
 490                                             cmd->DR1, cmd->DR4);
 491                         if (ret)
 492                                 return ret;
 493                 }
 494
 495                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 496                 if (ret)
 497                         return ret;
 498         }
 499
 500         i915_emit_breadcrumb( dev );
 501         return 0;
 502 }
 503
 504 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 505                                      drm_i915_batchbuffer_t * batch)
 506 {
 507         drm_i915_private_t *dev_priv = dev->dev_private;
 508         drm_clip_rect_t __user *boxes = batch->cliprects;
 509         int nbox = batch->num_cliprects;
 510         int i = 0, count;
 511         RING_LOCALS;
 512
 513         if ((batch->start | batch->used) & 0x7) {
 514                 DRM_ERROR("alignment");
 515                 return DRM_ERR(EINVAL);
 516         }
 517
 518         i915_kernel_lost_context(dev);
 519
 520         count = nbox ? nbox : 1;
 521
 522         for (i = 0; i < count; i++) {
 523                 if (i < nbox) {
 524                         int ret = i915_emit_box(dev, boxes, i,
 525                                                 batch->DR1, batch->DR4);
 526                         if (ret)
 527                                 return ret;
 528                 }
 529
 530                 if (dev_priv->use_mi_batchbuffer_start) {
 531                         BEGIN_LP_RING(2);
 532                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 533                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 534                         ADVANCE_LP_RING();
 535                 } else {
 536                         BEGIN_LP_RING(4);
 537                         OUT_RING(MI_BATCH_BUFFER);
 538                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 539                         OUT_RING(batch->start + batch->used - 4);
 540                         OUT_RING(0);
 541                         ADVANCE_LP_RING();
 542                 }
 543         }
 544
 545         i915_emit_breadcrumb( dev );
 546         return 0;
 547 }
 548
 549 static int i915_dispatch_flip(drm_device_t * dev)
 550 {
 551         drm_i915_private_t *dev_priv = dev->dev_private;
 552         RING_LOCALS;
 553
 554         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 555                   __FUNCTION__,
 556                   dev_priv->current_page,
 557                   dev_priv->sarea_priv->pf_current_page);
 558
 559         i915_kernel_lost_context(dev);
 560
 561         BEGIN_LP_RING(2);
 562         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 563         OUT_RING(0);
 564         ADVANCE_LP_RING();
 565
 566         BEGIN_LP_RING(6);
 567         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 568         OUT_RING(0);
 569         if (dev_priv->current_page == 0) {
 570                 OUT_RING(dev_priv->back_offset);
 571                 dev_priv->current_page = 1;
 572         } else {
 573                 OUT_RING(dev_priv->front_offset);
 574                 dev_priv->current_page = 0;
 575         }
 576         OUT_RING(0);
 577         ADVANCE_LP_RING();
 578
 579         BEGIN_LP_RING(2);
 580         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 581         OUT_RING(0);
 582         ADVANCE_LP_RING();
 583
 584         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 585
 586         BEGIN_LP_RING(4);
 587         OUT_RING(CMD_STORE_DWORD_IDX);
 588         OUT_RING(20);
 589         OUT_RING(dev_priv->counter);
 590         OUT_RING(0);
 591         ADVANCE_LP_RING();
 592 #ifdef I915_HAVE_FENCE
 593         drm_fence_flush_old(dev, dev_priv->counter);
 594 #endif
 595         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 596         return 0;
 597 }
 598
 599 static int i915_quiescent(drm_device_t * dev)
 600 {
 601         drm_i915_private_t *dev_priv = dev->dev_private;
 602
 603         i915_kernel_lost_context(dev);
 604         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 605 }
 606
 607 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 608 {
 609         DRM_DEVICE;
 610
 611         LOCK_TEST_WITH_RETURN(dev, filp);
 612
 613         return i915_quiescent(dev);
 614 }
 615
 616 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 617 {
 618         DRM_DEVICE;
 619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 620         u32 *hw_status = dev_priv->hw_status_page;
 621         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 622             dev_priv->sarea_priv;
 623         drm_i915_batchbuffer_t batch;
 624         int ret;
 625
 626         if (!dev_priv->allow_batchbuffer) {
 627                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 628                 return DRM_ERR(EINVAL);
 629         }
 630
 631         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 632                                  sizeof(batch));
 633
 634         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 635                   batch.start, batch.used, batch.num_cliprects);
 636
 637         LOCK_TEST_WITH_RETURN(dev, filp);
 638
 639         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 640                                                        batch.num_cliprects *
 641                                                        sizeof(drm_clip_rect_t)))
 642                 return DRM_ERR(EFAULT);
 643
 644         ret = i915_dispatch_batchbuffer(dev, &batch);
 645
 646         sarea_priv->last_dispatch = (int)hw_status[5];
 647         return ret;
 648 }
 649
 650 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 651 {
 652         DRM_DEVICE;
 653         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 654         u32 *hw_status = dev_priv->hw_status_page;
 655         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 656             dev_priv->sarea_priv;
 657         drm_i915_cmdbuffer_t cmdbuf;
 658         int ret;
 659
 660         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 661                                  sizeof(cmdbuf));
 662
 663         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 664                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 665
 666         LOCK_TEST_WITH_RETURN(dev, filp);
 667
 668         if (cmdbuf.num_cliprects &&
 669             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 670                                 cmdbuf.num_cliprects *
 671                                 sizeof(drm_clip_rect_t))) {
 672                 DRM_ERROR("Fault accessing cliprects\n");
 673                 return DRM_ERR(EFAULT);
 674         }
 675
 676         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 677         if (ret) {
 678                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 679                 return ret;
 680         }
 681
 682         sarea_priv->last_dispatch = (int)hw_status[5];
 683         return 0;
 684 }
 685
 686 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 687 {
 688         drm_i915_private_t *dev_priv = dev->dev_private;
 689
 690         DRM_DEBUG("%s\n", __FUNCTION__);
 691         if (dev_priv->current_page != 0)
 692                 i915_dispatch_flip(dev);
 693
 694         return 0;
 695 }
 696
 697 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 698 {
 699         DRM_DEVICE;
 700
 701         DRM_DEBUG("%s\n", __FUNCTION__);
 702
 703         LOCK_TEST_WITH_RETURN(dev, filp);
 704
 705         return i915_dispatch_flip(dev);
 706 }
 707
 708
 709 static int i915_getparam(DRM_IOCTL_ARGS)
 710 {
 711         DRM_DEVICE;
 712         drm_i915_private_t *dev_priv = dev->dev_private;
 713         drm_i915_getparam_t param;
 714         int value;
 715
 716         if (!dev_priv) {
 717                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 718                 return DRM_ERR(EINVAL);
 719         }
 720
 721         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 722                                  sizeof(param));
 723
 724         switch (param.param) {
 725         case I915_PARAM_IRQ_ACTIVE:
 726                 value = dev->irq ? 1 : 0;
 727                 break;
 728         case I915_PARAM_ALLOW_BATCHBUFFER:
 729                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 730                 break;
 731         case I915_PARAM_LAST_DISPATCH:
 732                 value = READ_BREADCRUMB(dev_priv);
 733                 break;
 734         default:
 735                 DRM_ERROR("Unknown parameter %d\n", param.param);
 736                 return DRM_ERR(EINVAL);
 737         }
 738
 739         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 740                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 741                 return DRM_ERR(EFAULT);
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int i915_setparam(DRM_IOCTL_ARGS)
 748 {
 749         DRM_DEVICE;
 750         drm_i915_private_t *dev_priv = dev->dev_private;
 751         drm_i915_setparam_t param;
 752
 753         if (!dev_priv) {
 754                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 755                 return DRM_ERR(EINVAL);
 756         }
 757
 758         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 759                                  sizeof(param));
 760
 761         switch (param.param) {
 762         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 763                 dev_priv->use_mi_batchbuffer_start = param.value;
 764                 break;
 765         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 766                 dev_priv->tex_lru_log_granularity = param.value;
 767                 break;
 768         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 769                 dev_priv->allow_batchbuffer = param.value;
 770                 break;
 771         default:
 772                 DRM_ERROR("unknown parameter %d\n", param.param);
 773                 return DRM_ERR(EINVAL);
 774         }
 775
 776         return 0;
 777 }
 778
 779 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 780 {
 781         /* i915 has 4 more counters */
 782         dev->counters += 4;
 783         dev->types[6] = _DRM_STAT_IRQ;
 784         dev->types[7] = _DRM_STAT_PRIMARY;
 785         dev->types[8] = _DRM_STAT_SECONDARY;
 786         dev->types[9] = _DRM_STAT_DMA;
 787
 788         return 0;
 789 }
 790
 791 void i915_driver_lastclose(drm_device_t * dev)
 792 {
 793         if (dev->dev_private) {
 794                 drm_i915_private_t *dev_priv = dev->dev_private;
 795                 i915_mem_takedown(&(dev_priv->agp_heap));
 796         }
 797         i915_dma_cleanup(dev);
 798 }
 799
 800 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 801 {
 802         if (dev->dev_private) {
 803                 drm_i915_private_t *dev_priv = dev->dev_private;
 804                 if (dev_priv->page_flipping) {
 805                         i915_do_cleanup_pageflip(dev);
 806                 }
 807                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 808         }
 809 }
 810
 811 drm_ioctl_desc_t i915_ioctls[] = {
 812         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 813         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 814         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 815         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 816         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 817         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 818         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 819         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 820         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 821         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 822         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 823         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 824         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 825         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 826         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 827         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 828 };
 829
 830 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 831
 832 /**
 833  * Determine if the device really is AGP or not.
 834  *
 835  * All Intel graphics chipsets are treated as AGP, even if they are really
 836  * PCI-e.
 837  *
 838  * \param dev   The device to be tested.
 839  *
 840  * \returns
 841  * A value of 1 is always retured to indictate every i9x5 is AGP.
 842  */
 843 int i915_driver_device_is_agp(drm_device_t * dev)
 844 {
 845         return 1;
 846 }