1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
46 for (i = 0; i < 10000; i++) {
47 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
48 ring->space = ring->head - (ring->tail + 8);
50 ring->space += ring->Size;
54 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
56 if (ring->head != last_head)
59 last_head = ring->head;
66 void i915_kernel_lost_context(struct drm_device * dev)
68 drm_i915_private_t *dev_priv = dev->dev_private;
69 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
71 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
72 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
73 ring->space = ring->head - (ring->tail + 8);
75 ring->space += ring->Size;
77 if (ring->head == ring->tail)
78 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
81 static int i915_dma_cleanup(struct drm_device * dev)
83 drm_i915_private_t *dev_priv = dev->dev_private;
84 /* Make sure interrupts are disabled here because the uninstall ioctl
85 * may not have been called from userspace and after dev_private
86 * is freed, it's too late.
89 drm_irq_uninstall(dev);
91 if (dev_priv->ring.virtual_start) {
92 drm_core_ioremapfree(&dev_priv->ring.map, dev);
93 dev_priv->ring.virtual_start = 0;
94 dev_priv->ring.map.handle = 0;
95 dev_priv->ring.map.size = 0;
98 if (dev_priv->status_page_dmah) {
99 drm_pci_free(dev, dev_priv->status_page_dmah);
100 dev_priv->status_page_dmah = NULL;
101 /* Need to rewrite hardware status page */
102 I915_WRITE(0x02080, 0x1ffff000);
105 if (dev_priv->status_gfx_addr) {
106 dev_priv->status_gfx_addr = 0;
107 drm_core_ioremapfree(&dev_priv->hws_map, dev);
108 I915_WRITE(0x02080, 0x1ffff000);
114 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
116 drm_i915_private_t *dev_priv = dev->dev_private;
118 dev_priv->sarea = drm_getsarea(dev);
119 if (!dev_priv->sarea) {
120 DRM_ERROR("can not find sarea!\n");
121 i915_dma_cleanup(dev);
125 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
126 if (!dev_priv->mmio_map) {
127 i915_dma_cleanup(dev);
128 DRM_ERROR("can not find mmio map!\n");
132 #ifdef I915_HAVE_BUFFER
133 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
136 dev_priv->sarea_priv = (drm_i915_sarea_t *)
137 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
139 dev_priv->ring.Start = init->ring_start;
140 dev_priv->ring.End = init->ring_end;
141 dev_priv->ring.Size = init->ring_size;
142 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
144 dev_priv->ring.map.offset = init->ring_start;
145 dev_priv->ring.map.size = init->ring_size;
146 dev_priv->ring.map.type = 0;
147 dev_priv->ring.map.flags = 0;
148 dev_priv->ring.map.mtrr = 0;
150 drm_core_ioremap(&dev_priv->ring.map, dev);
152 if (dev_priv->ring.map.handle == NULL) {
153 i915_dma_cleanup(dev);
154 DRM_ERROR("can not ioremap virtual address for"
159 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
161 dev_priv->cpp = init->cpp;
162 dev_priv->sarea_priv->pf_current_page = 0;
164 /* We are using separate values as placeholders for mechanisms for
165 * private backbuffer/depthbuffer usage.
167 dev_priv->use_mi_batchbuffer_start = 0;
169 /* Allow hardware batchbuffers unless told otherwise.
171 dev_priv->allow_batchbuffer = 1;
173 /* Enable vblank on pipe A for older X servers
175 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
177 /* Program Hardware Status Page */
179 dev_priv->status_page_dmah =
180 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
182 if (!dev_priv->status_page_dmah) {
183 i915_dma_cleanup(dev);
184 DRM_ERROR("Can not allocate hardware status page\n");
187 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
188 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
190 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
192 I915_WRITE(0x02080, dev_priv->dma_status_page);
194 DRM_DEBUG("Enabled hardware status page\n");
195 #ifdef I915_HAVE_BUFFER
196 mutex_init(&dev_priv->cmdbuf_mutex);
201 static int i915_dma_resume(struct drm_device * dev)
203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205 DRM_DEBUG("%s\n", __FUNCTION__);
207 if (!dev_priv->sarea) {
208 DRM_ERROR("can not find sarea!\n");
212 if (!dev_priv->mmio_map) {
213 DRM_ERROR("can not find mmio map!\n");
217 if (dev_priv->ring.map.handle == NULL) {
218 DRM_ERROR("can not ioremap virtual address for"
223 /* Program Hardware Status Page */
224 if (!dev_priv->hw_status_page) {
225 DRM_ERROR("Can not find hardware status page\n");
228 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
230 if (dev_priv->status_gfx_addr != 0)
231 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
233 I915_WRITE(0x02080, dev_priv->dma_status_page);
234 DRM_DEBUG("Enabled hardware status page\n");
239 static int i915_dma_init(struct drm_device *dev, void *data,
240 struct drm_file *file_priv)
242 drm_i915_init_t *init = data;
245 switch (init->func) {
247 retcode = i915_initialize(dev, init);
249 case I915_CLEANUP_DMA:
250 retcode = i915_dma_cleanup(dev);
252 case I915_RESUME_DMA:
253 retcode = i915_dma_resume(dev);
263 /* Implement basically the same security restrictions as hardware does
264 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
266 * Most of the calculations below involve calculating the size of a
267 * particular instruction. It's important to get the size right as
268 * that tells us where the next instruction to check is. Any illegal
269 * instruction detected will be given a size of zero, which is a
270 * signal to abort the rest of the buffer.
272 static int do_validate_cmd(int cmd)
274 switch (((cmd >> 29) & 0x7)) {
276 switch ((cmd >> 23) & 0x3f) {
278 return 1; /* MI_NOOP */
280 return 1; /* MI_FLUSH */
282 return 0; /* disallow everything else */
286 return 0; /* reserved */
288 return (cmd & 0xff) + 2; /* 2d commands */
290 if (((cmd >> 24) & 0x1f) <= 0x18)
293 switch ((cmd >> 24) & 0x1f) {
297 switch ((cmd >> 16) & 0xff) {
299 return (cmd & 0x1f) + 2;
301 return (cmd & 0xf) + 2;
303 return (cmd & 0xffff) + 2;
307 return (cmd & 0xffff) + 1;
311 if ((cmd & (1 << 23)) == 0) /* inline vertices */
312 return (cmd & 0x1ffff) + 2;
313 else if (cmd & (1 << 17)) /* indirect random */
314 if ((cmd & 0xffff) == 0)
315 return 0; /* unknown length, too hard */
317 return (((cmd & 0xffff) + 1) / 2) + 1;
319 return 2; /* indirect sequential */
330 static int validate_cmd(int cmd)
332 int ret = do_validate_cmd(cmd);
334 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
339 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
342 drm_i915_private_t *dev_priv = dev->dev_private;
346 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
349 BEGIN_LP_RING((dwords+1)&~1);
351 for (i = 0; i < dwords;) {
354 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
357 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
363 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
379 static int i915_emit_box(struct drm_device * dev,
380 struct drm_clip_rect __user * boxes,
381 int i, int DR1, int DR4)
383 drm_i915_private_t *dev_priv = dev->dev_private;
384 struct drm_clip_rect box;
387 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
391 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
392 DRM_ERROR("Bad box %d,%d..%d,%d\n",
393 box.x1, box.y1, box.x2, box.y2);
399 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
400 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
401 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
406 OUT_RING(GFX_OP_DRAWRECT_INFO);
408 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
409 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
418 /* XXX: Emitting the counter should really be moved to part of the IRQ
419 * emit. For now, do it in both places:
422 void i915_emit_breadcrumb(struct drm_device *dev)
424 drm_i915_private_t *dev_priv = dev->dev_private;
427 if (++dev_priv->counter > BREADCRUMB_MASK) {
428 dev_priv->counter = 1;
429 DRM_DEBUG("Breadcrumb counter wrapped around\n");
432 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
435 OUT_RING(CMD_STORE_DWORD_IDX);
437 OUT_RING(dev_priv->counter);
443 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
445 drm_i915_private_t *dev_priv = dev->dev_private;
446 uint32_t flush_cmd = CMD_MI_FLUSH;
451 i915_kernel_lost_context(dev);
464 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
465 drm_i915_cmdbuffer_t * cmd)
467 #ifdef I915_HAVE_FENCE
468 drm_i915_private_t *dev_priv = dev->dev_private;
470 int nbox = cmd->num_cliprects;
471 int i = 0, count, ret;
474 DRM_ERROR("alignment\n");
478 i915_kernel_lost_context(dev);
480 count = nbox ? nbox : 1;
482 for (i = 0; i < count; i++) {
484 ret = i915_emit_box(dev, cmd->cliprects, i,
490 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
495 i915_emit_breadcrumb( dev );
496 #ifdef I915_HAVE_FENCE
497 drm_fence_flush_old(dev, 0, dev_priv->counter);
502 static int i915_dispatch_batchbuffer(struct drm_device * dev,
503 drm_i915_batchbuffer_t * batch)
505 drm_i915_private_t *dev_priv = dev->dev_private;
506 struct drm_clip_rect __user *boxes = batch->cliprects;
507 int nbox = batch->num_cliprects;
511 if ((batch->start | batch->used) & 0x7) {
512 DRM_ERROR("alignment\n");
516 i915_kernel_lost_context(dev);
518 count = nbox ? nbox : 1;
520 for (i = 0; i < count; i++) {
522 int ret = i915_emit_box(dev, boxes, i,
523 batch->DR1, batch->DR4);
528 if (dev_priv->use_mi_batchbuffer_start) {
531 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
532 OUT_RING(batch->start);
534 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
535 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
541 OUT_RING(MI_BATCH_BUFFER);
542 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
543 OUT_RING(batch->start + batch->used - 4);
549 i915_emit_breadcrumb( dev );
550 #ifdef I915_HAVE_FENCE
551 drm_fence_flush_old(dev, 0, dev_priv->counter);
556 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
558 drm_i915_private_t *dev_priv = dev->dev_private;
559 u32 num_pages, current_page, next_page, dspbase;
560 int shift = 2 * plane, x, y;
563 /* Calculate display base offset */
564 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
565 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
566 next_page = (current_page + 1) % num_pages;
571 dspbase = dev_priv->sarea_priv->front_offset;
574 dspbase = dev_priv->sarea_priv->back_offset;
577 dspbase = dev_priv->sarea_priv->third_offset;
582 x = dev_priv->sarea_priv->planeA_x;
583 y = dev_priv->sarea_priv->planeA_y;
585 x = dev_priv->sarea_priv->planeB_x;
586 y = dev_priv->sarea_priv->planeB_y;
589 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
591 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
596 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
597 MI_WAIT_FOR_PLANE_A_FLIP)));
598 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
599 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
600 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
604 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
605 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
608 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
610 drm_i915_private_t *dev_priv = dev->dev_private;
613 DRM_DEBUG("%s: planes=0x%x pfCurrentPage=%d\n",
615 planes, dev_priv->sarea_priv->pf_current_page);
617 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
619 for (i = 0; i < 2; i++)
620 if (planes & (1 << i))
621 i915_do_dispatch_flip(dev, i, sync);
623 i915_emit_breadcrumb(dev);
624 #ifdef I915_HAVE_FENCE
626 drm_fence_flush_old(dev, 0, dev_priv->counter);
630 static int i915_quiescent(struct drm_device * dev)
632 drm_i915_private_t *dev_priv = dev->dev_private;
634 i915_kernel_lost_context(dev);
635 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
638 static int i915_flush_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *file_priv)
642 LOCK_TEST_WITH_RETURN(dev, file_priv);
644 return i915_quiescent(dev);
647 static int i915_batchbuffer(struct drm_device *dev, void *data,
648 struct drm_file *file_priv)
650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
651 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
652 dev_priv->sarea_priv;
653 drm_i915_batchbuffer_t *batch = data;
656 if (!dev_priv->allow_batchbuffer) {
657 DRM_ERROR("Batchbuffer ioctl disabled\n");
661 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
662 batch->start, batch->used, batch->num_cliprects);
664 LOCK_TEST_WITH_RETURN(dev, file_priv);
666 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
667 batch->num_cliprects *
668 sizeof(struct drm_clip_rect)))
671 ret = i915_dispatch_batchbuffer(dev, batch);
673 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
677 static int i915_cmdbuffer(struct drm_device *dev, void *data,
678 struct drm_file *file_priv)
680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
681 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
682 dev_priv->sarea_priv;
683 drm_i915_cmdbuffer_t *cmdbuf = data;
686 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
687 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
689 LOCK_TEST_WITH_RETURN(dev, file_priv);
691 if (cmdbuf->num_cliprects &&
692 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
693 cmdbuf->num_cliprects *
694 sizeof(struct drm_clip_rect))) {
695 DRM_ERROR("Fault accessing cliprects\n");
699 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
701 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
705 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
709 #ifdef I915_HAVE_BUFFER
710 struct i915_relocatee_info {
711 struct drm_buffer_object *buf;
712 unsigned long offset;
714 unsigned page_offset;
715 struct drm_bo_kmap_obj kmap;
719 static void i915_dereference_buffers_locked(struct drm_buffer_object **buffers,
720 unsigned num_buffers)
722 while (num_buffers--)
723 drm_bo_usage_deref_locked(&buffers[num_buffers]);
726 int i915_apply_reloc(struct drm_file *file_priv, int num_buffers,
727 struct drm_buffer_object **buffers,
728 struct i915_relocatee_info *relocatee,
732 unsigned long new_cmd_offset;
736 if (reloc[2] >= num_buffers) {
737 DRM_ERROR("Illegal relocation buffer %08X\n", reloc[2]);
741 new_cmd_offset = reloc[0];
742 if (!relocatee->data_page ||
743 !drm_bo_same_page(relocatee->offset, new_cmd_offset)) {
744 drm_bo_kunmap(&relocatee->kmap);
745 relocatee->offset = new_cmd_offset;
746 ret = drm_bo_kmap(relocatee->buf, new_cmd_offset >> PAGE_SHIFT,
747 1, &relocatee->kmap);
749 DRM_ERROR("Could not map command buffer to apply relocs\n %08lx", new_cmd_offset);
753 relocatee->data_page = drm_bmo_virtual(&relocatee->kmap,
754 &relocatee->is_iomem);
755 relocatee->page_offset = (relocatee->offset & PAGE_MASK);
758 val = buffers[reloc[2]]->offset;
759 index = (reloc[0] - relocatee->page_offset) >> 2;
761 /* add in validate */
762 val = val + reloc[1];
764 relocatee->data_page[index] = val;
768 int i915_process_relocs(struct drm_file *file_priv,
770 uint32_t *reloc_buf_handle,
771 struct i915_relocatee_info *relocatee,
772 struct drm_buffer_object **buffers,
773 uint32_t num_buffers)
775 struct drm_device *dev = file_priv->head->dev;
776 struct drm_buffer_object *reloc_list_object;
777 uint32_t cur_handle = *reloc_buf_handle;
778 uint32_t *reloc_page;
779 int ret, reloc_is_iomem, reloc_stride;
780 uint32_t num_relocs, reloc_offset, reloc_end, reloc_page_offset, next_offset, cur_offset;
781 struct drm_bo_kmap_obj reloc_kmap;
783 memset(&reloc_kmap, 0, sizeof(reloc_kmap));
785 mutex_lock(&dev->struct_mutex);
786 reloc_list_object = drm_lookup_buffer_object(file_priv, cur_handle, 1);
787 mutex_unlock(&dev->struct_mutex);
788 if (!reloc_list_object)
791 ret = drm_bo_kmap(reloc_list_object, 0, 1, &reloc_kmap);
793 DRM_ERROR("Could not map relocation buffer.\n");
797 reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
798 num_relocs = reloc_page[0] & 0xffff;
800 if ((reloc_page[0] >> 16) & 0xffff) {
801 DRM_ERROR("Unsupported relocation type requested\n");
805 /* get next relocate buffer handle */
806 *reloc_buf_handle = reloc_page[1];
807 reloc_stride = I915_RELOC0_STRIDE * sizeof(uint32_t); /* may be different for other types of relocs */
809 DRM_DEBUG("num relocs is %d, next is %08X\n", num_relocs, reloc_page[1]);
811 reloc_page_offset = 0;
812 reloc_offset = I915_RELOC_HEADER * sizeof(uint32_t);
813 reloc_end = reloc_offset + (num_relocs * reloc_stride);
816 next_offset = drm_bo_offset_end(reloc_offset, reloc_end);
819 cur_offset = ((reloc_offset + reloc_page_offset) & ~PAGE_MASK) / sizeof(uint32_t);
820 ret = i915_apply_reloc(file_priv, num_buffers,
821 buffers, relocatee, &reloc_page[cur_offset]);
825 reloc_offset += reloc_stride;
826 } while (reloc_offset < next_offset);
828 drm_bo_kunmap(&reloc_kmap);
830 reloc_offset = next_offset;
831 if (reloc_offset != reloc_end) {
832 ret = drm_bo_kmap(reloc_list_object, reloc_offset >> PAGE_SHIFT, 1, &reloc_kmap);
834 DRM_ERROR("Could not map relocation buffer.\n");
838 reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
839 reloc_page_offset = reloc_offset & ~PAGE_MASK;
842 } while (reloc_offset != reloc_end);
844 drm_bo_kunmap(&relocatee->kmap);
845 relocatee->data_page = NULL;
847 drm_bo_kunmap(&reloc_kmap);
849 mutex_lock(&dev->struct_mutex);
850 drm_bo_usage_deref_locked(&reloc_list_object);
851 mutex_unlock(&dev->struct_mutex);
856 static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle,
857 drm_handle_t buf_reloc_handle,
858 struct drm_buffer_object **buffers,
861 struct drm_device *dev = file_priv->head->dev;
862 struct i915_relocatee_info relocatee;
865 memset(&relocatee, 0, sizeof(relocatee));
867 mutex_lock(&dev->struct_mutex);
868 relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1);
869 mutex_unlock(&dev->struct_mutex);
870 if (!relocatee.buf) {
871 DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle);
876 while (buf_reloc_handle) {
877 ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count);
879 DRM_ERROR("process relocs failed\n");
884 mutex_lock(&dev->struct_mutex);
885 drm_bo_usage_deref_locked(&relocatee.buf);
886 mutex_unlock(&dev->struct_mutex);
893 * Validate, add fence and relocate a block of bos from a userspace list
895 int i915_validate_buffer_list(struct drm_file *file_priv,
896 unsigned int fence_class, uint64_t data,
897 struct drm_buffer_object **buffers,
898 uint32_t *num_buffers)
900 struct drm_i915_op_arg arg;
901 struct drm_bo_op_req *req = &arg.d.req;
902 struct drm_bo_arg_rep rep;
903 unsigned long next = 0;
905 unsigned buf_count = 0;
906 struct drm_device *dev = file_priv->head->dev;
907 uint32_t buf_reloc_handle, buf_handle;
911 if (buf_count >= *num_buffers) {
912 DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers);
917 buffers[buf_count] = NULL;
919 if (copy_from_user(&arg, (void __user *)(unsigned)data, sizeof(arg))) {
926 mutex_lock(&dev->struct_mutex);
927 buffers[buf_count] = drm_lookup_buffer_object(file_priv, req->arg_handle, 1);
928 mutex_unlock(&dev->struct_mutex);
934 if (req->op != drm_bo_validate) {
936 ("Buffer object operation wasn't \"validate\".\n");
941 buf_handle = req->bo_req.handle;
942 buf_reloc_handle = arg.reloc_handle;
944 if (buf_reloc_handle) {
945 ret = i915_exec_reloc(file_priv, buf_handle, buf_reloc_handle, buffers, buf_count);
951 rep.ret = drm_bo_handle_validate(file_priv, req->bo_req.handle,
952 req->bo_req.fence_class,
958 &buffers[buf_count]);
961 DRM_ERROR("error on handle validate %d\n", rep.ret);
970 if (copy_to_user((void __user *)(unsigned)data, &arg, sizeof(arg)))
977 *num_buffers = buf_count;
980 mutex_lock(&dev->struct_mutex);
981 i915_dereference_buffers_locked(buffers, buf_count);
982 mutex_unlock(&dev->struct_mutex);
984 return (ret) ? ret : rep.ret;
987 static int i915_execbuffer(struct drm_device *dev, void *data,
988 struct drm_file *file_priv)
990 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
991 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
992 dev_priv->sarea_priv;
993 struct drm_i915_execbuffer *exec_buf = data;
994 struct _drm_i915_batchbuffer *batch = &exec_buf->batch;
995 struct drm_fence_arg *fence_arg = &exec_buf->fence_arg;
998 struct drm_buffer_object **buffers;
999 struct drm_fence_object *fence;
1001 if (!dev_priv->allow_batchbuffer) {
1002 DRM_ERROR("Batchbuffer ioctl disabled\n");
1007 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
1008 batch->num_cliprects *
1009 sizeof(struct drm_clip_rect)))
1012 if (exec_buf->num_buffers > dev_priv->max_validate_buffers)
1016 ret = drm_bo_read_lock(&dev->bm.bm_lock);
1021 * The cmdbuf_mutex makes sure the validate-submit-fence
1022 * operation is atomic.
1025 ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
1027 drm_bo_read_unlock(&dev->bm.bm_lock);
1031 num_buffers = exec_buf->num_buffers;
1033 buffers = drm_calloc(num_buffers, sizeof(struct drm_buffer_object *), DRM_MEM_DRIVER);
1035 drm_bo_read_unlock(&dev->bm.bm_lock);
1036 mutex_unlock(&dev_priv->cmdbuf_mutex);
1040 /* validate buffer list + fixup relocations */
1041 ret = i915_validate_buffer_list(file_priv, 0, exec_buf->ops_list,
1042 buffers, &num_buffers);
1046 /* make sure all previous memory operations have passed */
1047 DRM_MEMORYBARRIER();
1048 drm_agp_chipset_flush(dev);
1051 batch->start = buffers[num_buffers-1]->offset;
1053 DRM_DEBUG("i915 exec batchbuffer, start %x used %d cliprects %d\n",
1054 batch->start, batch->used, batch->num_cliprects);
1056 ret = i915_dispatch_batchbuffer(dev, batch);
1060 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1063 ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
1067 if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
1068 ret = drm_fence_add_user_object(file_priv, fence, fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE);
1070 fence_arg->handle = fence->base.hash.key;
1071 fence_arg->fence_class = fence->fence_class;
1072 fence_arg->type = fence->type;
1073 fence_arg->signaled = fence->signaled;
1076 drm_fence_usage_deref_unlocked(&fence);
1080 mutex_lock(&dev->struct_mutex);
1081 i915_dereference_buffers_locked(buffers, num_buffers);
1082 mutex_unlock(&dev->struct_mutex);
1085 drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER);
1087 mutex_unlock(&dev_priv->cmdbuf_mutex);
1088 drm_bo_read_unlock(&dev->bm.bm_lock);
1093 static int i915_do_cleanup_pageflip(struct drm_device * dev)
1095 drm_i915_private_t *dev_priv = dev->dev_private;
1096 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
1098 DRM_DEBUG("%s\n", __FUNCTION__);
1100 for (i = 0, planes = 0; i < 2; i++)
1101 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
1102 dev_priv->sarea_priv->pf_current_page =
1103 (dev_priv->sarea_priv->pf_current_page &
1104 ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
1110 i915_dispatch_flip(dev, planes, 0);
1115 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
1117 drm_i915_flip_t *param = data;
1119 DRM_DEBUG("%s\n", __FUNCTION__);
1121 LOCK_TEST_WITH_RETURN(dev, file_priv);
1123 /* This is really planes */
1124 if (param->pipes & ~0x3) {
1125 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
1130 i915_dispatch_flip(dev, param->pipes, 0);
1136 static int i915_getparam(struct drm_device *dev, void *data,
1137 struct drm_file *file_priv)
1139 drm_i915_private_t *dev_priv = dev->dev_private;
1140 drm_i915_getparam_t *param = data;
1144 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1148 switch (param->param) {
1149 case I915_PARAM_IRQ_ACTIVE:
1150 value = dev->irq ? 1 : 0;
1152 case I915_PARAM_ALLOW_BATCHBUFFER:
1153 value = dev_priv->allow_batchbuffer ? 1 : 0;
1155 case I915_PARAM_LAST_DISPATCH:
1156 value = READ_BREADCRUMB(dev_priv);
1159 DRM_ERROR("Unknown parameter %d\n", param->param);
1163 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1164 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1171 static int i915_setparam(struct drm_device *dev, void *data,
1172 struct drm_file *file_priv)
1174 drm_i915_private_t *dev_priv = dev->dev_private;
1175 drm_i915_setparam_t *param = data;
1178 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1182 switch (param->param) {
1183 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1184 dev_priv->use_mi_batchbuffer_start = param->value;
1186 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1187 dev_priv->tex_lru_log_granularity = param->value;
1189 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1190 dev_priv->allow_batchbuffer = param->value;
1193 DRM_ERROR("unknown parameter %d\n", param->param);
1200 drm_i915_mmio_entry_t mmio_table[] = {
1201 [MMIO_REGS_PS_DEPTH_COUNT] = {
1202 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
1208 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
1210 static int i915_mmio(struct drm_device *dev, void *data,
1211 struct drm_file *file_priv)
1214 drm_i915_private_t *dev_priv = dev->dev_private;
1215 drm_i915_mmio_entry_t *e;
1216 drm_i915_mmio_t *mmio = data;
1221 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1225 if (mmio->reg >= mmio_table_size)
1228 e = &mmio_table[mmio->reg];
1229 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
1231 switch (mmio->read_write) {
1232 case I915_MMIO_READ:
1233 if (!(e->flag & I915_MMIO_MAY_READ))
1235 for (i = 0; i < e->size / 4; i++)
1236 buf[i] = I915_READ(e->offset + i * 4);
1237 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
1238 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1243 case I915_MMIO_WRITE:
1244 if (!(e->flag & I915_MMIO_MAY_WRITE))
1246 if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
1247 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1250 for (i = 0; i < e->size / 4; i++)
1251 I915_WRITE(e->offset + i * 4, buf[i]);
1257 static int i915_set_status_page(struct drm_device *dev, void *data,
1258 struct drm_file *file_priv)
1260 drm_i915_private_t *dev_priv = dev->dev_private;
1261 drm_i915_hws_addr_t *hws = data;
1264 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1267 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1269 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1271 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1272 dev_priv->hws_map.size = 4*1024;
1273 dev_priv->hws_map.type = 0;
1274 dev_priv->hws_map.flags = 0;
1275 dev_priv->hws_map.mtrr = 0;
1277 drm_core_ioremap(&dev_priv->hws_map, dev);
1278 if (dev_priv->hws_map.handle == NULL) {
1279 i915_dma_cleanup(dev);
1280 dev_priv->status_gfx_addr = 0;
1281 DRM_ERROR("can not ioremap virtual address for"
1282 " G33 hw status page\n");
1285 dev_priv->hw_status_page = dev_priv->hws_map.handle;
1287 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1288 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
1289 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1290 dev_priv->status_gfx_addr);
1291 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1295 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 unsigned long base, size;
1299 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1301 /* i915 has 4 more counters */
1303 dev->types[6] = _DRM_STAT_IRQ;
1304 dev->types[7] = _DRM_STAT_PRIMARY;
1305 dev->types[8] = _DRM_STAT_SECONDARY;
1306 dev->types[9] = _DRM_STAT_DMA;
1308 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1309 if (dev_priv == NULL)
1312 memset(dev_priv, 0, sizeof(drm_i915_private_t));
1314 dev->dev_private = (void *)dev_priv;
1316 /* Add register map (needed for suspend/resume) */
1317 base = drm_get_resource_start(dev, mmio_bar);
1318 size = drm_get_resource_len(dev, mmio_bar);
1320 ret = drm_addmap(dev, base, size, _DRM_REGISTERS, _DRM_KERNEL,
1321 &dev_priv->mmio_map);
1324 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1325 intel_init_chipset_flush_compat(dev);
1331 int i915_driver_unload(struct drm_device *dev)
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1335 if (dev_priv->mmio_map)
1336 drm_rmmap(dev, dev_priv->mmio_map);
1338 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1341 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1342 intel_fini_chipset_flush_compat(dev);
1348 void i915_driver_lastclose(struct drm_device * dev)
1350 drm_i915_private_t *dev_priv = dev->dev_private;
1352 if (drm_getsarea(dev) && dev_priv->sarea_priv)
1353 i915_do_cleanup_pageflip(dev);
1354 if (dev_priv->agp_heap)
1355 i915_mem_takedown(&(dev_priv->agp_heap));
1357 i915_dma_cleanup(dev);
1360 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1362 drm_i915_private_t *dev_priv = dev->dev_private;
1363 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1366 struct drm_ioctl_desc i915_ioctls[] = {
1367 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1368 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1369 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1370 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1371 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1372 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1373 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1374 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1375 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1376 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1377 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1378 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1379 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1380 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1381 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1382 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1383 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1384 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1385 #ifdef I915_HAVE_BUFFER
1386 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1390 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1393 * Determine if the device really is AGP or not.
1395 * All Intel graphics chipsets are treated as AGP, even if they are really
1398 * \param dev The device to be tested.
1401 * A value of 1 is always retured to indictate every i9x5 is AGP.
1403 int i915_driver_device_is_agp(struct drm_device * dev)
1408 int i915_driver_firstopen(struct drm_device *dev)
1410 #ifdef I915_HAVE_BUFFER
1411 drm_bo_driver_init(dev);