shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2)
  38
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 10000; i++) {
  53                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  54                 ring->space = ring->head - (ring->tail + 8);
  55                 if (ring->space < 0)
  56                         ring->space += ring->Size;
  57                 if (ring->space >= n)
  58                         return 0;
  59
  60                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61
  62                 if (ring->head != last_head)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 DRM_UDELAY(1);
  67         }
  68
  69         return DRM_ERR(EBUSY);
  70 }
  71
  72 void i915_kernel_lost_context(drm_device_t * dev)
  73 {
  74         drm_i915_private_t *dev_priv = dev->dev_private;
  75         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  76
  77         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  78         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  79         ring->space = ring->head - (ring->tail + 8);
  80         if (ring->space < 0)
  81                 ring->space += ring->Size;
  82
  83         if (ring->head == ring->tail)
  84                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  85 }
  86
  87 static int i915_dma_cleanup(drm_device_t * dev)
  88 {
  89         /* Make sure interrupts are disabled here because the uninstall ioctl
  90          * may not have been called from userspace and after dev_private
  91          * is freed, it's too late.
  92          */
  93         if (dev->irq)
  94                 drm_irq_uninstall(dev);
  95
  96         if (dev->dev_private) {
  97                 drm_i915_private_t *dev_priv =
  98                     (drm_i915_private_t *) dev->dev_private;
  99
 100                 if (dev_priv->ring.virtual_start) {
 101                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 102                 }
 103
 104                 if (dev_priv->status_page_dmah) {
 105                         drm_pci_free(dev, dev_priv->status_page_dmah);
 106                         /* Need to rewrite hardware status page */
 107                         I915_WRITE(0x02080, 0x1ffff000);
 108                 }
 109
 110                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 111                          DRM_MEM_DRIVER);
 112
 113                 dev->dev_private = NULL;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static int i915_initialize(drm_device_t * dev,
 120                            drm_i915_private_t * dev_priv,
 121                            drm_i915_init_t * init)
 122 {
 123         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 124
 125         DRM_GETSAREA();
 126         if (!dev_priv->sarea) {
 127                 DRM_ERROR("can not find sarea!\n");
 128                 dev->dev_private = (void *)dev_priv;
 129                 i915_dma_cleanup(dev);
 130                 return DRM_ERR(EINVAL);
 131         }
 132
 133         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 134         if (!dev_priv->mmio_map) {
 135                 dev->dev_private = (void *)dev_priv;
 136                 i915_dma_cleanup(dev);
 137                 DRM_ERROR("can not find mmio map!\n");
 138                 return DRM_ERR(EINVAL);
 139         }
 140
 141         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 142             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 143
 144         dev_priv->ring.Start = init->ring_start;
 145         dev_priv->ring.End = init->ring_end;
 146         dev_priv->ring.Size = init->ring_size;
 147         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 148
 149         dev_priv->ring.map.offset = init->ring_start;
 150         dev_priv->ring.map.size = init->ring_size;
 151         dev_priv->ring.map.type = 0;
 152         dev_priv->ring.map.flags = 0;
 153         dev_priv->ring.map.mtrr = 0;
 154
 155         drm_core_ioremap(&dev_priv->ring.map, dev);
 156
 157         if (dev_priv->ring.map.handle == NULL) {
 158                 dev->dev_private = (void *)dev_priv;
 159                 i915_dma_cleanup(dev);
 160                 DRM_ERROR("can not ioremap virtual address for"
 161                           " ring buffer\n");
 162                 return DRM_ERR(ENOMEM);
 163         }
 164
 165         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 166
 167         dev_priv->cpp = init->cpp;
 168         dev_priv->back_offset = init->back_offset;
 169         dev_priv->front_offset = init->front_offset;
 170         dev_priv->current_page = 0;
 171         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 172
 173         /* We are using separate values as placeholders for mechanisms for
 174          * private backbuffer/depthbuffer usage.
 175          */
 176         dev_priv->use_mi_batchbuffer_start = 0;
 177
 178         /* Allow hardware batchbuffers unless told otherwise.
 179          */
 180         dev_priv->allow_batchbuffer = 1;
 181
 182         /* Program Hardware Status Page */
 183         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 184             0xffffffff);
 185
 186         if (!dev_priv->status_page_dmah) {
 187                 dev->dev_private = (void *)dev_priv;
 188                 i915_dma_cleanup(dev);
 189                 DRM_ERROR("Can not allocate hardware status page\n");
 190                 return DRM_ERR(ENOMEM);
 191         }
 192         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 193         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 194
 195         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 196         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 197
 198         I915_WRITE(0x02080, dev_priv->dma_status_page);
 199         DRM_DEBUG("Enabled hardware status page\n");
 200         dev->dev_private = (void *)dev_priv;
 201 #ifdef I915_HAVE_BUFFER
 202         drm_bo_driver_init(dev);
 203 #endif
 204         return 0;
 205 }
 206
 207 static int i915_dma_resume(drm_device_t * dev)
 208 {
 209         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 210
 211         DRM_DEBUG("%s\n", __FUNCTION__);
 212
 213         if (!dev_priv->sarea) {
 214                 DRM_ERROR("can not find sarea!\n");
 215                 return DRM_ERR(EINVAL);
 216         }
 217
 218         if (!dev_priv->mmio_map) {
 219                 DRM_ERROR("can not find mmio map!\n");
 220                 return DRM_ERR(EINVAL);
 221         }
 222
 223         if (dev_priv->ring.map.handle == NULL) {
 224                 DRM_ERROR("can not ioremap virtual address for"
 225                           " ring buffer\n");
 226                 return DRM_ERR(ENOMEM);
 227         }
 228
 229         /* Program Hardware Status Page */
 230         if (!dev_priv->hw_status_page) {
 231                 DRM_ERROR("Can not find hardware status page\n");
 232                 return DRM_ERR(EINVAL);
 233         }
 234         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 235
 236         I915_WRITE(0x02080, dev_priv->dma_status_page);
 237         DRM_DEBUG("Enabled hardware status page\n");
 238
 239         return 0;
 240 }
 241
 242 static int i915_dma_init(DRM_IOCTL_ARGS)
 243 {
 244         DRM_DEVICE;
 245         drm_i915_private_t *dev_priv;
 246         drm_i915_init_t init;
 247         int retcode = 0;
 248
 249         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 250                                  sizeof(init));
 251
 252         switch (init.func) {
 253         case I915_INIT_DMA:
 254                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 255                                      DRM_MEM_DRIVER);
 256                 if (dev_priv == NULL)
 257                         return DRM_ERR(ENOMEM);
 258                 retcode = i915_initialize(dev, dev_priv, &init);
 259                 break;
 260         case I915_CLEANUP_DMA:
 261                 retcode = i915_dma_cleanup(dev);
 262                 break;
 263         case I915_RESUME_DMA:
 264                 retcode = i915_dma_resume(dev);
 265                 break;
 266         default:
 267                 retcode = DRM_ERR(EINVAL);
 268                 break;
 269         }
 270
 271         return retcode;
 272 }
 273
 274 /* Implement basically the same security restrictions as hardware does
 275  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 276  *
 277  * Most of the calculations below involve calculating the size of a
 278  * particular instruction.  It's important to get the size right as
 279  * that tells us where the next instruction to check is.  Any illegal
 280  * instruction detected will be given a size of zero, which is a
 281  * signal to abort the rest of the buffer.
 282  */
 283 static int do_validate_cmd(int cmd)
 284 {
 285         switch (((cmd >> 29) & 0x7)) {
 286         case 0x0:
 287                 switch ((cmd >> 23) & 0x3f) {
 288                 case 0x0:
 289                         return 1;       /* MI_NOOP */
 290                 case 0x4:
 291                         return 1;       /* MI_FLUSH */
 292                 default:
 293                         return 0;       /* disallow everything else */
 294                 }
 295                 break;
 296         case 0x1:
 297                 return 0;       /* reserved */
 298         case 0x2:
 299                 return (cmd & 0xff) + 2;        /* 2d commands */
 300         case 0x3:
 301                 if (((cmd >> 24) & 0x1f) <= 0x18)
 302                         return 1;
 303
 304                 switch ((cmd >> 24) & 0x1f) {
 305                 case 0x1c:
 306                         return 1;
 307                 case 0x1d:
 308                         switch ((cmd >> 16) & 0xff) {
 309                         case 0x3:
 310                                 return (cmd & 0x1f) + 2;
 311                         case 0x4:
 312                                 return (cmd & 0xf) + 2;
 313                         default:
 314                                 return (cmd & 0xffff) + 2;
 315                         }
 316                 case 0x1e:
 317                         if (cmd & (1 << 23))
 318                                 return (cmd & 0xffff) + 1;
 319                         else
 320                                 return 1;
 321                 case 0x1f:
 322                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 323                                 return (cmd & 0x1ffff) + 2;
 324                         else if (cmd & (1 << 17))       /* indirect random */
 325                                 if ((cmd & 0xffff) == 0)
 326                                         return 0;       /* unknown length, too hard */
 327                                 else
 328                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 329                         else
 330                                 return 2;       /* indirect sequential */
 331                 default:
 332                         return 0;
 333                 }
 334         default:
 335                 return 0;
 336         }
 337
 338         return 0;
 339 }
 340
 341 static int validate_cmd(int cmd)
 342 {
 343         int ret = do_validate_cmd(cmd);
 344
 345 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 346
 347         return ret;
 348 }
 349
 350 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 351 {
 352         drm_i915_private_t *dev_priv = dev->dev_private;
 353         int i;
 354         RING_LOCALS;
 355
 356         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 357                 return DRM_ERR(EINVAL);
 358
 359         BEGIN_LP_RING((dwords+1)&~1);
 360
 361         for (i = 0; i < dwords;) {
 362                 int cmd, sz;
 363
 364                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 365                         return DRM_ERR(EINVAL);
 366
 367                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 368                         return DRM_ERR(EINVAL);
 369
 370                 OUT_RING(cmd);
 371
 372                 while (++i, --sz) {
 373                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 374                                                          sizeof(cmd))) {
 375                                 return DRM_ERR(EINVAL);
 376                         }
 377                         OUT_RING(cmd);
 378                 }
 379         }
 380
 381         if (dwords & 1)
 382                 OUT_RING(0);
 383
 384         ADVANCE_LP_RING();
 385
 386         return 0;
 387 }
 388
 389 static int i915_emit_box(drm_device_t * dev,
 390                          drm_clip_rect_t __user * boxes,
 391                          int i, int DR1, int DR4)
 392 {
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         drm_clip_rect_t box;
 395         RING_LOCALS;
 396
 397         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 398                 return DRM_ERR(EFAULT);
 399         }
 400
 401         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 402                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 403                           box.x1, box.y1, box.x2, box.y2);
 404                 return DRM_ERR(EINVAL);
 405         }
 406
 407         if (IS_I965G(dev)) {
 408                 BEGIN_LP_RING(4);
 409                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 410                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 411                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 412                 OUT_RING(DR4);
 413                 ADVANCE_LP_RING();
 414         } else {
 415                 BEGIN_LP_RING(6);
 416                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 417                 OUT_RING(DR1);
 418                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 419                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 420                 OUT_RING(DR4);
 421                 OUT_RING(0);
 422                 ADVANCE_LP_RING();
 423         }
 424
 425         return 0;
 426 }
 427
 428 /* XXX: Emitting the counter should really be moved to part of the IRQ
 429  * emit.  For now, do it in both places:
 430  */
 431
 432 static void i915_emit_breadcrumb(drm_device_t *dev)
 433 {
 434         drm_i915_private_t *dev_priv = dev->dev_private;
 435         RING_LOCALS;
 436
 437         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 438
 439         BEGIN_LP_RING(4);
 440         OUT_RING(CMD_STORE_DWORD_IDX);
 441         OUT_RING(20);
 442         OUT_RING(dev_priv->counter);
 443         OUT_RING(0);
 444         ADVANCE_LP_RING();
 445 #ifdef I915_HAVE_FENCE
 446         drm_fence_flush_old(dev, dev_priv->counter);
 447 #endif
 448 }
 449
 450
 451 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 452 {
 453         drm_i915_private_t *dev_priv = dev->dev_private;
 454         uint32_t flush_cmd = CMD_MI_FLUSH;
 455         RING_LOCALS;
 456
 457         flush_cmd |= flush;
 458
 459         i915_kernel_lost_context(dev);
 460
 461         BEGIN_LP_RING(4);
 462         OUT_RING(flush_cmd);
 463         OUT_RING(0);
 464         OUT_RING(0);
 465         OUT_RING(0);
 466         ADVANCE_LP_RING();
 467
 468         return 0;
 469 }
 470
 471
 472 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 473                                    drm_i915_cmdbuffer_t * cmd)
 474 {
 475         int nbox = cmd->num_cliprects;
 476         int i = 0, count, ret;
 477
 478         if (cmd->sz & 0x3) {
 479                 DRM_ERROR("alignment");
 480                 return DRM_ERR(EINVAL);
 481         }
 482
 483         i915_kernel_lost_context(dev);
 484
 485         count = nbox ? nbox : 1;
 486
 487         for (i = 0; i < count; i++) {
 488                 if (i < nbox) {
 489                         ret = i915_emit_box(dev, cmd->cliprects, i,
 490                                             cmd->DR1, cmd->DR4);
 491                         if (ret)
 492                                 return ret;
 493                 }
 494
 495                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 496                 if (ret)
 497                         return ret;
 498         }
 499
 500         i915_emit_breadcrumb( dev );
 501         return 0;
 502 }
 503
 504 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 505                                      drm_i915_batchbuffer_t * batch)
 506 {
 507         drm_i915_private_t *dev_priv = dev->dev_private;
 508         drm_clip_rect_t __user *boxes = batch->cliprects;
 509         int nbox = batch->num_cliprects;
 510         int i = 0, count;
 511         RING_LOCALS;
 512
 513         if ((batch->start | batch->used) & 0x7) {
 514                 DRM_ERROR("alignment");
 515                 return DRM_ERR(EINVAL);
 516         }
 517
 518         i915_kernel_lost_context(dev);
 519
 520         count = nbox ? nbox : 1;
 521
 522         for (i = 0; i < count; i++) {
 523                 if (i < nbox) {
 524                         int ret = i915_emit_box(dev, boxes, i,
 525                                                 batch->DR1, batch->DR4);
 526                         if (ret)
 527                                 return ret;
 528                 }
 529
 530                 if (dev_priv->use_mi_batchbuffer_start) {
 531                         BEGIN_LP_RING(2);
 532                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 533                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 534                         ADVANCE_LP_RING();
 535                 } else {
 536                         BEGIN_LP_RING(4);
 537                         OUT_RING(MI_BATCH_BUFFER);
 538                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 539                         OUT_RING(batch->start + batch->used - 4);
 540                         OUT_RING(0);
 541                         ADVANCE_LP_RING();
 542                 }
 543         }
 544
 545         i915_emit_breadcrumb( dev );
 546         return 0;
 547 }
 548
 549 static int i915_dispatch_flip(drm_device_t * dev)
 550 {
 551         drm_i915_private_t *dev_priv = dev->dev_private;
 552         RING_LOCALS;
 553
 554         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 555                   __FUNCTION__,
 556                   dev_priv->current_page,
 557                   dev_priv->sarea_priv->pf_current_page);
 558
 559         i915_kernel_lost_context(dev);
 560
 561         BEGIN_LP_RING(2);
 562         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 563         OUT_RING(0);
 564         ADVANCE_LP_RING();
 565
 566         BEGIN_LP_RING(6);
 567         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 568         OUT_RING(0);
 569         if (dev_priv->current_page == 0) {
 570                 OUT_RING(dev_priv->back_offset);
 571                 dev_priv->current_page = 1;
 572         } else {
 573                 OUT_RING(dev_priv->front_offset);
 574                 dev_priv->current_page = 0;
 575         }
 576         OUT_RING(0);
 577         ADVANCE_LP_RING();
 578
 579         BEGIN_LP_RING(2);
 580         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 581         OUT_RING(0);
 582         ADVANCE_LP_RING();
 583
 584         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 585
 586         BEGIN_LP_RING(4);
 587         OUT_RING(CMD_STORE_DWORD_IDX);
 588         OUT_RING(20);
 589         OUT_RING(dev_priv->counter);
 590         OUT_RING(0);
 591         ADVANCE_LP_RING();
 592 #ifdef I915_HAVE_FENCE
 593         drm_fence_flush_old(dev, dev_priv->counter);
 594 #endif
 595         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 596         return 0;
 597 }
 598
 599 static int i915_quiescent(drm_device_t * dev)
 600 {
 601         drm_i915_private_t *dev_priv = dev->dev_private;
 602
 603         i915_kernel_lost_context(dev);
 604         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 605 }
 606
 607 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 608 {
 609         DRM_DEVICE;
 610
 611         LOCK_TEST_WITH_RETURN(dev, filp);
 612
 613         return i915_quiescent(dev);
 614 }
 615
 616 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 617 {
 618         DRM_DEVICE;
 619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 620         u32 *hw_status = dev_priv->hw_status_page;
 621         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 622             dev_priv->sarea_priv;
 623         drm_i915_batchbuffer_t batch;
 624         int ret;
 625
 626         if (!dev_priv->allow_batchbuffer) {
 627                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 628                 return DRM_ERR(EINVAL);
 629         }
 630
 631         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 632                                  sizeof(batch));
 633
 634         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 635                   batch.start, batch.used, batch.num_cliprects);
 636
 637         LOCK_TEST_WITH_RETURN(dev, filp);
 638
 639         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 640                                                        batch.num_cliprects *
 641                                                        sizeof(drm_clip_rect_t)))
 642                 return DRM_ERR(EFAULT);
 643
 644         ret = i915_dispatch_batchbuffer(dev, &batch);
 645
 646         sarea_priv->last_dispatch = (int)hw_status[5];
 647         return ret;
 648 }
 649
 650 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 651 {
 652         DRM_DEVICE;
 653         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 654         u32 *hw_status = dev_priv->hw_status_page;
 655         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 656             dev_priv->sarea_priv;
 657         drm_i915_cmdbuffer_t cmdbuf;
 658         int ret;
 659
 660         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 661                                  sizeof(cmdbuf));
 662
 663         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 664                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 665
 666         LOCK_TEST_WITH_RETURN(dev, filp);
 667
 668         if (cmdbuf.num_cliprects &&
 669             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 670                                 cmdbuf.num_cliprects *
 671                                 sizeof(drm_clip_rect_t))) {
 672                 DRM_ERROR("Fault accessing cliprects\n");
 673                 return DRM_ERR(EFAULT);
 674         }
 675
 676         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 677         if (ret) {
 678                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 679                 return ret;
 680         }
 681
 682         sarea_priv->last_dispatch = (int)hw_status[5];
 683         return 0;
 684 }
 685
 686 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 687 {
 688         drm_i915_private_t *dev_priv = dev->dev_private;
 689
 690         DRM_DEBUG("%s\n", __FUNCTION__);
 691         if (dev_priv->current_page != 0)
 692                 i915_dispatch_flip(dev);
 693
 694         return 0;
 695 }
 696
 697 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 698 {
 699         DRM_DEVICE;
 700
 701         DRM_DEBUG("%s\n", __FUNCTION__);
 702
 703         LOCK_TEST_WITH_RETURN(dev, filp);
 704
 705         return i915_dispatch_flip(dev);
 706 }
 707
 708
 709 static int i915_getparam(DRM_IOCTL_ARGS)
 710 {
 711         DRM_DEVICE;
 712         drm_i915_private_t *dev_priv = dev->dev_private;
 713         drm_i915_getparam_t param;
 714         int value;
 715
 716         if (!dev_priv) {
 717                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 718                 return DRM_ERR(EINVAL);
 719         }
 720
 721         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 722                                  sizeof(param));
 723
 724         switch (param.param) {
 725         case I915_PARAM_IRQ_ACTIVE:
 726                 value = dev->irq ? 1 : 0;
 727                 break;
 728         case I915_PARAM_ALLOW_BATCHBUFFER:
 729                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 730                 break;
 731         case I915_PARAM_LAST_DISPATCH:
 732                 value = READ_BREADCRUMB(dev_priv);
 733                 break;
 734         default:
 735                 DRM_ERROR("Unknown parameter %d\n", param.param);
 736                 return DRM_ERR(EINVAL);
 737         }
 738
 739         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 740                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 741                 return DRM_ERR(EFAULT);
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int i915_setparam(DRM_IOCTL_ARGS)
 748 {
 749         DRM_DEVICE;
 750         drm_i915_private_t *dev_priv = dev->dev_private;
 751         drm_i915_setparam_t param;
 752
 753         if (!dev_priv) {
 754                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 755                 return DRM_ERR(EINVAL);
 756         }
 757
 758         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 759                                  sizeof(param));
 760
 761         switch (param.param) {
 762         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 763                 dev_priv->use_mi_batchbuffer_start = param.value;
 764                 break;
 765         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 766                 dev_priv->tex_lru_log_granularity = param.value;
 767                 break;
 768         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 769                 dev_priv->allow_batchbuffer = param.value;
 770                 break;
 771         default:
 772                 DRM_ERROR("unknown parameter %d\n", param.param);
 773                 return DRM_ERR(EINVAL);
 774         }
 775
 776         return 0;
 777 }
 778
 779 drm_i915_mmio_entry_t mmio_table[] = {
 780         [MMIO_REGS_PS_DEPTH_COUNT] = {
 781                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 782                 0x2350,
 783                 8
 784         }
 785 };
 786
 787 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 788
 789 static int i915_mmio(DRM_IOCTL_ARGS)
 790 {
 791         char buf[32];
 792         DRM_DEVICE;
 793         drm_i915_private_t *dev_priv = dev->dev_private;
 794         drm_i915_mmio_entry_t *e;
 795         drm_i915_mmio_t mmio;
 796         void __iomem *base;
 797         if (!dev_priv) {
 798                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 799                 return DRM_ERR(EINVAL);
 800         }
 801         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_setparam_t __user *) data,
 802                                  sizeof(mmio));
 803
 804         if (mmio.reg >= mmio_table_size)
 805                 return DRM_ERR(EINVAL);
 806
 807         e = &mmio_table[mmio.reg];
 808         base = dev_priv->mmio_map->handle + e->offset;
 809
 810         switch (mmio.read_write) {
 811                 case I915_MMIO_READ:
 812                         if (!(e->flag & I915_MMIO_MAY_READ))
 813                                 return DRM_ERR(EINVAL);
 814                         memcpy_fromio(buf, base, e->size);
 815                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 816                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 817                                 return DRM_ERR(EFAULT);
 818                         }
 819                         break;
 820
 821                 case I915_MMIO_WRITE:
 822                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 823                                 return DRM_ERR(EINVAL);
 824                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 825                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 826                                 return DRM_ERR(EFAULT);
 827                         }
 828                         memcpy_toio(base, buf, e->size);
 829                         break;
 830         }
 831         return 0;
 832 }
 833
 834 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 835 {
 836         /* i915 has 4 more counters */
 837         dev->counters += 4;
 838         dev->types[6] = _DRM_STAT_IRQ;
 839         dev->types[7] = _DRM_STAT_PRIMARY;
 840         dev->types[8] = _DRM_STAT_SECONDARY;
 841         dev->types[9] = _DRM_STAT_DMA;
 842
 843         return 0;
 844 }
 845
 846 void i915_driver_lastclose(drm_device_t * dev)
 847 {
 848         if (dev->dev_private) {
 849                 drm_i915_private_t *dev_priv = dev->dev_private;
 850                 i915_mem_takedown(&(dev_priv->agp_heap));
 851         }
 852         i915_dma_cleanup(dev);
 853 }
 854
 855 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 856 {
 857         if (dev->dev_private) {
 858                 drm_i915_private_t *dev_priv = dev->dev_private;
 859                 if (dev_priv->page_flipping) {
 860                         i915_do_cleanup_pageflip(dev);
 861                 }
 862                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 863         }
 864 }
 865
 866 drm_ioctl_desc_t i915_ioctls[] = {
 867         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 868         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 869         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 870         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 871         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 872         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 873         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 874         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 875         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 876         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 877         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 878         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 879         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 880         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 881         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 882         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 883         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 884 };
 885
 886 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 887
 888 /**
 889  * Determine if the device really is AGP or not.
 890  *
 891  * All Intel graphics chipsets are treated as AGP, even if they are really
 892  * PCI-e.
 893  *
 894  * \param dev   The device to be tested.
 895  *
 896  * \returns
 897  * A value of 1 is always retured to indictate every i9x5 is AGP.
 898  */
 899 int i915_driver_device_is_agp(drm_device_t * dev)
 900 {
 901         return 1;
 902 }