1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2 || \
38 dev->pci_device == 0x2A02 || \
39 dev->pci_device == 0x2A12)
41 #define IS_G33(dev) (dev->pci_device == 0x29C2 || \
42 dev->pci_device == 0x29B2 || \
43 dev->pci_device == 0x29D2)
45 /* Really want an OS-independent resettable timer. Would like to have
46 * this loop run for (eg) 3 sec, but have the timer reset every time
47 * the head pointer changes, so that EBUSY only happens if the ring
48 * actually stalls for (eg) 3 seconds.
50 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
54 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
57 for (i = 0; i < 10000; i++) {
58 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
59 ring->space = ring->head - (ring->tail + 8);
61 ring->space += ring->Size;
65 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
67 if (ring->head != last_head)
70 last_head = ring->head;
77 void i915_kernel_lost_context(struct drm_device * dev)
79 drm_i915_private_t *dev_priv = dev->dev_private;
80 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
82 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
83 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
84 ring->space = ring->head - (ring->tail + 8);
86 ring->space += ring->Size;
88 if (ring->head == ring->tail)
89 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
92 static int i915_dma_cleanup(struct drm_device * dev)
94 /* Make sure interrupts are disabled here because the uninstall ioctl
95 * may not have been called from userspace and after dev_private
96 * is freed, it's too late.
99 drm_irq_uninstall(dev);
101 if (dev->dev_private) {
102 drm_i915_private_t *dev_priv =
103 (drm_i915_private_t *) dev->dev_private;
105 if (dev_priv->ring.virtual_start) {
106 drm_core_ioremapfree(&dev_priv->ring.map, dev);
109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 /* Need to rewrite hardware status page */
112 I915_WRITE(0x02080, 0x1ffff000);
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 I915_WRITE(0x02080, 0x1ffff000);
119 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
122 dev->dev_private = NULL;
128 static int i915_initialize(struct drm_device * dev,
129 drm_i915_private_t * dev_priv,
130 drm_i915_init_t * init)
132 memset(dev_priv, 0, sizeof(drm_i915_private_t));
134 dev_priv->sarea = drm_getsarea(dev);
135 if (!dev_priv->sarea) {
136 DRM_ERROR("can not find sarea!\n");
137 dev->dev_private = (void *)dev_priv;
138 i915_dma_cleanup(dev);
142 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
143 if (!dev_priv->mmio_map) {
144 dev->dev_private = (void *)dev_priv;
145 i915_dma_cleanup(dev);
146 DRM_ERROR("can not find mmio map!\n");
150 #ifdef I915_HAVE_BUFFER
151 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
154 dev_priv->sarea_priv = (drm_i915_sarea_t *)
155 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
157 dev_priv->ring.Start = init->ring_start;
158 dev_priv->ring.End = init->ring_end;
159 dev_priv->ring.Size = init->ring_size;
160 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
162 dev_priv->ring.map.offset = init->ring_start;
163 dev_priv->ring.map.size = init->ring_size;
164 dev_priv->ring.map.type = 0;
165 dev_priv->ring.map.flags = 0;
166 dev_priv->ring.map.mtrr = 0;
168 drm_core_ioremap(&dev_priv->ring.map, dev);
170 if (dev_priv->ring.map.handle == NULL) {
171 dev->dev_private = (void *)dev_priv;
172 i915_dma_cleanup(dev);
173 DRM_ERROR("can not ioremap virtual address for"
178 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
180 dev_priv->cpp = init->cpp;
181 dev_priv->sarea_priv->pf_current_page = 0;
183 /* We are using separate values as placeholders for mechanisms for
184 * private backbuffer/depthbuffer usage.
186 dev_priv->use_mi_batchbuffer_start = 0;
188 /* Allow hardware batchbuffers unless told otherwise.
190 dev_priv->allow_batchbuffer = 1;
192 /* Enable vblank on pipe A for older X servers
194 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
196 /* Program Hardware Status Page */
198 dev_priv->status_page_dmah =
199 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
201 if (!dev_priv->status_page_dmah) {
202 dev->dev_private = (void *)dev_priv;
203 i915_dma_cleanup(dev);
204 DRM_ERROR("Can not allocate hardware status page\n");
207 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
208 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
210 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
212 I915_WRITE(0x02080, dev_priv->dma_status_page);
214 DRM_DEBUG("Enabled hardware status page\n");
215 dev->dev_private = (void *)dev_priv;
219 static int i915_dma_resume(struct drm_device * dev)
221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
223 DRM_DEBUG("%s\n", __FUNCTION__);
225 if (!dev_priv->sarea) {
226 DRM_ERROR("can not find sarea!\n");
230 if (!dev_priv->mmio_map) {
231 DRM_ERROR("can not find mmio map!\n");
235 if (dev_priv->ring.map.handle == NULL) {
236 DRM_ERROR("can not ioremap virtual address for"
241 /* Program Hardware Status Page */
242 if (!dev_priv->hw_status_page) {
243 DRM_ERROR("Can not find hardware status page\n");
246 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
248 if (dev_priv->status_gfx_addr != 0)
249 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
251 I915_WRITE(0x02080, dev_priv->dma_status_page);
252 DRM_DEBUG("Enabled hardware status page\n");
257 static int i915_dma_init(struct drm_device *dev, void *data,
258 struct drm_file *file_priv)
260 drm_i915_private_t *dev_priv;
261 drm_i915_init_t *init = data;
264 switch (init->func) {
266 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
268 if (dev_priv == NULL)
270 retcode = i915_initialize(dev, dev_priv, init);
272 case I915_CLEANUP_DMA:
273 retcode = i915_dma_cleanup(dev);
275 case I915_RESUME_DMA:
276 retcode = i915_dma_resume(dev);
286 /* Implement basically the same security restrictions as hardware does
287 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
289 * Most of the calculations below involve calculating the size of a
290 * particular instruction. It's important to get the size right as
291 * that tells us where the next instruction to check is. Any illegal
292 * instruction detected will be given a size of zero, which is a
293 * signal to abort the rest of the buffer.
295 static int do_validate_cmd(int cmd)
297 switch (((cmd >> 29) & 0x7)) {
299 switch ((cmd >> 23) & 0x3f) {
301 return 1; /* MI_NOOP */
303 return 1; /* MI_FLUSH */
305 return 0; /* disallow everything else */
309 return 0; /* reserved */
311 return (cmd & 0xff) + 2; /* 2d commands */
313 if (((cmd >> 24) & 0x1f) <= 0x18)
316 switch ((cmd >> 24) & 0x1f) {
320 switch ((cmd >> 16) & 0xff) {
322 return (cmd & 0x1f) + 2;
324 return (cmd & 0xf) + 2;
326 return (cmd & 0xffff) + 2;
330 return (cmd & 0xffff) + 1;
334 if ((cmd & (1 << 23)) == 0) /* inline vertices */
335 return (cmd & 0x1ffff) + 2;
336 else if (cmd & (1 << 17)) /* indirect random */
337 if ((cmd & 0xffff) == 0)
338 return 0; /* unknown length, too hard */
340 return (((cmd & 0xffff) + 1) / 2) + 1;
342 return 2; /* indirect sequential */
353 static int validate_cmd(int cmd)
355 int ret = do_validate_cmd(cmd);
357 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
362 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
365 drm_i915_private_t *dev_priv = dev->dev_private;
369 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
372 BEGIN_LP_RING((dwords+1)&~1);
374 for (i = 0; i < dwords;) {
377 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
380 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
386 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
402 static int i915_emit_box(struct drm_device * dev,
403 struct drm_clip_rect __user * boxes,
404 int i, int DR1, int DR4)
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 struct drm_clip_rect box;
410 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
414 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
415 DRM_ERROR("Bad box %d,%d..%d,%d\n",
416 box.x1, box.y1, box.x2, box.y2);
422 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
423 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
424 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
429 OUT_RING(GFX_OP_DRAWRECT_INFO);
431 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
432 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
441 /* XXX: Emitting the counter should really be moved to part of the IRQ
442 * emit. For now, do it in both places:
445 void i915_emit_breadcrumb(struct drm_device *dev)
447 drm_i915_private_t *dev_priv = dev->dev_private;
450 if (++dev_priv->counter > BREADCRUMB_MASK) {
451 dev_priv->counter = 1;
452 DRM_DEBUG("Breadcrumb counter wrapped around\n");
455 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
458 OUT_RING(CMD_STORE_DWORD_IDX);
460 OUT_RING(dev_priv->counter);
466 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
468 drm_i915_private_t *dev_priv = dev->dev_private;
469 uint32_t flush_cmd = CMD_MI_FLUSH;
474 i915_kernel_lost_context(dev);
487 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
488 drm_i915_cmdbuffer_t * cmd)
490 #ifdef I915_HAVE_FENCE
491 drm_i915_private_t *dev_priv = dev->dev_private;
493 int nbox = cmd->num_cliprects;
494 int i = 0, count, ret;
497 DRM_ERROR("alignment");
501 i915_kernel_lost_context(dev);
503 count = nbox ? nbox : 1;
505 for (i = 0; i < count; i++) {
507 ret = i915_emit_box(dev, cmd->cliprects, i,
513 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
518 i915_emit_breadcrumb( dev );
519 #ifdef I915_HAVE_FENCE
520 drm_fence_flush_old(dev, 0, dev_priv->counter);
525 static int i915_dispatch_batchbuffer(struct drm_device * dev,
526 drm_i915_batchbuffer_t * batch)
528 drm_i915_private_t *dev_priv = dev->dev_private;
529 struct drm_clip_rect __user *boxes = batch->cliprects;
530 int nbox = batch->num_cliprects;
534 if ((batch->start | batch->used) & 0x7) {
535 DRM_ERROR("alignment");
539 i915_kernel_lost_context(dev);
541 count = nbox ? nbox : 1;
543 for (i = 0; i < count; i++) {
545 int ret = i915_emit_box(dev, boxes, i,
546 batch->DR1, batch->DR4);
551 if (dev_priv->use_mi_batchbuffer_start) {
554 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
555 OUT_RING(batch->start);
557 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
558 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
564 OUT_RING(MI_BATCH_BUFFER);
565 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
566 OUT_RING(batch->start + batch->used - 4);
572 i915_emit_breadcrumb( dev );
573 #ifdef I915_HAVE_FENCE
574 drm_fence_flush_old(dev, 0, dev_priv->counter);
579 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
581 drm_i915_private_t *dev_priv = dev->dev_private;
582 u32 num_pages, current_page, next_page, dspbase;
583 int shift = 2 * plane, x, y;
586 /* Calculate display base offset */
587 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
588 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
589 next_page = (current_page + 1) % num_pages;
594 dspbase = dev_priv->sarea_priv->front_offset;
597 dspbase = dev_priv->sarea_priv->back_offset;
600 dspbase = dev_priv->sarea_priv->third_offset;
605 x = dev_priv->sarea_priv->planeA_x;
606 y = dev_priv->sarea_priv->planeA_y;
608 x = dev_priv->sarea_priv->planeB_x;
609 y = dev_priv->sarea_priv->planeB_y;
612 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
614 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
619 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
620 MI_WAIT_FOR_PLANE_A_FLIP)));
621 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
622 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
623 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
627 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
628 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
631 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
633 drm_i915_private_t *dev_priv = dev->dev_private;
636 DRM_DEBUG("%s: planes=0x%x pfCurrentPage=%d\n",
638 planes, dev_priv->sarea_priv->pf_current_page);
640 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
642 for (i = 0; i < 2; i++)
643 if (planes & (1 << i))
644 i915_do_dispatch_flip(dev, i, sync);
646 i915_emit_breadcrumb(dev);
647 #ifdef I915_HAVE_FENCE
649 drm_fence_flush_old(dev, 0, dev_priv->counter);
653 static int i915_quiescent(struct drm_device * dev)
655 drm_i915_private_t *dev_priv = dev->dev_private;
657 i915_kernel_lost_context(dev);
658 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
661 static int i915_flush_ioctl(struct drm_device *dev, void *data,
662 struct drm_file *file_priv)
665 LOCK_TEST_WITH_RETURN(dev, file_priv);
667 return i915_quiescent(dev);
670 static int i915_batchbuffer(struct drm_device *dev, void *data,
671 struct drm_file *file_priv)
673 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
674 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
675 dev_priv->sarea_priv;
676 drm_i915_batchbuffer_t *batch = data;
679 if (!dev_priv->allow_batchbuffer) {
680 DRM_ERROR("Batchbuffer ioctl disabled\n");
684 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
685 batch->start, batch->used, batch->num_cliprects);
687 LOCK_TEST_WITH_RETURN(dev, file_priv);
689 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
690 batch->num_cliprects *
691 sizeof(struct drm_clip_rect)))
694 ret = i915_dispatch_batchbuffer(dev, batch);
696 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
700 static int i915_cmdbuffer(struct drm_device *dev, void *data,
701 struct drm_file *file_priv)
703 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
704 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
705 dev_priv->sarea_priv;
706 drm_i915_cmdbuffer_t *cmdbuf = data;
709 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
710 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
712 LOCK_TEST_WITH_RETURN(dev, file_priv);
714 if (cmdbuf->num_cliprects &&
715 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
716 cmdbuf->num_cliprects *
717 sizeof(struct drm_clip_rect))) {
718 DRM_ERROR("Fault accessing cliprects\n");
722 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
724 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
728 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
732 #ifdef I915_HAVE_BUFFER
733 struct i915_relocatee_info {
734 struct drm_buffer_object *buf;
735 unsigned long offset;
737 unsigned page_offset;
738 struct drm_bo_kmap_obj kmap;
742 static void i915_dereference_buffers_locked(struct drm_buffer_object **buffers,
743 unsigned num_buffers)
745 while (num_buffers--)
746 drm_bo_usage_deref_locked(&buffers[num_buffers]);
749 int i915_apply_reloc(struct drm_file *file_priv, int num_buffers,
750 struct drm_buffer_object **buffers,
751 struct i915_relocatee_info *relocatee,
755 unsigned long new_cmd_offset;
759 if (reloc[2] >= num_buffers) {
760 DRM_ERROR("Illegal relocation buffer %08X\n", reloc[2]);
764 new_cmd_offset = reloc[0];
765 if (!relocatee->data_page ||
766 !drm_bo_same_page(relocatee->offset, new_cmd_offset)) {
767 drm_bo_kunmap(&relocatee->kmap);
768 relocatee->offset = new_cmd_offset;
769 ret = drm_bo_kmap(relocatee->buf, new_cmd_offset >> PAGE_SHIFT,
770 1, &relocatee->kmap);
772 DRM_ERROR("Could not map command buffer to apply relocs\n %08lx", new_cmd_offset);
776 relocatee->data_page = drm_bmo_virtual(&relocatee->kmap,
777 &relocatee->is_iomem);
778 relocatee->page_offset = (relocatee->offset & PAGE_MASK);
781 val = buffers[reloc[2]]->offset;
782 index = (reloc[0] - relocatee->page_offset) >> 2;
784 /* add in validate */
785 val = val + reloc[1];
787 relocatee->data_page[index] = val;
791 int i915_process_relocs(struct drm_file *file_priv,
793 uint32_t *reloc_buf_handle,
794 struct i915_relocatee_info *relocatee,
795 struct drm_buffer_object **buffers,
796 uint32_t num_buffers)
798 struct drm_device *dev = file_priv->head->dev;
799 struct drm_buffer_object *reloc_list_object;
800 uint32_t cur_handle = *reloc_buf_handle;
801 uint32_t *reloc_page;
802 int ret, reloc_is_iomem, reloc_stride;
803 uint32_t num_relocs, reloc_offset, reloc_end, reloc_page_offset, next_offset, cur_offset;
804 struct drm_bo_kmap_obj reloc_kmap;
806 memset(&reloc_kmap, 0, sizeof(reloc_kmap));
808 reloc_list_object = drm_lookup_buffer_object(file_priv, cur_handle, 1);
809 if (!reloc_list_object)
812 ret = drm_bo_kmap(reloc_list_object, 0, 1, &reloc_kmap);
814 DRM_ERROR("Could not map relocation buffer.\n");
818 reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
819 num_relocs = reloc_page[0] & 0xffff;
821 if ((reloc_page[0] >> 16) & 0xffff) {
822 DRM_ERROR("Unsupported relocation type requested\n");
826 /* get next relocate buffer handle */
827 *reloc_buf_handle = reloc_page[1];
828 reloc_stride = I915_RELOC0_STRIDE * sizeof(uint32_t); /* may be different for other types of relocs */
830 DRM_DEBUG("num relocs is %d, next is %08X\n", num_relocs, reloc_page[1]);
832 reloc_page_offset = 0;
833 reloc_offset = I915_RELOC_HEADER * sizeof(uint32_t);
834 reloc_end = reloc_offset + (num_relocs * reloc_stride);
837 next_offset = drm_bo_offset_end(reloc_offset, reloc_end);
840 cur_offset = ((reloc_offset + reloc_page_offset) & ~PAGE_MASK) / sizeof(uint32_t);
841 ret = i915_apply_reloc(file_priv, num_buffers,
842 buffers, relocatee, &reloc_page[cur_offset]);
846 reloc_offset += reloc_stride;
847 } while (reloc_offset < next_offset);
849 drm_bo_kunmap(&reloc_kmap);
851 reloc_offset = next_offset;
852 if (reloc_offset != reloc_end) {
853 ret = drm_bo_kmap(reloc_list_object, reloc_offset >> PAGE_SHIFT, 1, &reloc_kmap);
855 DRM_ERROR("Could not map relocation buffer.\n");
859 reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
860 reloc_page_offset = reloc_offset & ~PAGE_MASK;
863 } while (reloc_offset != reloc_end);
865 drm_bo_kunmap(&reloc_kmap);
867 mutex_lock(&dev->struct_mutex);
868 drm_bo_usage_deref_locked(&reloc_list_object);
869 mutex_unlock(&dev->struct_mutex);
875 * Validate, add fence and relocate a block of bos from a userspace list
877 int i915_validate_buffer_list(struct drm_file *file_priv,
878 unsigned int fence_class, uint64_t data,
879 struct drm_buffer_object **buffers,
880 uint32_t *num_buffers)
882 struct drm_i915_op_arg arg;
883 struct drm_bo_op_req *req = &arg.d.req;
884 struct drm_bo_arg_rep rep;
885 unsigned long next = 0;
887 unsigned buf_count = 0;
888 struct drm_device *dev = file_priv->head->dev;
889 uint32_t buf_reloc_handle, buf_handle;
890 struct i915_relocatee_info relocatee;
893 if (buf_count >= *num_buffers) {
894 DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers);
899 buffers[buf_count] = NULL;
901 if (copy_from_user(&arg, (void __user *)(unsigned)data, sizeof(arg))) {
908 buffers[buf_count] = drm_lookup_buffer_object(file_priv, req->arg_handle, 1);
914 if (req->op != drm_bo_validate) {
916 ("Buffer object operation wasn't \"validate\".\n");
921 buf_handle = req->bo_req.handle;
922 buf_reloc_handle = arg.reloc_handle;
924 rep.ret = drm_bo_handle_validate(file_priv, req->bo_req.handle,
925 req->bo_req.fence_class,
930 &buffers[buf_count]);
933 DRM_ERROR("error on handle validate %d\n", rep.ret);
942 if (copy_to_user((void __user *)(unsigned)data, &arg, sizeof(arg)))
948 if (buf_reloc_handle) {
949 memset(&relocatee, 0, sizeof(relocatee));
951 relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1);
952 if (!relocatee.buf) {
953 DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle);
958 while (buf_reloc_handle) {
959 ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count);
961 DRM_ERROR("process relocs failed\n");
966 drm_bo_kunmap(&relocatee.kmap);
967 mutex_lock(&dev->struct_mutex);
968 drm_bo_usage_deref_locked(&relocatee.buf);
969 mutex_unlock(&dev->struct_mutex);
976 *num_buffers = buf_count;
979 mutex_lock(&dev->struct_mutex);
980 i915_dereference_buffers_locked(buffers, buf_count);
981 mutex_unlock(&dev->struct_mutex);
983 return (ret) ? ret : rep.ret;
986 static int i915_execbuffer(struct drm_device *dev, void *data,
987 struct drm_file *file_priv)
989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
990 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
991 dev_priv->sarea_priv;
992 struct drm_i915_execbuffer *exec_buf = data;
993 struct _drm_i915_batchbuffer *batch = &exec_buf->batch;
994 struct drm_fence_arg *fence_arg = &exec_buf->fence_arg;
997 struct drm_buffer_object **buffers;
998 struct drm_fence_object *fence;
1000 if (!dev_priv->allow_batchbuffer) {
1001 DRM_ERROR("Batchbuffer ioctl disabled\n");
1006 LOCK_TEST_WITH_RETURN(dev, file_priv);
1008 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
1009 batch->num_cliprects *
1010 sizeof(struct drm_clip_rect)))
1013 if (exec_buf->num_buffers > dev_priv->max_validate_buffers)
1016 num_buffers = exec_buf->num_buffers;
1018 buffers = drm_calloc(num_buffers, sizeof(struct drm_buffer_object *), DRM_MEM_DRIVER);
1022 /* validate buffer list + fixup relocations */
1023 ret = i915_validate_buffer_list(file_priv, 0, exec_buf->ops_list,
1024 buffers, &num_buffers);
1029 batch->start = buffers[num_buffers-1]->offset;
1031 DRM_DEBUG("i915 exec batchbuffer, start %x used %d cliprects %d\n",
1032 batch->start, batch->used, batch->num_cliprects);
1034 ret = i915_dispatch_batchbuffer(dev, batch);
1038 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1041 ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
1045 if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
1046 ret = drm_fence_add_user_object(file_priv, fence, fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE);
1048 fence_arg->handle = fence->base.hash.key;
1049 fence_arg->fence_class = fence->fence_class;
1050 fence_arg->type = fence->type;
1051 fence_arg->signaled = fence->signaled;
1054 drm_fence_usage_deref_unlocked(&fence);
1058 mutex_lock(&dev->struct_mutex);
1059 i915_dereference_buffers_locked(buffers, num_buffers);
1060 mutex_unlock(&dev->struct_mutex);
1063 drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER);
1069 static int i915_do_cleanup_pageflip(struct drm_device * dev)
1071 drm_i915_private_t *dev_priv = dev->dev_private;
1072 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
1074 DRM_DEBUG("%s\n", __FUNCTION__);
1076 for (i = 0, planes = 0; i < 2; i++)
1077 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
1078 dev_priv->sarea_priv->pf_current_page =
1079 (dev_priv->sarea_priv->pf_current_page &
1080 ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
1086 i915_dispatch_flip(dev, planes, 0);
1091 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
1093 drm_i915_flip_t *param = data;
1095 DRM_DEBUG("%s\n", __FUNCTION__);
1097 LOCK_TEST_WITH_RETURN(dev, file_priv);
1099 /* This is really planes */
1100 if (param->pipes & ~0x3) {
1101 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
1106 i915_dispatch_flip(dev, param->pipes, 0);
1112 static int i915_getparam(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv)
1115 drm_i915_private_t *dev_priv = dev->dev_private;
1116 drm_i915_getparam_t *param = data;
1120 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1124 switch (param->param) {
1125 case I915_PARAM_IRQ_ACTIVE:
1126 value = dev->irq ? 1 : 0;
1128 case I915_PARAM_ALLOW_BATCHBUFFER:
1129 value = dev_priv->allow_batchbuffer ? 1 : 0;
1131 case I915_PARAM_LAST_DISPATCH:
1132 value = READ_BREADCRUMB(dev_priv);
1135 DRM_ERROR("Unknown parameter %d\n", param->param);
1139 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1140 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1147 static int i915_setparam(struct drm_device *dev, void *data,
1148 struct drm_file *file_priv)
1150 drm_i915_private_t *dev_priv = dev->dev_private;
1151 drm_i915_setparam_t *param = data;
1154 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1158 switch (param->param) {
1159 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1160 dev_priv->use_mi_batchbuffer_start = param->value;
1162 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1163 dev_priv->tex_lru_log_granularity = param->value;
1165 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1166 dev_priv->allow_batchbuffer = param->value;
1169 DRM_ERROR("unknown parameter %d\n", param->param);
1176 drm_i915_mmio_entry_t mmio_table[] = {
1177 [MMIO_REGS_PS_DEPTH_COUNT] = {
1178 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
1184 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
1186 static int i915_mmio(struct drm_device *dev, void *data,
1187 struct drm_file *file_priv)
1190 drm_i915_private_t *dev_priv = dev->dev_private;
1191 drm_i915_mmio_entry_t *e;
1192 drm_i915_mmio_t *mmio = data;
1197 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1201 if (mmio->reg >= mmio_table_size)
1204 e = &mmio_table[mmio->reg];
1205 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
1207 switch (mmio->read_write) {
1208 case I915_MMIO_READ:
1209 if (!(e->flag & I915_MMIO_MAY_READ))
1211 for (i = 0; i < e->size / 4; i++)
1212 buf[i] = I915_READ(e->offset + i * 4);
1213 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
1214 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1219 case I915_MMIO_WRITE:
1220 if (!(e->flag & I915_MMIO_MAY_WRITE))
1222 if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
1223 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1226 for (i = 0; i < e->size / 4; i++)
1227 I915_WRITE(e->offset + i * 4, buf[i]);
1233 static int i915_set_status_page(struct drm_device *dev, void *data,
1234 struct drm_file *file_priv)
1236 drm_i915_private_t *dev_priv = dev->dev_private;
1237 drm_i915_hws_addr_t *hws = data;
1240 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1243 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1245 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1247 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1248 dev_priv->hws_map.size = 4*1024;
1249 dev_priv->hws_map.type = 0;
1250 dev_priv->hws_map.flags = 0;
1251 dev_priv->hws_map.mtrr = 0;
1253 drm_core_ioremap(&dev_priv->hws_map, dev);
1254 if (dev_priv->hws_map.handle == NULL) {
1255 dev->dev_private = (void *)dev_priv;
1256 i915_dma_cleanup(dev);
1257 dev_priv->status_gfx_addr = 0;
1258 DRM_ERROR("can not ioremap virtual address for"
1259 " G33 hw status page\n");
1262 dev_priv->hw_status_page = dev_priv->hws_map.handle;
1264 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1265 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
1266 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1267 dev_priv->status_gfx_addr);
1268 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1272 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1274 /* i915 has 4 more counters */
1276 dev->types[6] = _DRM_STAT_IRQ;
1277 dev->types[7] = _DRM_STAT_PRIMARY;
1278 dev->types[8] = _DRM_STAT_SECONDARY;
1279 dev->types[9] = _DRM_STAT_DMA;
1284 void i915_driver_lastclose(struct drm_device * dev)
1286 if (dev->dev_private) {
1287 drm_i915_private_t *dev_priv = dev->dev_private;
1288 i915_do_cleanup_pageflip(dev);
1289 i915_mem_takedown(&(dev_priv->agp_heap));
1291 i915_dma_cleanup(dev);
1294 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1296 if (dev->dev_private) {
1297 drm_i915_private_t *dev_priv = dev->dev_private;
1298 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1302 struct drm_ioctl_desc i915_ioctls[] = {
1303 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1304 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1305 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1306 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1307 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1308 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1309 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1310 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1311 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1312 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1313 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1314 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1315 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1316 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1317 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1318 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1319 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1320 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1321 #ifdef I915_HAVE_BUFFER
1322 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1326 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1329 * Determine if the device really is AGP or not.
1331 * All Intel graphics chipsets are treated as AGP, even if they are really
1334 * \param dev The device to be tested.
1337 * A value of 1 is always retured to indictate every i9x5 is AGP.
1339 int i915_driver_device_is_agp(struct drm_device * dev)
1344 int i915_driver_firstopen(struct drm_device *dev)
1346 #ifdef I915_HAVE_BUFFER
1347 drm_bo_driver_init(dev);