shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2)
  38
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 10000; i++) {
  53                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  54                 ring->space = ring->head - (ring->tail + 8);
  55                 if (ring->space < 0)
  56                         ring->space += ring->Size;
  57                 if (ring->space >= n)
  58                         return 0;
  59
  60                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61
  62                 if (ring->head != last_head)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 DRM_UDELAY(1);
  67         }
  68
  69         return DRM_ERR(EBUSY);
  70 }
  71
  72 void i915_kernel_lost_context(drm_device_t * dev)
  73 {
  74         drm_i915_private_t *dev_priv = dev->dev_private;
  75         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  76
  77         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  78         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  79         ring->space = ring->head - (ring->tail + 8);
  80         if (ring->space < 0)
  81                 ring->space += ring->Size;
  82
  83         if (ring->head == ring->tail)
  84                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  85 }
  86
  87 static int i915_dma_cleanup(drm_device_t * dev)
  88 {
  89         /* Make sure interrupts are disabled here because the uninstall ioctl
  90          * may not have been called from userspace and after dev_private
  91          * is freed, it's too late.
  92          */
  93         if (dev->irq)
  94                 drm_irq_uninstall(dev);
  95
  96         if (dev->dev_private) {
  97                 drm_i915_private_t *dev_priv =
  98                     (drm_i915_private_t *) dev->dev_private;
  99
 100                 if (dev_priv->ring.virtual_start) {
 101                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 102                 }
 103
 104                 if (dev_priv->status_page_dmah) {
 105                         drm_pci_free(dev, dev_priv->status_page_dmah);
 106                         /* Need to rewrite hardware status page */
 107                         I915_WRITE(0x02080, 0x1ffff000);
 108                 }
 109
 110                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 111                          DRM_MEM_DRIVER);
 112
 113                 dev->dev_private = NULL;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static int i915_initialize(drm_device_t * dev,
 120                            drm_i915_private_t * dev_priv,
 121                            drm_i915_init_t * init)
 122 {
 123         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 124
 125         DRM_GETSAREA();
 126         if (!dev_priv->sarea) {
 127                 DRM_ERROR("can not find sarea!\n");
 128                 dev->dev_private = (void *)dev_priv;
 129                 i915_dma_cleanup(dev);
 130                 return DRM_ERR(EINVAL);
 131         }
 132
 133         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 134         if (!dev_priv->mmio_map) {
 135                 dev->dev_private = (void *)dev_priv;
 136                 i915_dma_cleanup(dev);
 137                 DRM_ERROR("can not find mmio map!\n");
 138                 return DRM_ERR(EINVAL);
 139         }
 140
 141         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 142             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 143
 144         dev_priv->ring.Start = init->ring_start;
 145         dev_priv->ring.End = init->ring_end;
 146         dev_priv->ring.Size = init->ring_size;
 147         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 148
 149         dev_priv->ring.map.offset = init->ring_start;
 150         dev_priv->ring.map.size = init->ring_size;
 151         dev_priv->ring.map.type = 0;
 152         dev_priv->ring.map.flags = 0;
 153         dev_priv->ring.map.mtrr = 0;
 154
 155         drm_core_ioremap(&dev_priv->ring.map, dev);
 156
 157         if (dev_priv->ring.map.handle == NULL) {
 158                 dev->dev_private = (void *)dev_priv;
 159                 i915_dma_cleanup(dev);
 160                 DRM_ERROR("can not ioremap virtual address for"
 161                           " ring buffer\n");
 162                 return DRM_ERR(ENOMEM);
 163         }
 164
 165         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 166
 167         dev_priv->cpp = init->cpp;
 168         dev_priv->sarea_priv->pf_current_page = 0;
 169
 170         /* We are using separate values as placeholders for mechanisms for
 171          * private backbuffer/depthbuffer usage.
 172          */
 173         dev_priv->use_mi_batchbuffer_start = 0;
 174
 175         /* Allow hardware batchbuffers unless told otherwise.
 176          */
 177         dev_priv->allow_batchbuffer = 1;
 178
 179         /* Program Hardware Status Page */
 180         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 181             0xffffffff);
 182
 183         if (!dev_priv->status_page_dmah) {
 184                 dev->dev_private = (void *)dev_priv;
 185                 i915_dma_cleanup(dev);
 186                 DRM_ERROR("Can not allocate hardware status page\n");
 187                 return DRM_ERR(ENOMEM);
 188         }
 189         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 190         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 191
 192         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 193         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 194
 195         I915_WRITE(0x02080, dev_priv->dma_status_page);
 196         DRM_DEBUG("Enabled hardware status page\n");
 197         dev->dev_private = (void *)dev_priv;
 198 #ifdef I915_HAVE_BUFFER
 199         drm_bo_driver_init(dev);
 200 #endif
 201         return 0;
 202 }
 203
 204 static int i915_dma_resume(drm_device_t * dev)
 205 {
 206         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 207
 208         DRM_DEBUG("%s\n", __FUNCTION__);
 209
 210         if (!dev_priv->sarea) {
 211                 DRM_ERROR("can not find sarea!\n");
 212                 return DRM_ERR(EINVAL);
 213         }
 214
 215         if (!dev_priv->mmio_map) {
 216                 DRM_ERROR("can not find mmio map!\n");
 217                 return DRM_ERR(EINVAL);
 218         }
 219
 220         if (dev_priv->ring.map.handle == NULL) {
 221                 DRM_ERROR("can not ioremap virtual address for"
 222                           " ring buffer\n");
 223                 return DRM_ERR(ENOMEM);
 224         }
 225
 226         /* Program Hardware Status Page */
 227         if (!dev_priv->hw_status_page) {
 228                 DRM_ERROR("Can not find hardware status page\n");
 229                 return DRM_ERR(EINVAL);
 230         }
 231         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 232
 233         I915_WRITE(0x02080, dev_priv->dma_status_page);
 234         DRM_DEBUG("Enabled hardware status page\n");
 235
 236         return 0;
 237 }
 238
 239 static int i915_dma_init(DRM_IOCTL_ARGS)
 240 {
 241         DRM_DEVICE;
 242         drm_i915_private_t *dev_priv;
 243         drm_i915_init_t init;
 244         int retcode = 0;
 245
 246         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 247                                  sizeof(init));
 248
 249         switch (init.func) {
 250         case I915_INIT_DMA:
 251                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 252                                      DRM_MEM_DRIVER);
 253                 if (dev_priv == NULL)
 254                         return DRM_ERR(ENOMEM);
 255                 retcode = i915_initialize(dev, dev_priv, &init);
 256                 break;
 257         case I915_CLEANUP_DMA:
 258                 retcode = i915_dma_cleanup(dev);
 259                 break;
 260         case I915_RESUME_DMA:
 261                 retcode = i915_dma_resume(dev);
 262                 break;
 263         default:
 264                 retcode = DRM_ERR(EINVAL);
 265                 break;
 266         }
 267
 268         return retcode;
 269 }
 270
 271 /* Implement basically the same security restrictions as hardware does
 272  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 273  *
 274  * Most of the calculations below involve calculating the size of a
 275  * particular instruction.  It's important to get the size right as
 276  * that tells us where the next instruction to check is.  Any illegal
 277  * instruction detected will be given a size of zero, which is a
 278  * signal to abort the rest of the buffer.
 279  */
 280 static int do_validate_cmd(int cmd)
 281 {
 282         switch (((cmd >> 29) & 0x7)) {
 283         case 0x0:
 284                 switch ((cmd >> 23) & 0x3f) {
 285                 case 0x0:
 286                         return 1;       /* MI_NOOP */
 287                 case 0x4:
 288                         return 1;       /* MI_FLUSH */
 289                 default:
 290                         return 0;       /* disallow everything else */
 291                 }
 292                 break;
 293         case 0x1:
 294                 return 0;       /* reserved */
 295         case 0x2:
 296                 return (cmd & 0xff) + 2;        /* 2d commands */
 297         case 0x3:
 298                 if (((cmd >> 24) & 0x1f) <= 0x18)
 299                         return 1;
 300
 301                 switch ((cmd >> 24) & 0x1f) {
 302                 case 0x1c:
 303                         return 1;
 304                 case 0x1d:
 305                         switch ((cmd >> 16) & 0xff) {
 306                         case 0x3:
 307                                 return (cmd & 0x1f) + 2;
 308                         case 0x4:
 309                                 return (cmd & 0xf) + 2;
 310                         default:
 311                                 return (cmd & 0xffff) + 2;
 312                         }
 313                 case 0x1e:
 314                         if (cmd & (1 << 23))
 315                                 return (cmd & 0xffff) + 1;
 316                         else
 317                                 return 1;
 318                 case 0x1f:
 319                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 320                                 return (cmd & 0x1ffff) + 2;
 321                         else if (cmd & (1 << 17))       /* indirect random */
 322                                 if ((cmd & 0xffff) == 0)
 323                                         return 0;       /* unknown length, too hard */
 324                                 else
 325                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 326                         else
 327                                 return 2;       /* indirect sequential */
 328                 default:
 329                         return 0;
 330                 }
 331         default:
 332                 return 0;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int validate_cmd(int cmd)
 339 {
 340         int ret = do_validate_cmd(cmd);
 341
 342 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 343
 344         return ret;
 345 }
 346
 347 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 348 {
 349         drm_i915_private_t *dev_priv = dev->dev_private;
 350         int i;
 351         RING_LOCALS;
 352
 353         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 354                 return DRM_ERR(EINVAL);
 355
 356         BEGIN_LP_RING((dwords+1)&~1);
 357
 358         for (i = 0; i < dwords;) {
 359                 int cmd, sz;
 360
 361                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 362                         return DRM_ERR(EINVAL);
 363
 364                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 365                         return DRM_ERR(EINVAL);
 366
 367                 OUT_RING(cmd);
 368
 369                 while (++i, --sz) {
 370                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 371                                                          sizeof(cmd))) {
 372                                 return DRM_ERR(EINVAL);
 373                         }
 374                         OUT_RING(cmd);
 375                 }
 376         }
 377
 378         if (dwords & 1)
 379                 OUT_RING(0);
 380
 381         ADVANCE_LP_RING();
 382
 383         return 0;
 384 }
 385
 386 static int i915_emit_box(drm_device_t * dev,
 387                          drm_clip_rect_t __user * boxes,
 388                          int i, int DR1, int DR4)
 389 {
 390         drm_i915_private_t *dev_priv = dev->dev_private;
 391         drm_clip_rect_t box;
 392         RING_LOCALS;
 393
 394         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 395                 return DRM_ERR(EFAULT);
 396         }
 397
 398         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 399                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 400                           box.x1, box.y1, box.x2, box.y2);
 401                 return DRM_ERR(EINVAL);
 402         }
 403
 404         if (IS_I965G(dev)) {
 405                 BEGIN_LP_RING(4);
 406                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 407                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 408                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 409                 OUT_RING(DR4);
 410                 ADVANCE_LP_RING();
 411         } else {
 412                 BEGIN_LP_RING(6);
 413                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 414                 OUT_RING(DR1);
 415                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 416                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 417                 OUT_RING(DR4);
 418                 OUT_RING(0);
 419                 ADVANCE_LP_RING();
 420         }
 421
 422         return 0;
 423 }
 424
 425 /* XXX: Emitting the counter should really be moved to part of the IRQ
 426  * emit.  For now, do it in both places:
 427  */
 428
 429 void i915_emit_breadcrumb(drm_device_t *dev)
 430 {
 431         drm_i915_private_t *dev_priv = dev->dev_private;
 432         RING_LOCALS;
 433
 434         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 435
 436         if (dev_priv->counter > 0x7FFFFFFFUL)
 437                  dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 438
 439         BEGIN_LP_RING(4);
 440         OUT_RING(CMD_STORE_DWORD_IDX);
 441         OUT_RING(20);
 442         OUT_RING(dev_priv->counter);
 443         OUT_RING(0);
 444         ADVANCE_LP_RING();
 445 }
 446
 447
 448 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 449 {
 450         drm_i915_private_t *dev_priv = dev->dev_private;
 451         uint32_t flush_cmd = CMD_MI_FLUSH;
 452         RING_LOCALS;
 453
 454         flush_cmd |= flush;
 455
 456         i915_kernel_lost_context(dev);
 457
 458         BEGIN_LP_RING(4);
 459         OUT_RING(flush_cmd);
 460         OUT_RING(0);
 461         OUT_RING(0);
 462         OUT_RING(0);
 463         ADVANCE_LP_RING();
 464
 465         return 0;
 466 }
 467
 468
 469 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 470                                    drm_i915_cmdbuffer_t * cmd)
 471 {
 472         drm_i915_private_t *dev_priv = dev->dev_private;
 473         int nbox = cmd->num_cliprects;
 474         int i = 0, count, ret;
 475
 476         if (cmd->sz & 0x3) {
 477                 DRM_ERROR("alignment");
 478                 return DRM_ERR(EINVAL);
 479         }
 480
 481         i915_kernel_lost_context(dev);
 482
 483         count = nbox ? nbox : 1;
 484
 485         for (i = 0; i < count; i++) {
 486                 if (i < nbox) {
 487                         ret = i915_emit_box(dev, cmd->cliprects, i,
 488                                             cmd->DR1, cmd->DR4);
 489                         if (ret)
 490                                 return ret;
 491                 }
 492
 493                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 494                 if (ret)
 495                         return ret;
 496         }
 497
 498         i915_emit_breadcrumb( dev );
 499 #ifdef I915_HAVE_FENCE
 500         drm_fence_flush_old(dev, 0, dev_priv->counter);
 501 #endif
 502         return 0;
 503 }
 504
 505 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 506                                      drm_i915_batchbuffer_t * batch)
 507 {
 508         drm_i915_private_t *dev_priv = dev->dev_private;
 509         drm_clip_rect_t __user *boxes = batch->cliprects;
 510         int nbox = batch->num_cliprects;
 511         int i = 0, count;
 512         RING_LOCALS;
 513
 514         if ((batch->start | batch->used) & 0x7) {
 515                 DRM_ERROR("alignment");
 516                 return DRM_ERR(EINVAL);
 517         }
 518
 519         i915_kernel_lost_context(dev);
 520
 521         count = nbox ? nbox : 1;
 522
 523         for (i = 0; i < count; i++) {
 524                 if (i < nbox) {
 525                         int ret = i915_emit_box(dev, boxes, i,
 526                                                 batch->DR1, batch->DR4);
 527                         if (ret)
 528                                 return ret;
 529                 }
 530
 531                 if (dev_priv->use_mi_batchbuffer_start) {
 532                         BEGIN_LP_RING(2);
 533                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 534                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 535                         ADVANCE_LP_RING();
 536                 } else {
 537                         BEGIN_LP_RING(4);
 538                         OUT_RING(MI_BATCH_BUFFER);
 539                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 540                         OUT_RING(batch->start + batch->used - 4);
 541                         OUT_RING(0);
 542                         ADVANCE_LP_RING();
 543                 }
 544         }
 545
 546         i915_emit_breadcrumb( dev );
 547 #ifdef I915_HAVE_FENCE
 548         drm_fence_flush_old(dev, 0, dev_priv->counter);
 549 #endif
 550         return 0;
 551 }
 552
 553 static void i915_do_dispatch_flip(drm_device_t * dev, int pipe, int sync)
 554 {
 555         drm_i915_private_t *dev_priv = dev->dev_private;
 556         u32 num_pages, current_page, next_page, dspbase;
 557         int shift = 2 * pipe, x, y;
 558         RING_LOCALS;
 559
 560         /* Calculate display base offset */
 561         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 562         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 563         next_page = (current_page + 1) % num_pages;
 564
 565         switch (next_page) {
 566         default:
 567         case 0:
 568                 dspbase = dev_priv->sarea_priv->front_offset;
 569                 break;
 570         case 1:
 571                 dspbase = dev_priv->sarea_priv->back_offset;
 572                 break;
 573         case 2:
 574                 dspbase = dev_priv->sarea_priv->third_offset;
 575                 break;
 576         }
 577
 578         if (pipe == 0) {
 579                 x = dev_priv->sarea_priv->pipeA_x;
 580                 y = dev_priv->sarea_priv->pipeA_y;
 581         } else {
 582                 x = dev_priv->sarea_priv->pipeB_x;
 583                 y = dev_priv->sarea_priv->pipeB_y;
 584         }
 585
 586         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 587
 588         DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page,
 589                   dspbase);
 590
 591         BEGIN_LP_RING(4);
 592         OUT_RING(sync ? 0 :
 593                  (MI_WAIT_FOR_EVENT | (pipe ? MI_WAIT_FOR_PLANE_B_FLIP :
 594                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 595         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 596                  (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 597         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 598         OUT_RING(dspbase);
 599         ADVANCE_LP_RING();
 600
 601         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 602         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 603 }
 604
 605 void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync)
 606 {
 607         drm_i915_private_t *dev_priv = dev->dev_private;
 608         int i;
 609
 610         DRM_DEBUG("%s: pipes=0x%x pfCurrentPage=%d\n",
 611                   __FUNCTION__,
 612                   pipes, dev_priv->sarea_priv->pf_current_page);
 613
 614         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 615
 616         for (i = 0; i < 2; i++)
 617                 if (pipes & (1 << i))
 618                         i915_do_dispatch_flip(dev, i, sync);
 619
 620         i915_emit_breadcrumb(dev);
 621 #ifdef I915_HAVE_FENCE
 622         if (!sync)
 623                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 624 #endif
 625 }
 626
 627 static int i915_quiescent(drm_device_t * dev)
 628 {
 629         drm_i915_private_t *dev_priv = dev->dev_private;
 630
 631         i915_kernel_lost_context(dev);
 632         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 633 }
 634
 635 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 636 {
 637         DRM_DEVICE;
 638
 639         LOCK_TEST_WITH_RETURN(dev, filp);
 640
 641         return i915_quiescent(dev);
 642 }
 643
 644 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 645 {
 646         DRM_DEVICE;
 647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 648         u32 *hw_status = dev_priv->hw_status_page;
 649         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 650             dev_priv->sarea_priv;
 651         drm_i915_batchbuffer_t batch;
 652         int ret;
 653
 654         if (!dev_priv->allow_batchbuffer) {
 655                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 656                 return DRM_ERR(EINVAL);
 657         }
 658
 659         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 660                                  sizeof(batch));
 661
 662         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 663                   batch.start, batch.used, batch.num_cliprects);
 664
 665         LOCK_TEST_WITH_RETURN(dev, filp);
 666
 667         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 668                                                        batch.num_cliprects *
 669                                                        sizeof(drm_clip_rect_t)))
 670                 return DRM_ERR(EFAULT);
 671
 672         ret = i915_dispatch_batchbuffer(dev, &batch);
 673
 674         sarea_priv->last_dispatch = (int)hw_status[5];
 675         return ret;
 676 }
 677
 678 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 679 {
 680         DRM_DEVICE;
 681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 682         u32 *hw_status = dev_priv->hw_status_page;
 683         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 684             dev_priv->sarea_priv;
 685         drm_i915_cmdbuffer_t cmdbuf;
 686         int ret;
 687
 688         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 689                                  sizeof(cmdbuf));
 690
 691         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 692                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 693
 694         LOCK_TEST_WITH_RETURN(dev, filp);
 695
 696         if (cmdbuf.num_cliprects &&
 697             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 698                                 cmdbuf.num_cliprects *
 699                                 sizeof(drm_clip_rect_t))) {
 700                 DRM_ERROR("Fault accessing cliprects\n");
 701                 return DRM_ERR(EFAULT);
 702         }
 703
 704         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 705         if (ret) {
 706                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 707                 return ret;
 708         }
 709
 710         sarea_priv->last_dispatch = (int)hw_status[5];
 711         return 0;
 712 }
 713
 714 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 715 {
 716         drm_i915_private_t *dev_priv = dev->dev_private;
 717         int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 718
 719         DRM_DEBUG("%s\n", __FUNCTION__);
 720
 721         for (i = 0, pipes = 0; i < 2; i++)
 722                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 723                         dev_priv->sarea_priv->pf_current_page =
 724                                 (dev_priv->sarea_priv->pf_current_page &
 725                                  ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
 726
 727                         pipes |= 1 << i;
 728                 }
 729
 730         if (pipes)
 731                 i915_dispatch_flip(dev, pipes, 0);
 732
 733         return 0;
 734 }
 735
 736 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 737 {
 738         DRM_DEVICE;
 739         drm_i915_flip_t param;
 740
 741         DRM_DEBUG("%s\n", __FUNCTION__);
 742
 743         LOCK_TEST_WITH_RETURN(dev, filp);
 744
 745         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data,
 746                                  sizeof(param));
 747
 748         if (param.pipes & ~0x3) {
 749                 DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n",
 750                           param.pipes);
 751                 return DRM_ERR(EINVAL);
 752         }
 753
 754         i915_dispatch_flip(dev, param.pipes, 0);
 755
 756         return 0;
 757 }
 758
 759
 760 static int i915_getparam(DRM_IOCTL_ARGS)
 761 {
 762         DRM_DEVICE;
 763         drm_i915_private_t *dev_priv = dev->dev_private;
 764         drm_i915_getparam_t param;
 765         int value;
 766
 767         if (!dev_priv) {
 768                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 769                 return DRM_ERR(EINVAL);
 770         }
 771
 772         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 773                                  sizeof(param));
 774
 775         switch (param.param) {
 776         case I915_PARAM_IRQ_ACTIVE:
 777                 value = dev->irq ? 1 : 0;
 778                 break;
 779         case I915_PARAM_ALLOW_BATCHBUFFER:
 780                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 781                 break;
 782         case I915_PARAM_LAST_DISPATCH:
 783                 value = READ_BREADCRUMB(dev_priv);
 784                 break;
 785         default:
 786                 DRM_ERROR("Unknown parameter %d\n", param.param);
 787                 return DRM_ERR(EINVAL);
 788         }
 789
 790         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 791                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 792                 return DRM_ERR(EFAULT);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int i915_setparam(DRM_IOCTL_ARGS)
 799 {
 800         DRM_DEVICE;
 801         drm_i915_private_t *dev_priv = dev->dev_private;
 802         drm_i915_setparam_t param;
 803
 804         if (!dev_priv) {
 805                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 806                 return DRM_ERR(EINVAL);
 807         }
 808
 809         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 810                                  sizeof(param));
 811
 812         switch (param.param) {
 813         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 814                 dev_priv->use_mi_batchbuffer_start = param.value;
 815                 break;
 816         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 817                 dev_priv->tex_lru_log_granularity = param.value;
 818                 break;
 819         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 820                 dev_priv->allow_batchbuffer = param.value;
 821                 break;
 822         default:
 823                 DRM_ERROR("unknown parameter %d\n", param.param);
 824                 return DRM_ERR(EINVAL);
 825         }
 826
 827         return 0;
 828 }
 829
 830 drm_i915_mmio_entry_t mmio_table[] = {
 831         [MMIO_REGS_PS_DEPTH_COUNT] = {
 832                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 833                 0x2350,
 834                 8
 835         }
 836 };
 837
 838 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 839
 840 static int i915_mmio(DRM_IOCTL_ARGS)
 841 {
 842         char buf[32];
 843         DRM_DEVICE;
 844         drm_i915_private_t *dev_priv = dev->dev_private;
 845         drm_i915_mmio_entry_t *e;
 846         drm_i915_mmio_t mmio;
 847         void __iomem *base;
 848         if (!dev_priv) {
 849                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 850                 return DRM_ERR(EINVAL);
 851         }
 852         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
 853                                  sizeof(mmio));
 854
 855         if (mmio.reg >= mmio_table_size)
 856                 return DRM_ERR(EINVAL);
 857
 858         e = &mmio_table[mmio.reg];
 859         base = dev_priv->mmio_map->handle + e->offset;
 860
 861         switch (mmio.read_write) {
 862                 case I915_MMIO_READ:
 863                         if (!(e->flag & I915_MMIO_MAY_READ))
 864                                 return DRM_ERR(EINVAL);
 865                         memcpy_fromio(buf, base, e->size);
 866                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 867                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 868                                 return DRM_ERR(EFAULT);
 869                         }
 870                         break;
 871
 872                 case I915_MMIO_WRITE:
 873                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 874                                 return DRM_ERR(EINVAL);
 875                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 876                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 877                                 return DRM_ERR(EFAULT);
 878                         }
 879                         memcpy_toio(base, buf, e->size);
 880                         break;
 881         }
 882         return 0;
 883 }
 884
 885 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 886 {
 887         /* i915 has 4 more counters */
 888         dev->counters += 4;
 889         dev->types[6] = _DRM_STAT_IRQ;
 890         dev->types[7] = _DRM_STAT_PRIMARY;
 891         dev->types[8] = _DRM_STAT_SECONDARY;
 892         dev->types[9] = _DRM_STAT_DMA;
 893
 894         return 0;
 895 }
 896
 897 void i915_driver_lastclose(drm_device_t * dev)
 898 {
 899         if (dev->dev_private) {
 900                 drm_i915_private_t *dev_priv = dev->dev_private;
 901                 i915_do_cleanup_pageflip(dev);
 902                 i915_mem_takedown(&(dev_priv->agp_heap));
 903         }
 904         i915_dma_cleanup(dev);
 905 }
 906
 907 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 908 {
 909         if (dev->dev_private) {
 910                 drm_i915_private_t *dev_priv = dev->dev_private;
 911                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 912         }
 913 }
 914
 915 drm_ioctl_desc_t i915_ioctls[] = {
 916         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 917         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 918         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 919         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 920         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 921         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 922         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 923         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 924         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 925         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 926         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 927         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 928         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 929         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 930         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 931         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 932         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 933 };
 934
 935 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 936
 937 /**
 938  * Determine if the device really is AGP or not.
 939  *
 940  * All Intel graphics chipsets are treated as AGP, even if they are really
 941  * PCI-e.
 942  *
 943  * \param dev   The device to be tested.
 944  *
 945  * \returns
 946  * A value of 1 is always retured to indictate every i9x5 is AGP.
 947  */
 948 int i915_driver_device_is_agp(drm_device_t * dev)
 949 {
 950         return 1;
 951 }