1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2 || \
38 dev->pci_device == 0x2A02 || \
39 dev->pci_device == 0x2A12)
41 #define IS_G33(dev) (dev->pci_device == 0x29C2 || \
42 dev->pci_device == 0x29B2 || \
43 dev->pci_device == 0x29D2)
45 /* Really want an OS-independent resettable timer. Would like to have
46 * this loop run for (eg) 3 sec, but have the timer reset every time
47 * the head pointer changes, so that EBUSY only happens if the ring
48 * actually stalls for (eg) 3 seconds.
50 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
54 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
57 for (i = 0; i < 10000; i++) {
58 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
59 ring->space = ring->head - (ring->tail + 8);
61 ring->space += ring->Size;
65 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
67 if (ring->head != last_head)
70 last_head = ring->head;
77 void i915_kernel_lost_context(struct drm_device * dev)
79 drm_i915_private_t *dev_priv = dev->dev_private;
80 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
82 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
83 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
84 ring->space = ring->head - (ring->tail + 8);
86 ring->space += ring->Size;
88 if (ring->head == ring->tail)
89 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
92 static int i915_dma_cleanup(struct drm_device * dev)
94 /* Make sure interrupts are disabled here because the uninstall ioctl
95 * may not have been called from userspace and after dev_private
96 * is freed, it's too late.
99 drm_irq_uninstall(dev);
101 if (dev->dev_private) {
102 drm_i915_private_t *dev_priv =
103 (drm_i915_private_t *) dev->dev_private;
105 if (dev_priv->ring.virtual_start) {
106 drm_core_ioremapfree(&dev_priv->ring.map, dev);
109 if (dev_priv->status_page_dmah) {
110 drm_pci_free(dev, dev_priv->status_page_dmah);
111 /* Need to rewrite hardware status page */
112 I915_WRITE(0x02080, 0x1ffff000);
114 if (dev_priv->status_gfx_addr) {
115 dev_priv->status_gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
117 I915_WRITE(0x02080, 0x1ffff000);
119 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
122 dev->dev_private = NULL;
128 static int i915_initialize(struct drm_device * dev,
129 drm_i915_private_t * dev_priv,
130 drm_i915_init_t * init)
132 memset(dev_priv, 0, sizeof(drm_i915_private_t));
134 dev_priv->sarea = drm_getsarea(dev);
135 if (!dev_priv->sarea) {
136 DRM_ERROR("can not find sarea!\n");
137 dev->dev_private = (void *)dev_priv;
138 i915_dma_cleanup(dev);
142 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
143 if (!dev_priv->mmio_map) {
144 dev->dev_private = (void *)dev_priv;
145 i915_dma_cleanup(dev);
146 DRM_ERROR("can not find mmio map!\n");
150 dev_priv->sarea_priv = (drm_i915_sarea_t *)
151 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
153 dev_priv->ring.Start = init->ring_start;
154 dev_priv->ring.End = init->ring_end;
155 dev_priv->ring.Size = init->ring_size;
156 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
158 dev_priv->ring.map.offset = init->ring_start;
159 dev_priv->ring.map.size = init->ring_size;
160 dev_priv->ring.map.type = 0;
161 dev_priv->ring.map.flags = 0;
162 dev_priv->ring.map.mtrr = 0;
164 drm_core_ioremap(&dev_priv->ring.map, dev);
166 if (dev_priv->ring.map.handle == NULL) {
167 dev->dev_private = (void *)dev_priv;
168 i915_dma_cleanup(dev);
169 DRM_ERROR("can not ioremap virtual address for"
174 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
176 dev_priv->cpp = init->cpp;
177 dev_priv->sarea_priv->pf_current_page = 0;
179 /* We are using separate values as placeholders for mechanisms for
180 * private backbuffer/depthbuffer usage.
182 dev_priv->use_mi_batchbuffer_start = 0;
184 /* Allow hardware batchbuffers unless told otherwise.
186 dev_priv->allow_batchbuffer = 1;
188 /* Enable vblank on pipe A for older X servers
190 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
192 /* Program Hardware Status Page */
194 dev_priv->status_page_dmah =
195 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
197 if (!dev_priv->status_page_dmah) {
198 dev->dev_private = (void *)dev_priv;
199 i915_dma_cleanup(dev);
200 DRM_ERROR("Can not allocate hardware status page\n");
203 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
204 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
206 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
208 I915_WRITE(0x02080, dev_priv->dma_status_page);
210 DRM_DEBUG("Enabled hardware status page\n");
211 dev->dev_private = (void *)dev_priv;
215 static int i915_dma_resume(struct drm_device * dev)
217 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
219 DRM_DEBUG("%s\n", __FUNCTION__);
221 if (!dev_priv->sarea) {
222 DRM_ERROR("can not find sarea!\n");
226 if (!dev_priv->mmio_map) {
227 DRM_ERROR("can not find mmio map!\n");
231 if (dev_priv->ring.map.handle == NULL) {
232 DRM_ERROR("can not ioremap virtual address for"
237 /* Program Hardware Status Page */
238 if (!dev_priv->hw_status_page) {
239 DRM_ERROR("Can not find hardware status page\n");
242 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
244 if (dev_priv->status_gfx_addr != 0)
245 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
247 I915_WRITE(0x02080, dev_priv->dma_status_page);
248 DRM_DEBUG("Enabled hardware status page\n");
253 static int i915_dma_init(struct drm_device *dev, void *data,
254 struct drm_file *file_priv)
256 drm_i915_private_t *dev_priv;
257 drm_i915_init_t *init = data;
260 switch (init->func) {
262 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
264 if (dev_priv == NULL)
266 retcode = i915_initialize(dev, dev_priv, init);
268 case I915_CLEANUP_DMA:
269 retcode = i915_dma_cleanup(dev);
271 case I915_RESUME_DMA:
272 retcode = i915_dma_resume(dev);
282 /* Implement basically the same security restrictions as hardware does
283 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
285 * Most of the calculations below involve calculating the size of a
286 * particular instruction. It's important to get the size right as
287 * that tells us where the next instruction to check is. Any illegal
288 * instruction detected will be given a size of zero, which is a
289 * signal to abort the rest of the buffer.
291 static int do_validate_cmd(int cmd)
293 switch (((cmd >> 29) & 0x7)) {
295 switch ((cmd >> 23) & 0x3f) {
297 return 1; /* MI_NOOP */
299 return 1; /* MI_FLUSH */
301 return 0; /* disallow everything else */
305 return 0; /* reserved */
307 return (cmd & 0xff) + 2; /* 2d commands */
309 if (((cmd >> 24) & 0x1f) <= 0x18)
312 switch ((cmd >> 24) & 0x1f) {
316 switch ((cmd >> 16) & 0xff) {
318 return (cmd & 0x1f) + 2;
320 return (cmd & 0xf) + 2;
322 return (cmd & 0xffff) + 2;
326 return (cmd & 0xffff) + 1;
330 if ((cmd & (1 << 23)) == 0) /* inline vertices */
331 return (cmd & 0x1ffff) + 2;
332 else if (cmd & (1 << 17)) /* indirect random */
333 if ((cmd & 0xffff) == 0)
334 return 0; /* unknown length, too hard */
336 return (((cmd & 0xffff) + 1) / 2) + 1;
338 return 2; /* indirect sequential */
349 static int validate_cmd(int cmd)
351 int ret = do_validate_cmd(cmd);
353 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
358 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
361 drm_i915_private_t *dev_priv = dev->dev_private;
365 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
368 BEGIN_LP_RING((dwords+1)&~1);
370 for (i = 0; i < dwords;) {
373 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
376 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
382 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
398 static int i915_emit_box(struct drm_device * dev,
399 struct drm_clip_rect __user * boxes,
400 int i, int DR1, int DR4)
402 drm_i915_private_t *dev_priv = dev->dev_private;
403 struct drm_clip_rect box;
406 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
410 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
411 DRM_ERROR("Bad box %d,%d..%d,%d\n",
412 box.x1, box.y1, box.x2, box.y2);
418 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
419 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
420 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
425 OUT_RING(GFX_OP_DRAWRECT_INFO);
427 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
428 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
437 /* XXX: Emitting the counter should really be moved to part of the IRQ
438 * emit. For now, do it in both places:
441 void i915_emit_breadcrumb(struct drm_device *dev)
443 drm_i915_private_t *dev_priv = dev->dev_private;
446 if (++dev_priv->counter > BREADCRUMB_MASK) {
447 dev_priv->counter = 1;
448 DRM_DEBUG("Breadcrumb counter wrapped around\n");
451 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
454 OUT_RING(CMD_STORE_DWORD_IDX);
456 OUT_RING(dev_priv->counter);
462 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
464 drm_i915_private_t *dev_priv = dev->dev_private;
465 uint32_t flush_cmd = CMD_MI_FLUSH;
470 i915_kernel_lost_context(dev);
483 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
484 drm_i915_cmdbuffer_t * cmd)
486 #ifdef I915_HAVE_FENCE
487 drm_i915_private_t *dev_priv = dev->dev_private;
489 int nbox = cmd->num_cliprects;
490 int i = 0, count, ret;
493 DRM_ERROR("alignment");
497 i915_kernel_lost_context(dev);
499 count = nbox ? nbox : 1;
501 for (i = 0; i < count; i++) {
503 ret = i915_emit_box(dev, cmd->cliprects, i,
509 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
514 i915_emit_breadcrumb( dev );
515 #ifdef I915_HAVE_FENCE
516 drm_fence_flush_old(dev, 0, dev_priv->counter);
521 static int i915_dispatch_batchbuffer(struct drm_device * dev,
522 drm_i915_batchbuffer_t * batch)
524 drm_i915_private_t *dev_priv = dev->dev_private;
525 struct drm_clip_rect __user *boxes = batch->cliprects;
526 int nbox = batch->num_cliprects;
530 if ((batch->start | batch->used) & 0x7) {
531 DRM_ERROR("alignment");
535 i915_kernel_lost_context(dev);
537 count = nbox ? nbox : 1;
539 for (i = 0; i < count; i++) {
541 int ret = i915_emit_box(dev, boxes, i,
542 batch->DR1, batch->DR4);
547 if (dev_priv->use_mi_batchbuffer_start) {
550 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
551 OUT_RING(batch->start);
553 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
554 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
560 OUT_RING(MI_BATCH_BUFFER);
561 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
562 OUT_RING(batch->start + batch->used - 4);
568 i915_emit_breadcrumb( dev );
569 #ifdef I915_HAVE_FENCE
570 drm_fence_flush_old(dev, 0, dev_priv->counter);
575 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
577 drm_i915_private_t *dev_priv = dev->dev_private;
578 u32 num_pages, current_page, next_page, dspbase;
579 int shift = 2 * plane, x, y;
582 /* Calculate display base offset */
583 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
584 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
585 next_page = (current_page + 1) % num_pages;
590 dspbase = dev_priv->sarea_priv->front_offset;
593 dspbase = dev_priv->sarea_priv->back_offset;
596 dspbase = dev_priv->sarea_priv->third_offset;
601 x = dev_priv->sarea_priv->planeA_x;
602 y = dev_priv->sarea_priv->planeA_y;
604 x = dev_priv->sarea_priv->planeB_x;
605 y = dev_priv->sarea_priv->planeB_y;
608 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
610 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
615 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
616 MI_WAIT_FOR_PLANE_A_FLIP)));
617 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
618 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
619 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
623 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
624 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
627 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
629 drm_i915_private_t *dev_priv = dev->dev_private;
632 DRM_DEBUG("%s: planes=0x%x pfCurrentPage=%d\n",
634 planes, dev_priv->sarea_priv->pf_current_page);
636 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
638 for (i = 0; i < 2; i++)
639 if (planes & (1 << i))
640 i915_do_dispatch_flip(dev, i, sync);
642 i915_emit_breadcrumb(dev);
643 #ifdef I915_HAVE_FENCE
645 drm_fence_flush_old(dev, 0, dev_priv->counter);
649 static int i915_quiescent(struct drm_device * dev)
651 drm_i915_private_t *dev_priv = dev->dev_private;
653 i915_kernel_lost_context(dev);
654 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
657 static int i915_flush_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *file_priv)
661 LOCK_TEST_WITH_RETURN(dev, file_priv);
663 return i915_quiescent(dev);
666 static int i915_batchbuffer(struct drm_device *dev, void *data,
667 struct drm_file *file_priv)
669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
670 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
671 dev_priv->sarea_priv;
672 drm_i915_batchbuffer_t *batch = data;
675 if (!dev_priv->allow_batchbuffer) {
676 DRM_ERROR("Batchbuffer ioctl disabled\n");
680 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
681 batch->start, batch->used, batch->num_cliprects);
683 LOCK_TEST_WITH_RETURN(dev, file_priv);
685 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
686 batch->num_cliprects *
687 sizeof(struct drm_clip_rect)))
690 ret = i915_dispatch_batchbuffer(dev, batch);
692 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
696 static int i915_cmdbuffer(struct drm_device *dev, void *data,
697 struct drm_file *file_priv)
699 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
700 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
701 dev_priv->sarea_priv;
702 drm_i915_cmdbuffer_t *cmdbuf = data;
705 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
706 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
708 LOCK_TEST_WITH_RETURN(dev, file_priv);
710 if (cmdbuf->num_cliprects &&
711 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
712 cmdbuf->num_cliprects *
713 sizeof(struct drm_clip_rect))) {
714 DRM_ERROR("Fault accessing cliprects\n");
718 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
720 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
724 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
728 static int i915_do_cleanup_pageflip(struct drm_device * dev)
730 drm_i915_private_t *dev_priv = dev->dev_private;
731 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
733 DRM_DEBUG("%s\n", __FUNCTION__);
735 for (i = 0, planes = 0; i < 2; i++)
736 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
737 dev_priv->sarea_priv->pf_current_page =
738 (dev_priv->sarea_priv->pf_current_page &
739 ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
745 i915_dispatch_flip(dev, planes, 0);
750 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
752 drm_i915_flip_t *param = data;
754 DRM_DEBUG("%s\n", __FUNCTION__);
756 LOCK_TEST_WITH_RETURN(dev, file_priv);
758 if (param->planes & ~0x3) {
759 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
764 i915_dispatch_flip(dev, param->planes, 0);
770 static int i915_getparam(struct drm_device *dev, void *data,
771 struct drm_file *file_priv)
773 drm_i915_private_t *dev_priv = dev->dev_private;
774 drm_i915_getparam_t *param = data;
778 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
782 switch (param->param) {
783 case I915_PARAM_IRQ_ACTIVE:
784 value = dev->irq ? 1 : 0;
786 case I915_PARAM_ALLOW_BATCHBUFFER:
787 value = dev_priv->allow_batchbuffer ? 1 : 0;
789 case I915_PARAM_LAST_DISPATCH:
790 value = READ_BREADCRUMB(dev_priv);
793 DRM_ERROR("Unknown parameter %d\n", param->param);
797 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
798 DRM_ERROR("DRM_COPY_TO_USER failed\n");
805 static int i915_setparam(struct drm_device *dev, void *data,
806 struct drm_file *file_priv)
808 drm_i915_private_t *dev_priv = dev->dev_private;
809 drm_i915_setparam_t *param = data;
812 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
816 switch (param->param) {
817 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
818 dev_priv->use_mi_batchbuffer_start = param->value;
820 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
821 dev_priv->tex_lru_log_granularity = param->value;
823 case I915_SETPARAM_ALLOW_BATCHBUFFER:
824 dev_priv->allow_batchbuffer = param->value;
827 DRM_ERROR("unknown parameter %d\n", param->param);
834 drm_i915_mmio_entry_t mmio_table[] = {
835 [MMIO_REGS_PS_DEPTH_COUNT] = {
836 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
842 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
844 static int i915_mmio(struct drm_device *dev, void *data,
845 struct drm_file *file_priv)
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 drm_i915_mmio_entry_t *e;
850 drm_i915_mmio_t *mmio = data;
855 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
859 if (mmio->reg >= mmio_table_size)
862 e = &mmio_table[mmio->reg];
863 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
865 switch (mmio->read_write) {
867 if (!(e->flag & I915_MMIO_MAY_READ))
869 for (i = 0; i < e->size / 4; i++)
870 buf[i] = I915_READ(e->offset + i * 4);
871 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
872 DRM_ERROR("DRM_COPY_TO_USER failed\n");
877 case I915_MMIO_WRITE:
878 if (!(e->flag & I915_MMIO_MAY_WRITE))
880 if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
881 DRM_ERROR("DRM_COPY_TO_USER failed\n");
884 for (i = 0; i < e->size / 4; i++)
885 I915_WRITE(e->offset + i * 4, buf[i]);
891 static int i915_set_status_page(struct drm_device *dev, void *data,
892 struct drm_file *file_priv)
894 drm_i915_private_t *dev_priv = dev->dev_private;
895 drm_i915_hws_addr_t *hws = data;
898 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
901 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
903 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
905 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
906 dev_priv->hws_map.size = 4*1024;
907 dev_priv->hws_map.type = 0;
908 dev_priv->hws_map.flags = 0;
909 dev_priv->hws_map.mtrr = 0;
911 drm_core_ioremap(&dev_priv->hws_map, dev);
912 if (dev_priv->hws_map.handle == NULL) {
913 dev->dev_private = (void *)dev_priv;
914 i915_dma_cleanup(dev);
915 dev_priv->status_gfx_addr = 0;
916 DRM_ERROR("can not ioremap virtual address for"
917 " G33 hw status page\n");
920 dev_priv->hw_status_page = dev_priv->hws_map.handle;
922 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
923 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
924 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
925 dev_priv->status_gfx_addr);
926 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
930 int i915_driver_load(struct drm_device *dev, unsigned long flags)
932 /* i915 has 4 more counters */
934 dev->types[6] = _DRM_STAT_IRQ;
935 dev->types[7] = _DRM_STAT_PRIMARY;
936 dev->types[8] = _DRM_STAT_SECONDARY;
937 dev->types[9] = _DRM_STAT_DMA;
942 void i915_driver_lastclose(struct drm_device * dev)
944 if (dev->dev_private) {
945 drm_i915_private_t *dev_priv = dev->dev_private;
946 i915_do_cleanup_pageflip(dev);
947 i915_mem_takedown(&(dev_priv->agp_heap));
949 i915_dma_cleanup(dev);
952 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
954 if (dev->dev_private) {
955 drm_i915_private_t *dev_priv = dev->dev_private;
956 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
960 struct drm_ioctl_desc i915_ioctls[] = {
961 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
962 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
963 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
964 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
965 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
966 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
967 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
968 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
969 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
970 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
971 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
972 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
973 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
974 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
975 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
976 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
977 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
978 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
981 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
984 * Determine if the device really is AGP or not.
986 * All Intel graphics chipsets are treated as AGP, even if they are really
989 * \param dev The device to be tested.
992 * A value of 1 is always retured to indictate every i9x5 is AGP.
994 int i915_driver_device_is_agp(struct drm_device * dev)
999 int i915_driver_firstopen(struct drm_device *dev)
1001 #ifdef I915_HAVE_BUFFER
1002 drm_bo_driver_init(dev);