shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2)
  38
  39
  40 /* Really want an OS-independent resettable timer.  Would like to have
  41  * this loop run for (eg) 3 sec, but have the timer reset every time
  42  * the head pointer changes, so that EBUSY only happens if the ring
  43  * actually stalls for (eg) 3 seconds.
  44  */
  45 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  46 {
  47         drm_i915_private_t *dev_priv = dev->dev_private;
  48         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  49         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  50         int i;
  51
  52         for (i = 0; i < 10000; i++) {
  53                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  54                 ring->space = ring->head - (ring->tail + 8);
  55                 if (ring->space < 0)
  56                         ring->space += ring->Size;
  57                 if (ring->space >= n)
  58                         return 0;
  59
  60                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  61
  62                 if (ring->head != last_head)
  63                         i = 0;
  64
  65                 last_head = ring->head;
  66                 DRM_UDELAY(1);
  67         }
  68
  69         return DRM_ERR(EBUSY);
  70 }
  71
  72 void i915_kernel_lost_context(drm_device_t * dev)
  73 {
  74         drm_i915_private_t *dev_priv = dev->dev_private;
  75         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  76
  77         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  78         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  79         ring->space = ring->head - (ring->tail + 8);
  80         if (ring->space < 0)
  81                 ring->space += ring->Size;
  82
  83         if (ring->head == ring->tail)
  84                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  85 }
  86
  87 static int i915_dma_cleanup(drm_device_t * dev)
  88 {
  89         /* Make sure interrupts are disabled here because the uninstall ioctl
  90          * may not have been called from userspace and after dev_private
  91          * is freed, it's too late.
  92          */
  93         if (dev->irq)
  94                 drm_irq_uninstall(dev);
  95
  96         if (dev->dev_private) {
  97                 drm_i915_private_t *dev_priv =
  98                     (drm_i915_private_t *) dev->dev_private;
  99
 100                 if (dev_priv->ring.virtual_start) {
 101                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 102                 }
 103
 104                 if (dev_priv->status_page_dmah) {
 105                         drm_pci_free(dev, dev_priv->status_page_dmah);
 106                         /* Need to rewrite hardware status page */
 107                         I915_WRITE(0x02080, 0x1ffff000);
 108                 }
 109
 110                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 111                          DRM_MEM_DRIVER);
 112
 113                 dev->dev_private = NULL;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static int i915_initialize(drm_device_t * dev,
 120                            drm_i915_private_t * dev_priv,
 121                            drm_i915_init_t * init)
 122 {
 123         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 124
 125         DRM_GETSAREA();
 126         if (!dev_priv->sarea) {
 127                 DRM_ERROR("can not find sarea!\n");
 128                 dev->dev_private = (void *)dev_priv;
 129                 i915_dma_cleanup(dev);
 130                 return DRM_ERR(EINVAL);
 131         }
 132
 133         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 134         if (!dev_priv->mmio_map) {
 135                 dev->dev_private = (void *)dev_priv;
 136                 i915_dma_cleanup(dev);
 137                 DRM_ERROR("can not find mmio map!\n");
 138                 return DRM_ERR(EINVAL);
 139         }
 140
 141         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 142             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 143
 144         dev_priv->ring.Start = init->ring_start;
 145         dev_priv->ring.End = init->ring_end;
 146         dev_priv->ring.Size = init->ring_size;
 147         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 148
 149         dev_priv->ring.map.offset = init->ring_start;
 150         dev_priv->ring.map.size = init->ring_size;
 151         dev_priv->ring.map.type = 0;
 152         dev_priv->ring.map.flags = 0;
 153         dev_priv->ring.map.mtrr = 0;
 154
 155         drm_core_ioremap(&dev_priv->ring.map, dev);
 156
 157         if (dev_priv->ring.map.handle == NULL) {
 158                 dev->dev_private = (void *)dev_priv;
 159                 i915_dma_cleanup(dev);
 160                 DRM_ERROR("can not ioremap virtual address for"
 161                           " ring buffer\n");
 162                 return DRM_ERR(ENOMEM);
 163         }
 164
 165         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 166
 167         dev_priv->cpp = init->cpp;
 168         dev_priv->current_page = 0;
 169         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 170
 171         /* We are using separate values as placeholders for mechanisms for
 172          * private backbuffer/depthbuffer usage.
 173          */
 174         dev_priv->use_mi_batchbuffer_start = 0;
 175
 176         /* Allow hardware batchbuffers unless told otherwise.
 177          */
 178         dev_priv->allow_batchbuffer = 1;
 179
 180         /* Program Hardware Status Page */
 181         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 182             0xffffffff);
 183
 184         if (!dev_priv->status_page_dmah) {
 185                 dev->dev_private = (void *)dev_priv;
 186                 i915_dma_cleanup(dev);
 187                 DRM_ERROR("Can not allocate hardware status page\n");
 188                 return DRM_ERR(ENOMEM);
 189         }
 190         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 191         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 192
 193         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 194         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 195
 196         I915_WRITE(0x02080, dev_priv->dma_status_page);
 197         DRM_DEBUG("Enabled hardware status page\n");
 198         dev->dev_private = (void *)dev_priv;
 199 #ifdef I915_HAVE_BUFFER
 200         drm_bo_driver_init(dev);
 201 #endif
 202         return 0;
 203 }
 204
 205 static int i915_dma_resume(drm_device_t * dev)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208
 209         DRM_DEBUG("%s\n", __FUNCTION__);
 210
 211         if (!dev_priv->sarea) {
 212                 DRM_ERROR("can not find sarea!\n");
 213                 return DRM_ERR(EINVAL);
 214         }
 215
 216         if (!dev_priv->mmio_map) {
 217                 DRM_ERROR("can not find mmio map!\n");
 218                 return DRM_ERR(EINVAL);
 219         }
 220
 221         if (dev_priv->ring.map.handle == NULL) {
 222                 DRM_ERROR("can not ioremap virtual address for"
 223                           " ring buffer\n");
 224                 return DRM_ERR(ENOMEM);
 225         }
 226
 227         /* Program Hardware Status Page */
 228         if (!dev_priv->hw_status_page) {
 229                 DRM_ERROR("Can not find hardware status page\n");
 230                 return DRM_ERR(EINVAL);
 231         }
 232         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 233
 234         I915_WRITE(0x02080, dev_priv->dma_status_page);
 235         DRM_DEBUG("Enabled hardware status page\n");
 236
 237         return 0;
 238 }
 239
 240 static int i915_dma_init(DRM_IOCTL_ARGS)
 241 {
 242         DRM_DEVICE;
 243         drm_i915_private_t *dev_priv;
 244         drm_i915_init_t init;
 245         int retcode = 0;
 246
 247         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 248                                  sizeof(init));
 249
 250         switch (init.func) {
 251         case I915_INIT_DMA:
 252                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 253                                      DRM_MEM_DRIVER);
 254                 if (dev_priv == NULL)
 255                         return DRM_ERR(ENOMEM);
 256                 retcode = i915_initialize(dev, dev_priv, &init);
 257                 break;
 258         case I915_CLEANUP_DMA:
 259                 retcode = i915_dma_cleanup(dev);
 260                 break;
 261         case I915_RESUME_DMA:
 262                 retcode = i915_dma_resume(dev);
 263                 break;
 264         default:
 265                 retcode = DRM_ERR(EINVAL);
 266                 break;
 267         }
 268
 269         return retcode;
 270 }
 271
 272 /* Implement basically the same security restrictions as hardware does
 273  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 274  *
 275  * Most of the calculations below involve calculating the size of a
 276  * particular instruction.  It's important to get the size right as
 277  * that tells us where the next instruction to check is.  Any illegal
 278  * instruction detected will be given a size of zero, which is a
 279  * signal to abort the rest of the buffer.
 280  */
 281 static int do_validate_cmd(int cmd)
 282 {
 283         switch (((cmd >> 29) & 0x7)) {
 284         case 0x0:
 285                 switch ((cmd >> 23) & 0x3f) {
 286                 case 0x0:
 287                         return 1;       /* MI_NOOP */
 288                 case 0x4:
 289                         return 1;       /* MI_FLUSH */
 290                 default:
 291                         return 0;       /* disallow everything else */
 292                 }
 293                 break;
 294         case 0x1:
 295                 return 0;       /* reserved */
 296         case 0x2:
 297                 return (cmd & 0xff) + 2;        /* 2d commands */
 298         case 0x3:
 299                 if (((cmd >> 24) & 0x1f) <= 0x18)
 300                         return 1;
 301
 302                 switch ((cmd >> 24) & 0x1f) {
 303                 case 0x1c:
 304                         return 1;
 305                 case 0x1d:
 306                         switch ((cmd >> 16) & 0xff) {
 307                         case 0x3:
 308                                 return (cmd & 0x1f) + 2;
 309                         case 0x4:
 310                                 return (cmd & 0xf) + 2;
 311                         default:
 312                                 return (cmd & 0xffff) + 2;
 313                         }
 314                 case 0x1e:
 315                         if (cmd & (1 << 23))
 316                                 return (cmd & 0xffff) + 1;
 317                         else
 318                                 return 1;
 319                 case 0x1f:
 320                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 321                                 return (cmd & 0x1ffff) + 2;
 322                         else if (cmd & (1 << 17))       /* indirect random */
 323                                 if ((cmd & 0xffff) == 0)
 324                                         return 0;       /* unknown length, too hard */
 325                                 else
 326                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 327                         else
 328                                 return 2;       /* indirect sequential */
 329                 default:
 330                         return 0;
 331                 }
 332         default:
 333                 return 0;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int validate_cmd(int cmd)
 340 {
 341         int ret = do_validate_cmd(cmd);
 342
 343 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 344
 345         return ret;
 346 }
 347
 348 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 349 {
 350         drm_i915_private_t *dev_priv = dev->dev_private;
 351         int i;
 352         RING_LOCALS;
 353
 354         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 355                 return DRM_ERR(EINVAL);
 356
 357         BEGIN_LP_RING((dwords+1)&~1);
 358
 359         for (i = 0; i < dwords;) {
 360                 int cmd, sz;
 361
 362                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 363                         return DRM_ERR(EINVAL);
 364
 365                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 366                         return DRM_ERR(EINVAL);
 367
 368                 OUT_RING(cmd);
 369
 370                 while (++i, --sz) {
 371                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 372                                                          sizeof(cmd))) {
 373                                 return DRM_ERR(EINVAL);
 374                         }
 375                         OUT_RING(cmd);
 376                 }
 377         }
 378
 379         if (dwords & 1)
 380                 OUT_RING(0);
 381
 382         ADVANCE_LP_RING();
 383
 384         return 0;
 385 }
 386
 387 static int i915_emit_box(drm_device_t * dev,
 388                          drm_clip_rect_t __user * boxes,
 389                          int i, int DR1, int DR4)
 390 {
 391         drm_i915_private_t *dev_priv = dev->dev_private;
 392         drm_clip_rect_t box;
 393         RING_LOCALS;
 394
 395         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 396                 return DRM_ERR(EFAULT);
 397         }
 398
 399         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 400                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 401                           box.x1, box.y1, box.x2, box.y2);
 402                 return DRM_ERR(EINVAL);
 403         }
 404
 405         if (IS_I965G(dev)) {
 406                 BEGIN_LP_RING(4);
 407                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 408                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 409                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 410                 OUT_RING(DR4);
 411                 ADVANCE_LP_RING();
 412         } else {
 413                 BEGIN_LP_RING(6);
 414                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 415                 OUT_RING(DR1);
 416                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 417                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 418                 OUT_RING(DR4);
 419                 OUT_RING(0);
 420                 ADVANCE_LP_RING();
 421         }
 422
 423         return 0;
 424 }
 425
 426 /* XXX: Emitting the counter should really be moved to part of the IRQ
 427  * emit.  For now, do it in both places:
 428  */
 429
 430 void i915_emit_breadcrumb(drm_device_t *dev)
 431 {
 432         drm_i915_private_t *dev_priv = dev->dev_private;
 433         RING_LOCALS;
 434
 435         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 436
 437         if (dev_priv->counter > 0x7FFFFFFFUL)
 438                  dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
 439
 440         BEGIN_LP_RING(4);
 441         OUT_RING(CMD_STORE_DWORD_IDX);
 442         OUT_RING(20);
 443         OUT_RING(dev_priv->counter);
 444         OUT_RING(0);
 445         ADVANCE_LP_RING();
 446 }
 447
 448
 449 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 450 {
 451         drm_i915_private_t *dev_priv = dev->dev_private;
 452         uint32_t flush_cmd = CMD_MI_FLUSH;
 453         RING_LOCALS;
 454
 455         flush_cmd |= flush;
 456
 457         i915_kernel_lost_context(dev);
 458
 459         BEGIN_LP_RING(4);
 460         OUT_RING(flush_cmd);
 461         OUT_RING(0);
 462         OUT_RING(0);
 463         OUT_RING(0);
 464         ADVANCE_LP_RING();
 465
 466         return 0;
 467 }
 468
 469
 470 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 471                                    drm_i915_cmdbuffer_t * cmd)
 472 {
 473         drm_i915_private_t *dev_priv = dev->dev_private;
 474         int nbox = cmd->num_cliprects;
 475         int i = 0, count, ret;
 476
 477         if (cmd->sz & 0x3) {
 478                 DRM_ERROR("alignment");
 479                 return DRM_ERR(EINVAL);
 480         }
 481
 482         i915_kernel_lost_context(dev);
 483
 484         count = nbox ? nbox : 1;
 485
 486         for (i = 0; i < count; i++) {
 487                 if (i < nbox) {
 488                         ret = i915_emit_box(dev, cmd->cliprects, i,
 489                                             cmd->DR1, cmd->DR4);
 490                         if (ret)
 491                                 return ret;
 492                 }
 493
 494                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 495                 if (ret)
 496                         return ret;
 497         }
 498
 499         i915_emit_breadcrumb( dev );
 500 #ifdef I915_HAVE_FENCE
 501         drm_fence_flush_old(dev, 0, dev_priv->counter);
 502 #endif
 503         return 0;
 504 }
 505
 506 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 507                                      drm_i915_batchbuffer_t * batch)
 508 {
 509         drm_i915_private_t *dev_priv = dev->dev_private;
 510         drm_clip_rect_t __user *boxes = batch->cliprects;
 511         int nbox = batch->num_cliprects;
 512         int i = 0, count;
 513         RING_LOCALS;
 514
 515         if ((batch->start | batch->used) & 0x7) {
 516                 DRM_ERROR("alignment");
 517                 return DRM_ERR(EINVAL);
 518         }
 519
 520         i915_kernel_lost_context(dev);
 521
 522         count = nbox ? nbox : 1;
 523
 524         for (i = 0; i < count; i++) {
 525                 if (i < nbox) {
 526                         int ret = i915_emit_box(dev, boxes, i,
 527                                                 batch->DR1, batch->DR4);
 528                         if (ret)
 529                                 return ret;
 530                 }
 531
 532                 if (dev_priv->use_mi_batchbuffer_start) {
 533                         BEGIN_LP_RING(2);
 534                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 535                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 536                         ADVANCE_LP_RING();
 537                 } else {
 538                         BEGIN_LP_RING(4);
 539                         OUT_RING(MI_BATCH_BUFFER);
 540                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 541                         OUT_RING(batch->start + batch->used - 4);
 542                         OUT_RING(0);
 543                         ADVANCE_LP_RING();
 544                 }
 545         }
 546
 547         i915_emit_breadcrumb( dev );
 548 #ifdef I915_HAVE_FENCE
 549         drm_fence_flush_old(dev, 0, dev_priv->counter);
 550 #endif
 551         return 0;
 552 }
 553
 554 static void i915_do_dispatch_flip(drm_device_t * dev, int pipe, int sync)
 555 {
 556         drm_i915_private_t *dev_priv = dev->dev_private;
 557         u32 num_pages, current_page, next_page, dspbase;
 558         int shift = 2 * pipe, x, y;
 559         RING_LOCALS;
 560
 561         /* Calculate display base offset */
 562         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 563         current_page = (dev_priv->current_page >> shift) & 0x3;
 564         next_page = (current_page + 1) % num_pages;
 565
 566         switch (next_page) {
 567         default:
 568         case 0:
 569                 dspbase = dev_priv->sarea_priv->front_offset;
 570                 break;
 571         case 1:
 572                 dspbase = dev_priv->sarea_priv->back_offset;
 573                 break;
 574         case 2:
 575                 dspbase = dev_priv->sarea_priv->third_offset;
 576                 break;
 577         }
 578
 579         if (pipe == 0) {
 580                 x = dev_priv->sarea_priv->pipeA_x;
 581                 y = dev_priv->sarea_priv->pipeA_y;
 582         } else {
 583                 x = dev_priv->sarea_priv->pipeB_x;
 584                 y = dev_priv->sarea_priv->pipeB_y;
 585         }
 586
 587         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 588
 589         DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page,
 590                   dspbase);
 591
 592         BEGIN_LP_RING(4);
 593         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 594                  (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 595         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 596         OUT_RING(dspbase);
 597         OUT_RING(0);
 598         ADVANCE_LP_RING();
 599
 600         dev_priv->current_page &= ~(0x3 << shift);
 601         dev_priv->current_page |= next_page << shift;
 602 }
 603
 604 void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync)
 605 {
 606         drm_i915_private_t *dev_priv = dev->dev_private;
 607         u32 mi_wait = MI_WAIT_FOR_EVENT;
 608         int i;
 609         RING_LOCALS;
 610
 611         DRM_DEBUG("%s: pipes=0x%x page=%d pfCurrentPage=%d\n",
 612                   __FUNCTION__,
 613                   pipes, dev_priv->current_page,
 614                   dev_priv->sarea_priv->pf_current_page);
 615
 616         if (pipes & 0x1)
 617                 mi_wait |= MI_WAIT_FOR_PLANE_A_FLIP;
 618
 619         if (pipes & 0x2)
 620                 mi_wait |= MI_WAIT_FOR_PLANE_B_FLIP;
 621
 622         i915_kernel_lost_context(dev);
 623
 624         BEGIN_LP_RING(2);
 625         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 626         OUT_RING(0);
 627         ADVANCE_LP_RING();
 628
 629         /* Wait for pending flips to take effect */
 630         BEGIN_LP_RING(2);
 631         OUT_RING(mi_wait);
 632         OUT_RING(0);
 633         ADVANCE_LP_RING();
 634
 635         for (i = 0; i < 2; i++)
 636                 if (pipes & (1 << i))
 637                         i915_do_dispatch_flip(dev, i, sync);
 638
 639         i915_emit_breadcrumb(dev);
 640 #ifdef I915_HAVE_FENCE
 641         if (!sync)
 642                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 643 #endif
 644
 645         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 646 }
 647
 648 static int i915_quiescent(drm_device_t * dev)
 649 {
 650         drm_i915_private_t *dev_priv = dev->dev_private;
 651
 652         i915_kernel_lost_context(dev);
 653         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 654 }
 655
 656 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 657 {
 658         DRM_DEVICE;
 659
 660         LOCK_TEST_WITH_RETURN(dev, filp);
 661
 662         return i915_quiescent(dev);
 663 }
 664
 665 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 666 {
 667         DRM_DEVICE;
 668         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 669         u32 *hw_status = dev_priv->hw_status_page;
 670         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 671             dev_priv->sarea_priv;
 672         drm_i915_batchbuffer_t batch;
 673         int ret;
 674
 675         if (!dev_priv->allow_batchbuffer) {
 676                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 677                 return DRM_ERR(EINVAL);
 678         }
 679
 680         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 681                                  sizeof(batch));
 682
 683         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 684                   batch.start, batch.used, batch.num_cliprects);
 685
 686         LOCK_TEST_WITH_RETURN(dev, filp);
 687
 688         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 689                                                        batch.num_cliprects *
 690                                                        sizeof(drm_clip_rect_t)))
 691                 return DRM_ERR(EFAULT);
 692
 693         ret = i915_dispatch_batchbuffer(dev, &batch);
 694
 695         sarea_priv->last_dispatch = (int)hw_status[5];
 696         return ret;
 697 }
 698
 699 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 700 {
 701         DRM_DEVICE;
 702         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 703         u32 *hw_status = dev_priv->hw_status_page;
 704         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 705             dev_priv->sarea_priv;
 706         drm_i915_cmdbuffer_t cmdbuf;
 707         int ret;
 708
 709         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 710                                  sizeof(cmdbuf));
 711
 712         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 713                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 714
 715         LOCK_TEST_WITH_RETURN(dev, filp);
 716
 717         if (cmdbuf.num_cliprects &&
 718             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 719                                 cmdbuf.num_cliprects *
 720                                 sizeof(drm_clip_rect_t))) {
 721                 DRM_ERROR("Fault accessing cliprects\n");
 722                 return DRM_ERR(EFAULT);
 723         }
 724
 725         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 726         if (ret) {
 727                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 728                 return ret;
 729         }
 730
 731         sarea_priv->last_dispatch = (int)hw_status[5];
 732         return 0;
 733 }
 734
 735 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 736 {
 737         drm_i915_private_t *dev_priv = dev->dev_private;
 738         int j;
 739
 740         DRM_DEBUG("%s\n", __FUNCTION__);
 741
 742         for (j = 0; j < 2 && dev_priv->current_page != 0; j++) {
 743                 int i, pipes;
 744
 745                 for (i = 0, pipes = 0; i < 2; i++)
 746                         if (dev_priv->current_page & (0x3 << (2 * i)))
 747                                 pipes |= 1 << i;
 748
 749                 i915_dispatch_flip(dev, pipes, 0);
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 756 {
 757         DRM_DEVICE;
 758         drm_i915_flip_t param;
 759
 760         DRM_DEBUG("%s\n", __FUNCTION__);
 761
 762         LOCK_TEST_WITH_RETURN(dev, filp);
 763
 764         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data,
 765                                  sizeof(param));
 766
 767         if (param.pipes & ~0x3) {
 768                 DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n",
 769                           param.pipes);
 770                 return DRM_ERR(EINVAL);
 771         }
 772
 773         i915_dispatch_flip(dev, param.pipes, 0);
 774
 775         return 0;
 776 }
 777
 778
 779 static int i915_getparam(DRM_IOCTL_ARGS)
 780 {
 781         DRM_DEVICE;
 782         drm_i915_private_t *dev_priv = dev->dev_private;
 783         drm_i915_getparam_t param;
 784         int value;
 785
 786         if (!dev_priv) {
 787                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 788                 return DRM_ERR(EINVAL);
 789         }
 790
 791         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 792                                  sizeof(param));
 793
 794         switch (param.param) {
 795         case I915_PARAM_IRQ_ACTIVE:
 796                 value = dev->irq ? 1 : 0;
 797                 break;
 798         case I915_PARAM_ALLOW_BATCHBUFFER:
 799                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 800                 break;
 801         case I915_PARAM_LAST_DISPATCH:
 802                 value = READ_BREADCRUMB(dev_priv);
 803                 break;
 804         default:
 805                 DRM_ERROR("Unknown parameter %d\n", param.param);
 806                 return DRM_ERR(EINVAL);
 807         }
 808
 809         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 810                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 811                 return DRM_ERR(EFAULT);
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int i915_setparam(DRM_IOCTL_ARGS)
 818 {
 819         DRM_DEVICE;
 820         drm_i915_private_t *dev_priv = dev->dev_private;
 821         drm_i915_setparam_t param;
 822
 823         if (!dev_priv) {
 824                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 825                 return DRM_ERR(EINVAL);
 826         }
 827
 828         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 829                                  sizeof(param));
 830
 831         switch (param.param) {
 832         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 833                 dev_priv->use_mi_batchbuffer_start = param.value;
 834                 break;
 835         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 836                 dev_priv->tex_lru_log_granularity = param.value;
 837                 break;
 838         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 839                 dev_priv->allow_batchbuffer = param.value;
 840                 break;
 841         default:
 842                 DRM_ERROR("unknown parameter %d\n", param.param);
 843                 return DRM_ERR(EINVAL);
 844         }
 845
 846         return 0;
 847 }
 848
 849 drm_i915_mmio_entry_t mmio_table[] = {
 850         [MMIO_REGS_PS_DEPTH_COUNT] = {
 851                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 852                 0x2350,
 853                 8
 854         }
 855 };
 856
 857 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 858
 859 static int i915_mmio(DRM_IOCTL_ARGS)
 860 {
 861         char buf[32];
 862         DRM_DEVICE;
 863         drm_i915_private_t *dev_priv = dev->dev_private;
 864         drm_i915_mmio_entry_t *e;
 865         drm_i915_mmio_t mmio;
 866         void __iomem *base;
 867         if (!dev_priv) {
 868                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 869                 return DRM_ERR(EINVAL);
 870         }
 871         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
 872                                  sizeof(mmio));
 873
 874         if (mmio.reg >= mmio_table_size)
 875                 return DRM_ERR(EINVAL);
 876
 877         e = &mmio_table[mmio.reg];
 878         base = dev_priv->mmio_map->handle + e->offset;
 879
 880         switch (mmio.read_write) {
 881                 case I915_MMIO_READ:
 882                         if (!(e->flag & I915_MMIO_MAY_READ))
 883                                 return DRM_ERR(EINVAL);
 884                         memcpy_fromio(buf, base, e->size);
 885                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 886                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 887                                 return DRM_ERR(EFAULT);
 888                         }
 889                         break;
 890
 891                 case I915_MMIO_WRITE:
 892                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 893                                 return DRM_ERR(EINVAL);
 894                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 895                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 896                                 return DRM_ERR(EFAULT);
 897                         }
 898                         memcpy_toio(base, buf, e->size);
 899                         break;
 900         }
 901         return 0;
 902 }
 903
 904 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 905 {
 906         /* i915 has 4 more counters */
 907         dev->counters += 4;
 908         dev->types[6] = _DRM_STAT_IRQ;
 909         dev->types[7] = _DRM_STAT_PRIMARY;
 910         dev->types[8] = _DRM_STAT_SECONDARY;
 911         dev->types[9] = _DRM_STAT_DMA;
 912
 913         return 0;
 914 }
 915
 916 void i915_driver_lastclose(drm_device_t * dev)
 917 {
 918         if (dev->dev_private) {
 919                 drm_i915_private_t *dev_priv = dev->dev_private;
 920                 i915_mem_takedown(&(dev_priv->agp_heap));
 921         }
 922         i915_dma_cleanup(dev);
 923 }
 924
 925 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 926 {
 927         if (dev->dev_private) {
 928                 drm_i915_private_t *dev_priv = dev->dev_private;
 929                 i915_do_cleanup_pageflip(dev);
 930                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 931         }
 932 }
 933
 934 drm_ioctl_desc_t i915_ioctls[] = {
 935         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 936         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 937         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 938         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 939         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 940         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 941         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 942         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 943         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 944         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 945         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 946         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 947         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 948         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 949         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 950         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 951         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 952 };
 953
 954 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 955
 956 /**
 957  * Determine if the device really is AGP or not.
 958  *
 959  * All Intel graphics chipsets are treated as AGP, even if they are really
 960  * PCI-e.
 961  *
 962  * \param dev   The device to be tested.
 963  *
 964  * \returns
 965  * A value of 1 is always retured to indictate every i9x5 is AGP.
 966  */
 967 int i915_driver_device_is_agp(drm_device_t * dev)
 968 {
 969         return 1;
 970 }