shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2 || \
  38                         dev->pci_device == 0x2A02)
  39
  40
  41 /* Really want an OS-independent resettable timer.  Would like to have
  42  * this loop run for (eg) 3 sec, but have the timer reset every time
  43  * the head pointer changes, so that EBUSY only happens if the ring
  44  * actually stalls for (eg) 3 seconds.
  45  */
  46 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
  47 {
  48         drm_i915_private_t *dev_priv = dev->dev_private;
  49         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  50         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  51         int i;
  52
  53         for (i = 0; i < 10000; i++) {
  54                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  55                 ring->space = ring->head - (ring->tail + 8);
  56                 if (ring->space < 0)
  57                         ring->space += ring->Size;
  58                 if (ring->space >= n)
  59                         return 0;
  60
  61                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  62
  63                 if (ring->head != last_head)
  64                         i = 0;
  65
  66                 last_head = ring->head;
  67                 DRM_UDELAY(1);
  68         }
  69
  70         return DRM_ERR(EBUSY);
  71 }
  72
  73 void i915_kernel_lost_context(drm_device_t * dev)
  74 {
  75         drm_i915_private_t *dev_priv = dev->dev_private;
  76         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  77
  78         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  79         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  80         ring->space = ring->head - (ring->tail + 8);
  81         if (ring->space < 0)
  82                 ring->space += ring->Size;
  83
  84         if (ring->head == ring->tail)
  85                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  86 }
  87
  88 static int i915_dma_cleanup(drm_device_t * dev)
  89 {
  90         /* Make sure interrupts are disabled here because the uninstall ioctl
  91          * may not have been called from userspace and after dev_private
  92          * is freed, it's too late.
  93          */
  94         if (dev->irq)
  95                 drm_irq_uninstall(dev);
  96
  97         if (dev->dev_private) {
  98                 drm_i915_private_t *dev_priv =
  99                     (drm_i915_private_t *) dev->dev_private;
 100
 101                 if (dev_priv->ring.virtual_start) {
 102                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 103                 }
 104
 105                 if (dev_priv->status_page_dmah) {
 106                         drm_pci_free(dev, dev_priv->status_page_dmah);
 107                         /* Need to rewrite hardware status page */
 108                         I915_WRITE(0x02080, 0x1ffff000);
 109                 }
 110
 111                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 112                          DRM_MEM_DRIVER);
 113
 114                 dev->dev_private = NULL;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static int i915_initialize(drm_device_t * dev,
 121                            drm_i915_private_t * dev_priv,
 122                            drm_i915_init_t * init)
 123 {
 124         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 125
 126         DRM_GETSAREA();
 127         if (!dev_priv->sarea) {
 128                 DRM_ERROR("can not find sarea!\n");
 129                 dev->dev_private = (void *)dev_priv;
 130                 i915_dma_cleanup(dev);
 131                 return DRM_ERR(EINVAL);
 132         }
 133
 134         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 135         if (!dev_priv->mmio_map) {
 136                 dev->dev_private = (void *)dev_priv;
 137                 i915_dma_cleanup(dev);
 138                 DRM_ERROR("can not find mmio map!\n");
 139                 return DRM_ERR(EINVAL);
 140         }
 141
 142         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 143             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 144
 145         dev_priv->ring.Start = init->ring_start;
 146         dev_priv->ring.End = init->ring_end;
 147         dev_priv->ring.Size = init->ring_size;
 148         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 149
 150         dev_priv->ring.map.offset = init->ring_start;
 151         dev_priv->ring.map.size = init->ring_size;
 152         dev_priv->ring.map.type = 0;
 153         dev_priv->ring.map.flags = 0;
 154         dev_priv->ring.map.mtrr = 0;
 155
 156         drm_core_ioremap(&dev_priv->ring.map, dev);
 157
 158         if (dev_priv->ring.map.handle == NULL) {
 159                 dev->dev_private = (void *)dev_priv;
 160                 i915_dma_cleanup(dev);
 161                 DRM_ERROR("can not ioremap virtual address for"
 162                           " ring buffer\n");
 163                 return DRM_ERR(ENOMEM);
 164         }
 165
 166         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 167
 168         dev_priv->cpp = init->cpp;
 169         dev_priv->back_offset = init->back_offset;
 170         dev_priv->front_offset = init->front_offset;
 171         dev_priv->current_page = 0;
 172         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 173
 174         /* We are using separate values as placeholders for mechanisms for
 175          * private backbuffer/depthbuffer usage.
 176          */
 177         dev_priv->use_mi_batchbuffer_start = 0;
 178
 179         /* Allow hardware batchbuffers unless told otherwise.
 180          */
 181         dev_priv->allow_batchbuffer = 1;
 182
 183         /* Program Hardware Status Page */
 184         dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
 185             0xffffffff);
 186
 187         if (!dev_priv->status_page_dmah) {
 188                 dev->dev_private = (void *)dev_priv;
 189                 i915_dma_cleanup(dev);
 190                 DRM_ERROR("Can not allocate hardware status page\n");
 191                 return DRM_ERR(ENOMEM);
 192         }
 193         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 194         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 195
 196         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 197         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 198
 199         I915_WRITE(0x02080, dev_priv->dma_status_page);
 200         DRM_DEBUG("Enabled hardware status page\n");
 201         dev->dev_private = (void *)dev_priv;
 202 #ifdef I915_HAVE_BUFFER
 203         drm_bo_driver_init(dev);
 204 #endif
 205         return 0;
 206 }
 207
 208 static int i915_dma_resume(drm_device_t * dev)
 209 {
 210         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 211
 212         DRM_DEBUG("%s\n", __FUNCTION__);
 213
 214         if (!dev_priv->sarea) {
 215                 DRM_ERROR("can not find sarea!\n");
 216                 return DRM_ERR(EINVAL);
 217         }
 218
 219         if (!dev_priv->mmio_map) {
 220                 DRM_ERROR("can not find mmio map!\n");
 221                 return DRM_ERR(EINVAL);
 222         }
 223
 224         if (dev_priv->ring.map.handle == NULL) {
 225                 DRM_ERROR("can not ioremap virtual address for"
 226                           " ring buffer\n");
 227                 return DRM_ERR(ENOMEM);
 228         }
 229
 230         /* Program Hardware Status Page */
 231         if (!dev_priv->hw_status_page) {
 232                 DRM_ERROR("Can not find hardware status page\n");
 233                 return DRM_ERR(EINVAL);
 234         }
 235         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 236
 237         I915_WRITE(0x02080, dev_priv->dma_status_page);
 238         DRM_DEBUG("Enabled hardware status page\n");
 239
 240         return 0;
 241 }
 242
 243 static int i915_dma_init(DRM_IOCTL_ARGS)
 244 {
 245         DRM_DEVICE;
 246         drm_i915_private_t *dev_priv;
 247         drm_i915_init_t init;
 248         int retcode = 0;
 249
 250         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 251                                  sizeof(init));
 252
 253         switch (init.func) {
 254         case I915_INIT_DMA:
 255                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 256                                      DRM_MEM_DRIVER);
 257                 if (dev_priv == NULL)
 258                         return DRM_ERR(ENOMEM);
 259                 retcode = i915_initialize(dev, dev_priv, &init);
 260                 break;
 261         case I915_CLEANUP_DMA:
 262                 retcode = i915_dma_cleanup(dev);
 263                 break;
 264         case I915_RESUME_DMA:
 265                 retcode = i915_dma_resume(dev);
 266                 break;
 267         default:
 268                 retcode = DRM_ERR(EINVAL);
 269                 break;
 270         }
 271
 272         return retcode;
 273 }
 274
 275 /* Implement basically the same security restrictions as hardware does
 276  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 277  *
 278  * Most of the calculations below involve calculating the size of a
 279  * particular instruction.  It's important to get the size right as
 280  * that tells us where the next instruction to check is.  Any illegal
 281  * instruction detected will be given a size of zero, which is a
 282  * signal to abort the rest of the buffer.
 283  */
 284 static int do_validate_cmd(int cmd)
 285 {
 286         switch (((cmd >> 29) & 0x7)) {
 287         case 0x0:
 288                 switch ((cmd >> 23) & 0x3f) {
 289                 case 0x0:
 290                         return 1;       /* MI_NOOP */
 291                 case 0x4:
 292                         return 1;       /* MI_FLUSH */
 293                 default:
 294                         return 0;       /* disallow everything else */
 295                 }
 296                 break;
 297         case 0x1:
 298                 return 0;       /* reserved */
 299         case 0x2:
 300                 return (cmd & 0xff) + 2;        /* 2d commands */
 301         case 0x3:
 302                 if (((cmd >> 24) & 0x1f) <= 0x18)
 303                         return 1;
 304
 305                 switch ((cmd >> 24) & 0x1f) {
 306                 case 0x1c:
 307                         return 1;
 308                 case 0x1d:
 309                         switch ((cmd >> 16) & 0xff) {
 310                         case 0x3:
 311                                 return (cmd & 0x1f) + 2;
 312                         case 0x4:
 313                                 return (cmd & 0xf) + 2;
 314                         default:
 315                                 return (cmd & 0xffff) + 2;
 316                         }
 317                 case 0x1e:
 318                         if (cmd & (1 << 23))
 319                                 return (cmd & 0xffff) + 1;
 320                         else
 321                                 return 1;
 322                 case 0x1f:
 323                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 324                                 return (cmd & 0x1ffff) + 2;
 325                         else if (cmd & (1 << 17))       /* indirect random */
 326                                 if ((cmd & 0xffff) == 0)
 327                                         return 0;       /* unknown length, too hard */
 328                                 else
 329                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 330                         else
 331                                 return 2;       /* indirect sequential */
 332                 default:
 333                         return 0;
 334                 }
 335         default:
 336                 return 0;
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int validate_cmd(int cmd)
 343 {
 344         int ret = do_validate_cmd(cmd);
 345
 346 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 347
 348         return ret;
 349 }
 350
 351 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
 352 {
 353         drm_i915_private_t *dev_priv = dev->dev_private;
 354         int i;
 355         RING_LOCALS;
 356
 357         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 358                 return DRM_ERR(EINVAL);
 359
 360         BEGIN_LP_RING((dwords+1)&~1);
 361
 362         for (i = 0; i < dwords;) {
 363                 int cmd, sz;
 364
 365                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 366                         return DRM_ERR(EINVAL);
 367
 368                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 369                         return DRM_ERR(EINVAL);
 370
 371                 OUT_RING(cmd);
 372
 373                 while (++i, --sz) {
 374                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 375                                                          sizeof(cmd))) {
 376                                 return DRM_ERR(EINVAL);
 377                         }
 378                         OUT_RING(cmd);
 379                 }
 380         }
 381
 382         if (dwords & 1)
 383                 OUT_RING(0);
 384
 385         ADVANCE_LP_RING();
 386
 387         return 0;
 388 }
 389
 390 static int i915_emit_box(drm_device_t * dev,
 391                          drm_clip_rect_t __user * boxes,
 392                          int i, int DR1, int DR4)
 393 {
 394         drm_i915_private_t *dev_priv = dev->dev_private;
 395         drm_clip_rect_t box;
 396         RING_LOCALS;
 397
 398         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 399                 return DRM_ERR(EFAULT);
 400         }
 401
 402         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 403                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 404                           box.x1, box.y1, box.x2, box.y2);
 405                 return DRM_ERR(EINVAL);
 406         }
 407
 408         if (IS_I965G(dev)) {
 409                 BEGIN_LP_RING(4);
 410                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 411                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 412                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 413                 OUT_RING(DR4);
 414                 ADVANCE_LP_RING();
 415         } else {
 416                 BEGIN_LP_RING(6);
 417                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 418                 OUT_RING(DR1);
 419                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 420                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 421                 OUT_RING(DR4);
 422                 OUT_RING(0);
 423                 ADVANCE_LP_RING();
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* XXX: Emitting the counter should really be moved to part of the IRQ
 430  * emit.  For now, do it in both places:
 431  */
 432
 433 static void i915_emit_breadcrumb(drm_device_t *dev)
 434 {
 435         drm_i915_private_t *dev_priv = dev->dev_private;
 436         RING_LOCALS;
 437
 438         dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
 439
 440         BEGIN_LP_RING(4);
 441         OUT_RING(CMD_STORE_DWORD_IDX);
 442         OUT_RING(20);
 443         OUT_RING(dev_priv->counter);
 444         OUT_RING(0);
 445         ADVANCE_LP_RING();
 446 #ifdef I915_HAVE_FENCE
 447         drm_fence_flush_old(dev, 0, dev_priv->counter);
 448 #endif
 449 }
 450
 451
 452 int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush)
 453 {
 454         drm_i915_private_t *dev_priv = dev->dev_private;
 455         uint32_t flush_cmd = CMD_MI_FLUSH;
 456         RING_LOCALS;
 457
 458         flush_cmd |= flush;
 459
 460         i915_kernel_lost_context(dev);
 461
 462         BEGIN_LP_RING(4);
 463         OUT_RING(flush_cmd);
 464         OUT_RING(0);
 465         OUT_RING(0);
 466         OUT_RING(0);
 467         ADVANCE_LP_RING();
 468
 469         return 0;
 470 }
 471
 472
 473 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
 474                                    drm_i915_cmdbuffer_t * cmd)
 475 {
 476         int nbox = cmd->num_cliprects;
 477         int i = 0, count, ret;
 478
 479         if (cmd->sz & 0x3) {
 480                 DRM_ERROR("alignment");
 481                 return DRM_ERR(EINVAL);
 482         }
 483
 484         i915_kernel_lost_context(dev);
 485
 486         count = nbox ? nbox : 1;
 487
 488         for (i = 0; i < count; i++) {
 489                 if (i < nbox) {
 490                         ret = i915_emit_box(dev, cmd->cliprects, i,
 491                                             cmd->DR1, cmd->DR4);
 492                         if (ret)
 493                                 return ret;
 494                 }
 495
 496                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 497                 if (ret)
 498                         return ret;
 499         }
 500
 501         i915_emit_breadcrumb( dev );
 502         return 0;
 503 }
 504
 505 static int i915_dispatch_batchbuffer(drm_device_t * dev,
 506                                      drm_i915_batchbuffer_t * batch)
 507 {
 508         drm_i915_private_t *dev_priv = dev->dev_private;
 509         drm_clip_rect_t __user *boxes = batch->cliprects;
 510         int nbox = batch->num_cliprects;
 511         int i = 0, count;
 512         RING_LOCALS;
 513
 514         if ((batch->start | batch->used) & 0x7) {
 515                 DRM_ERROR("alignment");
 516                 return DRM_ERR(EINVAL);
 517         }
 518
 519         i915_kernel_lost_context(dev);
 520
 521         count = nbox ? nbox : 1;
 522
 523         for (i = 0; i < count; i++) {
 524                 if (i < nbox) {
 525                         int ret = i915_emit_box(dev, boxes, i,
 526                                                 batch->DR1, batch->DR4);
 527                         if (ret)
 528                                 return ret;
 529                 }
 530
 531                 if (dev_priv->use_mi_batchbuffer_start) {
 532                         BEGIN_LP_RING(2);
 533                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 534                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 535                         ADVANCE_LP_RING();
 536                 } else {
 537                         BEGIN_LP_RING(4);
 538                         OUT_RING(MI_BATCH_BUFFER);
 539                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 540                         OUT_RING(batch->start + batch->used - 4);
 541                         OUT_RING(0);
 542                         ADVANCE_LP_RING();
 543                 }
 544         }
 545
 546         i915_emit_breadcrumb( dev );
 547         return 0;
 548 }
 549
 550 static int i915_dispatch_flip(drm_device_t * dev)
 551 {
 552         drm_i915_private_t *dev_priv = dev->dev_private;
 553         RING_LOCALS;
 554
 555         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 556                   __FUNCTION__,
 557                   dev_priv->current_page,
 558                   dev_priv->sarea_priv->pf_current_page);
 559
 560         i915_kernel_lost_context(dev);
 561
 562         BEGIN_LP_RING(2);
 563         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
 564         OUT_RING(0);
 565         ADVANCE_LP_RING();
 566
 567         BEGIN_LP_RING(6);
 568         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 569         OUT_RING(0);
 570         if (dev_priv->current_page == 0) {
 571                 OUT_RING(dev_priv->back_offset);
 572                 dev_priv->current_page = 1;
 573         } else {
 574                 OUT_RING(dev_priv->front_offset);
 575                 dev_priv->current_page = 0;
 576         }
 577         OUT_RING(0);
 578         ADVANCE_LP_RING();
 579
 580         BEGIN_LP_RING(2);
 581         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 582         OUT_RING(0);
 583         ADVANCE_LP_RING();
 584
 585         dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 586
 587         BEGIN_LP_RING(4);
 588         OUT_RING(CMD_STORE_DWORD_IDX);
 589         OUT_RING(20);
 590         OUT_RING(dev_priv->counter);
 591         OUT_RING(0);
 592         ADVANCE_LP_RING();
 593 #ifdef I915_HAVE_FENCE
 594         drm_fence_flush_old(dev, 0, dev_priv->counter);
 595 #endif
 596         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 597         return 0;
 598 }
 599
 600 static int i915_quiescent(drm_device_t * dev)
 601 {
 602         drm_i915_private_t *dev_priv = dev->dev_private;
 603
 604         i915_kernel_lost_context(dev);
 605         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 606 }
 607
 608 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 609 {
 610         DRM_DEVICE;
 611
 612         LOCK_TEST_WITH_RETURN(dev, filp);
 613
 614         return i915_quiescent(dev);
 615 }
 616
 617 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 618 {
 619         DRM_DEVICE;
 620         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 621         u32 *hw_status = dev_priv->hw_status_page;
 622         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 623             dev_priv->sarea_priv;
 624         drm_i915_batchbuffer_t batch;
 625         int ret;
 626
 627         if (!dev_priv->allow_batchbuffer) {
 628                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 629                 return DRM_ERR(EINVAL);
 630         }
 631
 632         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 633                                  sizeof(batch));
 634
 635         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 636                   batch.start, batch.used, batch.num_cliprects);
 637
 638         LOCK_TEST_WITH_RETURN(dev, filp);
 639
 640         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 641                                                        batch.num_cliprects *
 642                                                        sizeof(drm_clip_rect_t)))
 643                 return DRM_ERR(EFAULT);
 644
 645         ret = i915_dispatch_batchbuffer(dev, &batch);
 646
 647         sarea_priv->last_dispatch = (int)hw_status[5];
 648         return ret;
 649 }
 650
 651 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 652 {
 653         DRM_DEVICE;
 654         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 655         u32 *hw_status = dev_priv->hw_status_page;
 656         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 657             dev_priv->sarea_priv;
 658         drm_i915_cmdbuffer_t cmdbuf;
 659         int ret;
 660
 661         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 662                                  sizeof(cmdbuf));
 663
 664         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 665                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 666
 667         LOCK_TEST_WITH_RETURN(dev, filp);
 668
 669         if (cmdbuf.num_cliprects &&
 670             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 671                                 cmdbuf.num_cliprects *
 672                                 sizeof(drm_clip_rect_t))) {
 673                 DRM_ERROR("Fault accessing cliprects\n");
 674                 return DRM_ERR(EFAULT);
 675         }
 676
 677         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 678         if (ret) {
 679                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 680                 return ret;
 681         }
 682
 683         sarea_priv->last_dispatch = (int)hw_status[5];
 684         return 0;
 685 }
 686
 687 static int i915_do_cleanup_pageflip(drm_device_t * dev)
 688 {
 689         drm_i915_private_t *dev_priv = dev->dev_private;
 690
 691         DRM_DEBUG("%s\n", __FUNCTION__);
 692         if (dev_priv->current_page != 0)
 693                 i915_dispatch_flip(dev);
 694
 695         return 0;
 696 }
 697
 698 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 699 {
 700         DRM_DEVICE;
 701
 702         DRM_DEBUG("%s\n", __FUNCTION__);
 703
 704         LOCK_TEST_WITH_RETURN(dev, filp);
 705
 706         return i915_dispatch_flip(dev);
 707 }
 708
 709
 710 static int i915_getparam(DRM_IOCTL_ARGS)
 711 {
 712         DRM_DEVICE;
 713         drm_i915_private_t *dev_priv = dev->dev_private;
 714         drm_i915_getparam_t param;
 715         int value;
 716
 717         if (!dev_priv) {
 718                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 719                 return DRM_ERR(EINVAL);
 720         }
 721
 722         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 723                                  sizeof(param));
 724
 725         switch (param.param) {
 726         case I915_PARAM_IRQ_ACTIVE:
 727                 value = dev->irq ? 1 : 0;
 728                 break;
 729         case I915_PARAM_ALLOW_BATCHBUFFER:
 730                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 731                 break;
 732         case I915_PARAM_LAST_DISPATCH:
 733                 value = READ_BREADCRUMB(dev_priv);
 734                 break;
 735         default:
 736                 DRM_ERROR("Unknown parameter %d\n", param.param);
 737                 return DRM_ERR(EINVAL);
 738         }
 739
 740         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 741                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 742                 return DRM_ERR(EFAULT);
 743         }
 744
 745         return 0;
 746 }
 747
 748 static int i915_setparam(DRM_IOCTL_ARGS)
 749 {
 750         DRM_DEVICE;
 751         drm_i915_private_t *dev_priv = dev->dev_private;
 752         drm_i915_setparam_t param;
 753
 754         if (!dev_priv) {
 755                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 756                 return DRM_ERR(EINVAL);
 757         }
 758
 759         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 760                                  sizeof(param));
 761
 762         switch (param.param) {
 763         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 764                 dev_priv->use_mi_batchbuffer_start = param.value;
 765                 break;
 766         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 767                 dev_priv->tex_lru_log_granularity = param.value;
 768                 break;
 769         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 770                 dev_priv->allow_batchbuffer = param.value;
 771                 break;
 772         default:
 773                 DRM_ERROR("unknown parameter %d\n", param.param);
 774                 return DRM_ERR(EINVAL);
 775         }
 776
 777         return 0;
 778 }
 779
 780 drm_i915_mmio_entry_t mmio_table[] = {
 781         [MMIO_REGS_PS_DEPTH_COUNT] = {
 782                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 783                 0x2350,
 784                 8
 785         }
 786 };
 787
 788 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 789
 790 static int i915_mmio(DRM_IOCTL_ARGS)
 791 {
 792         char buf[32];
 793         DRM_DEVICE;
 794         drm_i915_private_t *dev_priv = dev->dev_private;
 795         drm_i915_mmio_entry_t *e;
 796         drm_i915_mmio_t mmio;
 797         void __iomem *base;
 798         if (!dev_priv) {
 799                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 800                 return DRM_ERR(EINVAL);
 801         }
 802         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
 803                                  sizeof(mmio));
 804
 805         if (mmio.reg >= mmio_table_size)
 806                 return DRM_ERR(EINVAL);
 807
 808         e = &mmio_table[mmio.reg];
 809         base = dev_priv->mmio_map->handle + e->offset;
 810
 811         switch (mmio.read_write) {
 812                 case I915_MMIO_READ:
 813                         if (!(e->flag & I915_MMIO_MAY_READ))
 814                                 return DRM_ERR(EINVAL);
 815                         memcpy_fromio(buf, base, e->size);
 816                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 817                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 818                                 return DRM_ERR(EFAULT);
 819                         }
 820                         break;
 821
 822                 case I915_MMIO_WRITE:
 823                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 824                                 return DRM_ERR(EINVAL);
 825                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 826                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 827                                 return DRM_ERR(EFAULT);
 828                         }
 829                         memcpy_toio(base, buf, e->size);
 830                         break;
 831         }
 832         return 0;
 833 }
 834
 835 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 836 {
 837         /* i915 has 4 more counters */
 838         dev->counters += 4;
 839         dev->types[6] = _DRM_STAT_IRQ;
 840         dev->types[7] = _DRM_STAT_PRIMARY;
 841         dev->types[8] = _DRM_STAT_SECONDARY;
 842         dev->types[9] = _DRM_STAT_DMA;
 843
 844         return 0;
 845 }
 846
 847 void i915_driver_lastclose(drm_device_t * dev)
 848 {
 849         if (dev->dev_private) {
 850                 drm_i915_private_t *dev_priv = dev->dev_private;
 851                 i915_mem_takedown(&(dev_priv->agp_heap));
 852         }
 853         i915_dma_cleanup(dev);
 854 }
 855
 856 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
 857 {
 858         if (dev->dev_private) {
 859                 drm_i915_private_t *dev_priv = dev->dev_private;
 860                 if (dev_priv->page_flipping) {
 861                         i915_do_cleanup_pageflip(dev);
 862                 }
 863                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 864         }
 865 }
 866
 867 drm_ioctl_desc_t i915_ioctls[] = {
 868         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 869         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 870         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 871         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 872         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 873         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 874         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 875         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 876         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 877         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 878         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 879         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 880         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 881         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 882         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 883         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 884         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 885 };
 886
 887 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 888
 889 /**
 890  * Determine if the device really is AGP or not.
 891  *
 892  * All Intel graphics chipsets are treated as AGP, even if they are really
 893  * PCI-e.
 894  *
 895  * \param dev   The device to be tested.
 896  *
 897  * \returns
 898  * A value of 1 is always retured to indictate every i9x5 is AGP.
 899  */
 900 int i915_driver_device_is_agp(drm_device_t * dev)
 901 {
 902         return 1;
 903 }