shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2 || \
  38                         dev->pci_device == 0x2A02 || \
  39                         dev->pci_device == 0x2A12)
  40
  41 #define IS_G33(dev)    (dev->pci_device == 0x29C2 || \
  42                         dev->pci_device == 0x29B2 || \
  43                         dev->pci_device == 0x29D2)
  44
  45 /* Really want an OS-independent resettable timer.  Would like to have
  46  * this loop run for (eg) 3 sec, but have the timer reset every time
  47  * the head pointer changes, so that EBUSY only happens if the ring
  48  * actually stalls for (eg) 3 seconds.
  49  */
  50 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  54         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  55         int i;
  56
  57         for (i = 0; i < 10000; i++) {
  58                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  59                 ring->space = ring->head - (ring->tail + 8);
  60                 if (ring->space < 0)
  61                         ring->space += ring->Size;
  62                 if (ring->space >= n)
  63                         return 0;
  64
  65                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  66
  67                 if (ring->head != last_head)
  68                         i = 0;
  69
  70                 last_head = ring->head;
  71                 DRM_UDELAY(1);
  72         }
  73
  74         return DRM_ERR(EBUSY);
  75 }
  76
  77 void i915_kernel_lost_context(struct drm_device * dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  81
  82         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  83         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  84         ring->space = ring->head - (ring->tail + 8);
  85         if (ring->space < 0)
  86                 ring->space += ring->Size;
  87
  88         if (ring->head == ring->tail)
  89                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  90 }
  91
  92 static int i915_dma_cleanup(struct drm_device * dev)
  93 {
  94         /* Make sure interrupts are disabled here because the uninstall ioctl
  95          * may not have been called from userspace and after dev_private
  96          * is freed, it's too late.
  97          */
  98         if (dev->irq)
  99                 drm_irq_uninstall(dev);
 100
 101         if (dev->dev_private) {
 102                 drm_i915_private_t *dev_priv =
 103                     (drm_i915_private_t *) dev->dev_private;
 104
 105                 if (dev_priv->ring.virtual_start) {
 106                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 107                 }
 108
 109                 if (dev_priv->status_page_dmah) {
 110                         drm_pci_free(dev, dev_priv->status_page_dmah);
 111                         /* Need to rewrite hardware status page */
 112                         I915_WRITE(0x02080, 0x1ffff000);
 113                 }
 114                 if (dev_priv->status_gfx_addr) {
 115                         dev_priv->status_gfx_addr = 0;
 116                         drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117                         I915_WRITE(0x02080, 0x1ffff000);
 118                 }
 119                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 120                          DRM_MEM_DRIVER);
 121
 122                 dev->dev_private = NULL;
 123         }
 124
 125         return 0;
 126 }
 127
 128 static int i915_initialize(struct drm_device * dev,
 129                            drm_i915_private_t * dev_priv,
 130                            drm_i915_init_t * init)
 131 {
 132         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 133
 134         dev_priv->sarea = drm_getsarea(dev);
 135         if (!dev_priv->sarea) {
 136                 DRM_ERROR("can not find sarea!\n");
 137                 dev->dev_private = (void *)dev_priv;
 138                 i915_dma_cleanup(dev);
 139                 return DRM_ERR(EINVAL);
 140         }
 141
 142         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 143         if (!dev_priv->mmio_map) {
 144                 dev->dev_private = (void *)dev_priv;
 145                 i915_dma_cleanup(dev);
 146                 DRM_ERROR("can not find mmio map!\n");
 147                 return DRM_ERR(EINVAL);
 148         }
 149
 150         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 151             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 152
 153         dev_priv->ring.Start = init->ring_start;
 154         dev_priv->ring.End = init->ring_end;
 155         dev_priv->ring.Size = init->ring_size;
 156         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 157
 158         dev_priv->ring.map.offset = init->ring_start;
 159         dev_priv->ring.map.size = init->ring_size;
 160         dev_priv->ring.map.type = 0;
 161         dev_priv->ring.map.flags = 0;
 162         dev_priv->ring.map.mtrr = 0;
 163
 164         drm_core_ioremap(&dev_priv->ring.map, dev);
 165
 166         if (dev_priv->ring.map.handle == NULL) {
 167                 dev->dev_private = (void *)dev_priv;
 168                 i915_dma_cleanup(dev);
 169                 DRM_ERROR("can not ioremap virtual address for"
 170                           " ring buffer\n");
 171                 return DRM_ERR(ENOMEM);
 172         }
 173
 174         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 175
 176         dev_priv->cpp = init->cpp;
 177         dev_priv->sarea_priv->pf_current_page = 0;
 178
 179         /* We are using separate values as placeholders for mechanisms for
 180          * private backbuffer/depthbuffer usage.
 181          */
 182         dev_priv->use_mi_batchbuffer_start = 0;
 183
 184         /* Allow hardware batchbuffers unless told otherwise.
 185          */
 186         dev_priv->allow_batchbuffer = 1;
 187
 188         /* Enable vblank on pipe A for older X servers
 189          */
 190         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 191
 192         /* Program Hardware Status Page */
 193         if (!IS_G33(dev)) {
 194                 dev_priv->status_page_dmah =
 195                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 196
 197                 if (!dev_priv->status_page_dmah) {
 198                         dev->dev_private = (void *)dev_priv;
 199                         i915_dma_cleanup(dev);
 200                         DRM_ERROR("Can not allocate hardware status page\n");
 201                         return DRM_ERR(ENOMEM);
 202                 }
 203                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 204                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 205
 206                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 207
 208                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 209         }
 210         DRM_DEBUG("Enabled hardware status page\n");
 211         dev->dev_private = (void *)dev_priv;
 212         return 0;
 213 }
 214
 215 static int i915_dma_resume(struct drm_device * dev)
 216 {
 217         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 218
 219         DRM_DEBUG("%s\n", __FUNCTION__);
 220
 221         if (!dev_priv->sarea) {
 222                 DRM_ERROR("can not find sarea!\n");
 223                 return DRM_ERR(EINVAL);
 224         }
 225
 226         if (!dev_priv->mmio_map) {
 227                 DRM_ERROR("can not find mmio map!\n");
 228                 return DRM_ERR(EINVAL);
 229         }
 230
 231         if (dev_priv->ring.map.handle == NULL) {
 232                 DRM_ERROR("can not ioremap virtual address for"
 233                           " ring buffer\n");
 234                 return DRM_ERR(ENOMEM);
 235         }
 236
 237         /* Program Hardware Status Page */
 238         if (!dev_priv->hw_status_page) {
 239                 DRM_ERROR("Can not find hardware status page\n");
 240                 return DRM_ERR(EINVAL);
 241         }
 242         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 243
 244         if (dev_priv->status_gfx_addr != 0)
 245                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 246         else
 247                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 248         DRM_DEBUG("Enabled hardware status page\n");
 249
 250         return 0;
 251 }
 252
 253 static int i915_dma_init(DRM_IOCTL_ARGS)
 254 {
 255         DRM_DEVICE;
 256         drm_i915_private_t *dev_priv;
 257         drm_i915_init_t init;
 258         int retcode = 0;
 259
 260         DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
 261                                  sizeof(init));
 262
 263         switch (init.func) {
 264         case I915_INIT_DMA:
 265                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 266                                      DRM_MEM_DRIVER);
 267                 if (dev_priv == NULL)
 268                         return DRM_ERR(ENOMEM);
 269                 retcode = i915_initialize(dev, dev_priv, &init);
 270                 break;
 271         case I915_CLEANUP_DMA:
 272                 retcode = i915_dma_cleanup(dev);
 273                 break;
 274         case I915_RESUME_DMA:
 275                 retcode = i915_dma_resume(dev);
 276                 break;
 277         default:
 278                 retcode = DRM_ERR(EINVAL);
 279                 break;
 280         }
 281
 282         return retcode;
 283 }
 284
 285 /* Implement basically the same security restrictions as hardware does
 286  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 287  *
 288  * Most of the calculations below involve calculating the size of a
 289  * particular instruction.  It's important to get the size right as
 290  * that tells us where the next instruction to check is.  Any illegal
 291  * instruction detected will be given a size of zero, which is a
 292  * signal to abort the rest of the buffer.
 293  */
 294 static int do_validate_cmd(int cmd)
 295 {
 296         switch (((cmd >> 29) & 0x7)) {
 297         case 0x0:
 298                 switch ((cmd >> 23) & 0x3f) {
 299                 case 0x0:
 300                         return 1;       /* MI_NOOP */
 301                 case 0x4:
 302                         return 1;       /* MI_FLUSH */
 303                 default:
 304                         return 0;       /* disallow everything else */
 305                 }
 306                 break;
 307         case 0x1:
 308                 return 0;       /* reserved */
 309         case 0x2:
 310                 return (cmd & 0xff) + 2;        /* 2d commands */
 311         case 0x3:
 312                 if (((cmd >> 24) & 0x1f) <= 0x18)
 313                         return 1;
 314
 315                 switch ((cmd >> 24) & 0x1f) {
 316                 case 0x1c:
 317                         return 1;
 318                 case 0x1d:
 319                         switch ((cmd >> 16) & 0xff) {
 320                         case 0x3:
 321                                 return (cmd & 0x1f) + 2;
 322                         case 0x4:
 323                                 return (cmd & 0xf) + 2;
 324                         default:
 325                                 return (cmd & 0xffff) + 2;
 326                         }
 327                 case 0x1e:
 328                         if (cmd & (1 << 23))
 329                                 return (cmd & 0xffff) + 1;
 330                         else
 331                                 return 1;
 332                 case 0x1f:
 333                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 334                                 return (cmd & 0x1ffff) + 2;
 335                         else if (cmd & (1 << 17))       /* indirect random */
 336                                 if ((cmd & 0xffff) == 0)
 337                                         return 0;       /* unknown length, too hard */
 338                                 else
 339                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 340                         else
 341                                 return 2;       /* indirect sequential */
 342                 default:
 343                         return 0;
 344                 }
 345         default:
 346                 return 0;
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int validate_cmd(int cmd)
 353 {
 354         int ret = do_validate_cmd(cmd);
 355
 356 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 357
 358         return ret;
 359 }
 360
 361 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer, int dwords)
 362 {
 363         drm_i915_private_t *dev_priv = dev->dev_private;
 364         int i;
 365         RING_LOCALS;
 366
 367         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 368                 return DRM_ERR(EINVAL);
 369
 370         BEGIN_LP_RING((dwords+1)&~1);
 371
 372         for (i = 0; i < dwords;) {
 373                 int cmd, sz;
 374
 375                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 376                         return DRM_ERR(EINVAL);
 377
 378                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 379                         return DRM_ERR(EINVAL);
 380
 381                 OUT_RING(cmd);
 382
 383                 while (++i, --sz) {
 384                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 385                                                          sizeof(cmd))) {
 386                                 return DRM_ERR(EINVAL);
 387                         }
 388                         OUT_RING(cmd);
 389                 }
 390         }
 391
 392         if (dwords & 1)
 393                 OUT_RING(0);
 394
 395         ADVANCE_LP_RING();
 396
 397         return 0;
 398 }
 399
 400 static int i915_emit_box(struct drm_device * dev,
 401                          struct drm_clip_rect __user * boxes,
 402                          int i, int DR1, int DR4)
 403 {
 404         drm_i915_private_t *dev_priv = dev->dev_private;
 405         struct drm_clip_rect box;
 406         RING_LOCALS;
 407
 408         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 409                 return DRM_ERR(EFAULT);
 410         }
 411
 412         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 413                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 414                           box.x1, box.y1, box.x2, box.y2);
 415                 return DRM_ERR(EINVAL);
 416         }
 417
 418         if (IS_I965G(dev)) {
 419                 BEGIN_LP_RING(4);
 420                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 421                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 422                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 423                 OUT_RING(DR4);
 424                 ADVANCE_LP_RING();
 425         } else {
 426                 BEGIN_LP_RING(6);
 427                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 428                 OUT_RING(DR1);
 429                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 430                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 431                 OUT_RING(DR4);
 432                 OUT_RING(0);
 433                 ADVANCE_LP_RING();
 434         }
 435
 436         return 0;
 437 }
 438
 439 /* XXX: Emitting the counter should really be moved to part of the IRQ
 440  * emit.  For now, do it in both places:
 441  */
 442
 443 void i915_emit_breadcrumb(struct drm_device *dev)
 444 {
 445         drm_i915_private_t *dev_priv = dev->dev_private;
 446         RING_LOCALS;
 447
 448         if (++dev_priv->counter > BREADCRUMB_MASK) {
 449                  dev_priv->counter = 1;
 450                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 451         }
 452
 453         dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 454
 455         BEGIN_LP_RING(4);
 456         OUT_RING(CMD_STORE_DWORD_IDX);
 457         OUT_RING(20);
 458         OUT_RING(dev_priv->counter);
 459         OUT_RING(0);
 460         ADVANCE_LP_RING();
 461 }
 462
 463
 464 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 465 {
 466         drm_i915_private_t *dev_priv = dev->dev_private;
 467         uint32_t flush_cmd = CMD_MI_FLUSH;
 468         RING_LOCALS;
 469
 470         flush_cmd |= flush;
 471
 472         i915_kernel_lost_context(dev);
 473
 474         BEGIN_LP_RING(4);
 475         OUT_RING(flush_cmd);
 476         OUT_RING(0);
 477         OUT_RING(0);
 478         OUT_RING(0);
 479         ADVANCE_LP_RING();
 480
 481         return 0;
 482 }
 483
 484
 485 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 486                                    drm_i915_cmdbuffer_t * cmd)
 487 {
 488 #ifdef I915_HAVE_FENCE
 489         drm_i915_private_t *dev_priv = dev->dev_private;
 490 #endif
 491         int nbox = cmd->num_cliprects;
 492         int i = 0, count, ret;
 493
 494         if (cmd->sz & 0x3) {
 495                 DRM_ERROR("alignment");
 496                 return DRM_ERR(EINVAL);
 497         }
 498
 499         i915_kernel_lost_context(dev);
 500
 501         count = nbox ? nbox : 1;
 502
 503         for (i = 0; i < count; i++) {
 504                 if (i < nbox) {
 505                         ret = i915_emit_box(dev, cmd->cliprects, i,
 506                                             cmd->DR1, cmd->DR4);
 507                         if (ret)
 508                                 return ret;
 509                 }
 510
 511                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 512                 if (ret)
 513                         return ret;
 514         }
 515
 516         i915_emit_breadcrumb( dev );
 517 #ifdef I915_HAVE_FENCE
 518         drm_fence_flush_old(dev, 0, dev_priv->counter);
 519 #endif
 520         return 0;
 521 }
 522
 523 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 524                                      drm_i915_batchbuffer_t * batch)
 525 {
 526         drm_i915_private_t *dev_priv = dev->dev_private;
 527         struct drm_clip_rect __user *boxes = batch->cliprects;
 528         int nbox = batch->num_cliprects;
 529         int i = 0, count;
 530         RING_LOCALS;
 531
 532         if ((batch->start | batch->used) & 0x7) {
 533                 DRM_ERROR("alignment");
 534                 return DRM_ERR(EINVAL);
 535         }
 536
 537         i915_kernel_lost_context(dev);
 538
 539         count = nbox ? nbox : 1;
 540
 541         for (i = 0; i < count; i++) {
 542                 if (i < nbox) {
 543                         int ret = i915_emit_box(dev, boxes, i,
 544                                                 batch->DR1, batch->DR4);
 545                         if (ret)
 546                                 return ret;
 547                 }
 548
 549                 if (dev_priv->use_mi_batchbuffer_start) {
 550                         BEGIN_LP_RING(2);
 551                         OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 552                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 553                         ADVANCE_LP_RING();
 554                 } else {
 555                         BEGIN_LP_RING(4);
 556                         OUT_RING(MI_BATCH_BUFFER);
 557                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 558                         OUT_RING(batch->start + batch->used - 4);
 559                         OUT_RING(0);
 560                         ADVANCE_LP_RING();
 561                 }
 562         }
 563
 564         i915_emit_breadcrumb( dev );
 565 #ifdef I915_HAVE_FENCE
 566         drm_fence_flush_old(dev, 0, dev_priv->counter);
 567 #endif
 568         return 0;
 569 }
 570
 571 static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync)
 572 {
 573         drm_i915_private_t *dev_priv = dev->dev_private;
 574         u32 num_pages, current_page, next_page, dspbase;
 575         int shift = 2 * pipe, x, y;
 576         RING_LOCALS;
 577
 578         /* Calculate display base offset */
 579         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 580         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 581         next_page = (current_page + 1) % num_pages;
 582
 583         switch (next_page) {
 584         default:
 585         case 0:
 586                 dspbase = dev_priv->sarea_priv->front_offset;
 587                 break;
 588         case 1:
 589                 dspbase = dev_priv->sarea_priv->back_offset;
 590                 break;
 591         case 2:
 592                 dspbase = dev_priv->sarea_priv->third_offset;
 593                 break;
 594         }
 595
 596         if (pipe == 0) {
 597                 x = dev_priv->sarea_priv->pipeA_x;
 598                 y = dev_priv->sarea_priv->pipeA_y;
 599         } else {
 600                 x = dev_priv->sarea_priv->pipeB_x;
 601                 y = dev_priv->sarea_priv->pipeB_y;
 602         }
 603
 604         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 605
 606         DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page,
 607                   dspbase);
 608
 609         BEGIN_LP_RING(4);
 610         OUT_RING(sync ? 0 :
 611                  (MI_WAIT_FOR_EVENT | (pipe ? MI_WAIT_FOR_PLANE_B_FLIP :
 612                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 613         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 614                  (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 615         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 616         OUT_RING(dspbase);
 617         ADVANCE_LP_RING();
 618
 619         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 620         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 621 }
 622
 623 void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync)
 624 {
 625         drm_i915_private_t *dev_priv = dev->dev_private;
 626         int i;
 627
 628         DRM_DEBUG("%s: pipes=0x%x pfCurrentPage=%d\n",
 629                   __FUNCTION__,
 630                   pipes, dev_priv->sarea_priv->pf_current_page);
 631
 632         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 633
 634         for (i = 0; i < 2; i++)
 635                 if (pipes & (1 << i))
 636                         i915_do_dispatch_flip(dev, i, sync);
 637
 638         i915_emit_breadcrumb(dev);
 639 #ifdef I915_HAVE_FENCE
 640         if (!sync)
 641                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 642 #endif
 643 }
 644
 645 static int i915_quiescent(struct drm_device * dev)
 646 {
 647         drm_i915_private_t *dev_priv = dev->dev_private;
 648
 649         i915_kernel_lost_context(dev);
 650         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 651 }
 652
 653 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
 654 {
 655         DRM_DEVICE;
 656
 657         LOCK_TEST_WITH_RETURN(dev, filp);
 658
 659         return i915_quiescent(dev);
 660 }
 661
 662 static int i915_batchbuffer(DRM_IOCTL_ARGS)
 663 {
 664         DRM_DEVICE;
 665         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 666         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 667             dev_priv->sarea_priv;
 668         drm_i915_batchbuffer_t batch;
 669         int ret;
 670
 671         if (!dev_priv->allow_batchbuffer) {
 672                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 673                 return DRM_ERR(EINVAL);
 674         }
 675
 676         DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
 677                                  sizeof(batch));
 678
 679         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 680                   batch.start, batch.used, batch.num_cliprects);
 681
 682         LOCK_TEST_WITH_RETURN(dev, filp);
 683
 684         if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
 685                                                        batch.num_cliprects *
 686                                                        sizeof(struct drm_clip_rect)))
 687                 return DRM_ERR(EFAULT);
 688
 689         ret = i915_dispatch_batchbuffer(dev, &batch);
 690
 691         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 692         return ret;
 693 }
 694
 695 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
 696 {
 697         DRM_DEVICE;
 698         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 699         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 700             dev_priv->sarea_priv;
 701         drm_i915_cmdbuffer_t cmdbuf;
 702         int ret;
 703
 704         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
 705                                  sizeof(cmdbuf));
 706
 707         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 708                   cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
 709
 710         LOCK_TEST_WITH_RETURN(dev, filp);
 711
 712         if (cmdbuf.num_cliprects &&
 713             DRM_VERIFYAREA_READ(cmdbuf.cliprects,
 714                                 cmdbuf.num_cliprects *
 715                                 sizeof(struct drm_clip_rect))) {
 716                 DRM_ERROR("Fault accessing cliprects\n");
 717                 return DRM_ERR(EFAULT);
 718         }
 719
 720         ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
 721         if (ret) {
 722                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 723                 return ret;
 724         }
 725
 726         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 727         return 0;
 728 }
 729
 730 static int i915_do_cleanup_pageflip(struct drm_device * dev)
 731 {
 732         drm_i915_private_t *dev_priv = dev->dev_private;
 733         int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 734
 735         DRM_DEBUG("%s\n", __FUNCTION__);
 736
 737         for (i = 0, pipes = 0; i < 2; i++)
 738                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 739                         dev_priv->sarea_priv->pf_current_page =
 740                                 (dev_priv->sarea_priv->pf_current_page &
 741                                  ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
 742
 743                         pipes |= 1 << i;
 744                 }
 745
 746         if (pipes)
 747                 i915_dispatch_flip(dev, pipes, 0);
 748
 749         return 0;
 750 }
 751
 752 static int i915_flip_bufs(DRM_IOCTL_ARGS)
 753 {
 754         DRM_DEVICE;
 755         drm_i915_flip_t param;
 756
 757         DRM_DEBUG("%s\n", __FUNCTION__);
 758
 759         LOCK_TEST_WITH_RETURN(dev, filp);
 760
 761         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_flip_t __user *) data,
 762                                  sizeof(param));
 763
 764         if (param.pipes & ~0x3) {
 765                 DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n",
 766                           param.pipes);
 767                 return DRM_ERR(EINVAL);
 768         }
 769
 770         i915_dispatch_flip(dev, param.pipes, 0);
 771
 772         return 0;
 773 }
 774
 775
 776 static int i915_getparam(DRM_IOCTL_ARGS)
 777 {
 778         DRM_DEVICE;
 779         drm_i915_private_t *dev_priv = dev->dev_private;
 780         drm_i915_getparam_t param;
 781         int value;
 782
 783         if (!dev_priv) {
 784                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 785                 return DRM_ERR(EINVAL);
 786         }
 787
 788         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
 789                                  sizeof(param));
 790
 791         switch (param.param) {
 792         case I915_PARAM_IRQ_ACTIVE:
 793                 value = dev->irq ? 1 : 0;
 794                 break;
 795         case I915_PARAM_ALLOW_BATCHBUFFER:
 796                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 797                 break;
 798         case I915_PARAM_LAST_DISPATCH:
 799                 value = READ_BREADCRUMB(dev_priv);
 800                 break;
 801         default:
 802                 DRM_ERROR("Unknown parameter %d\n", param.param);
 803                 return DRM_ERR(EINVAL);
 804         }
 805
 806         if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
 807                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 808                 return DRM_ERR(EFAULT);
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int i915_setparam(DRM_IOCTL_ARGS)
 815 {
 816         DRM_DEVICE;
 817         drm_i915_private_t *dev_priv = dev->dev_private;
 818         drm_i915_setparam_t param;
 819
 820         if (!dev_priv) {
 821                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 822                 return DRM_ERR(EINVAL);
 823         }
 824
 825         DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
 826                                  sizeof(param));
 827
 828         switch (param.param) {
 829         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 830                 dev_priv->use_mi_batchbuffer_start = param.value;
 831                 break;
 832         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 833                 dev_priv->tex_lru_log_granularity = param.value;
 834                 break;
 835         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 836                 dev_priv->allow_batchbuffer = param.value;
 837                 break;
 838         default:
 839                 DRM_ERROR("unknown parameter %d\n", param.param);
 840                 return DRM_ERR(EINVAL);
 841         }
 842
 843         return 0;
 844 }
 845
 846 drm_i915_mmio_entry_t mmio_table[] = {
 847         [MMIO_REGS_PS_DEPTH_COUNT] = {
 848                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 849                 0x2350,
 850                 8
 851         }
 852 };
 853
 854 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 855
 856 static int i915_mmio(DRM_IOCTL_ARGS)
 857 {
 858         uint32_t buf[8];
 859         DRM_DEVICE;
 860         drm_i915_private_t *dev_priv = dev->dev_private;
 861         drm_i915_mmio_entry_t *e;
 862         drm_i915_mmio_t mmio;
 863         void __iomem *base;
 864         int i;
 865
 866         if (!dev_priv) {
 867                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 868                 return DRM_ERR(EINVAL);
 869         }
 870         DRM_COPY_FROM_USER_IOCTL(mmio, (drm_i915_mmio_t __user *) data,
 871                                  sizeof(mmio));
 872
 873         if (mmio.reg >= mmio_table_size)
 874                 return DRM_ERR(EINVAL);
 875
 876         e = &mmio_table[mmio.reg];
 877         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 878
 879         switch (mmio.read_write) {
 880                 case I915_MMIO_READ:
 881                         if (!(e->flag & I915_MMIO_MAY_READ))
 882                                 return DRM_ERR(EINVAL);
 883                         for (i = 0; i < e->size / 4; i++)
 884                                 buf[i] = I915_READ(e->offset + i * 4);
 885                         if (DRM_COPY_TO_USER(mmio.data, buf, e->size)) {
 886                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 887                                 return DRM_ERR(EFAULT);
 888                         }
 889                         break;
 890
 891                 case I915_MMIO_WRITE:
 892                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 893                                 return DRM_ERR(EINVAL);
 894                         if(DRM_COPY_FROM_USER(buf, mmio.data, e->size)) {
 895                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 896                                 return DRM_ERR(EFAULT);
 897                         }
 898                         for (i = 0; i < e->size / 4; i++)
 899                                 I915_WRITE(e->offset + i * 4, buf[i]);
 900                         break;
 901         }
 902         return 0;
 903 }
 904
 905 static int i915_set_status_page(DRM_IOCTL_ARGS)
 906 {
 907         DRM_DEVICE;
 908         drm_i915_private_t *dev_priv = dev->dev_private;
 909         drm_i915_hws_addr_t hws;
 910
 911         if (!dev_priv) {
 912                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 913                 return DRM_ERR(EINVAL);
 914         }
 915         DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data,
 916                         sizeof(hws));
 917         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws.addr);
 918
 919         dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
 920
 921         dev_priv->hws_map.offset = dev->agp->base + hws.addr;
 922         dev_priv->hws_map.size = 4*1024;
 923         dev_priv->hws_map.type = 0;
 924         dev_priv->hws_map.flags = 0;
 925         dev_priv->hws_map.mtrr = 0;
 926
 927         drm_core_ioremap(&dev_priv->hws_map, dev);
 928         if (dev_priv->hws_map.handle == NULL) {
 929                 dev->dev_private = (void *)dev_priv;
 930                 i915_dma_cleanup(dev);
 931                 dev_priv->status_gfx_addr = 0;
 932                 DRM_ERROR("can not ioremap virtual address for"
 933                                 " G33 hw status page\n");
 934                 return DRM_ERR(ENOMEM);
 935         }
 936         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 937
 938         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 939         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 940         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
 941                         dev_priv->status_gfx_addr);
 942         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 943         return 0;
 944 }
 945
 946 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 947 {
 948         /* i915 has 4 more counters */
 949         dev->counters += 4;
 950         dev->types[6] = _DRM_STAT_IRQ;
 951         dev->types[7] = _DRM_STAT_PRIMARY;
 952         dev->types[8] = _DRM_STAT_SECONDARY;
 953         dev->types[9] = _DRM_STAT_DMA;
 954
 955         return 0;
 956 }
 957
 958 void i915_driver_lastclose(struct drm_device * dev)
 959 {
 960         if (dev->dev_private) {
 961                 drm_i915_private_t *dev_priv = dev->dev_private;
 962                 i915_do_cleanup_pageflip(dev);
 963                 i915_mem_takedown(&(dev_priv->agp_heap));
 964         }
 965         i915_dma_cleanup(dev);
 966 }
 967
 968 void i915_driver_preclose(struct drm_device * dev, DRMFILE filp)
 969 {
 970         if (dev->dev_private) {
 971                 drm_i915_private_t *dev_priv = dev->dev_private;
 972                 i915_mem_release(dev, filp, dev_priv->agp_heap);
 973         }
 974 }
 975
 976 struct drm_ioctl_desc i915_ioctls[] = {
 977         [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 978         [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
 979         [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
 980         [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
 981         [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
 982         [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
 983         [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
 984         [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 985         [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
 986         [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
 987         [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 988         [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
 989         [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 990         [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
 991         [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
 992         [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
 993         [DRM_IOCTL_NR(DRM_I915_MMIO)] = {i915_mmio, DRM_AUTH},
 994         [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH},
 995 };
 996
 997 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 998
 999 /**
1000  * Determine if the device really is AGP or not.
1001  *
1002  * All Intel graphics chipsets are treated as AGP, even if they are really
1003  * PCI-e.
1004  *
1005  * \param dev   The device to be tested.
1006  *
1007  * \returns
1008  * A value of 1 is always retured to indictate every i9x5 is AGP.
1009  */
1010 int i915_driver_device_is_agp(struct drm_device * dev)
1011 {
1012         return 1;
1013 }
1014
1015 int i915_driver_firstopen(struct drm_device *dev)
1016 {
1017 #ifdef I915_HAVE_BUFFER
1018         drm_bo_driver_init(dev);
1019 #endif
1020         return 0;
1021 }