shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define IS_I965G(dev)  (dev->pci_device == 0x2972 || \
  35                         dev->pci_device == 0x2982 || \
  36                         dev->pci_device == 0x2992 || \
  37                         dev->pci_device == 0x29A2 || \
  38                         dev->pci_device == 0x2A02 || \
  39                         dev->pci_device == 0x2A12)
  40
  41 #define IS_G33(dev)    (dev->pci_device == 0x29C2 || \
  42                         dev->pci_device == 0x29B2 || \
  43                         dev->pci_device == 0x29D2)
  44
  45 /* Really want an OS-independent resettable timer.  Would like to have
  46  * this loop run for (eg) 3 sec, but have the timer reset every time
  47  * the head pointer changes, so that EBUSY only happens if the ring
  48  * actually stalls for (eg) 3 seconds.
  49  */
  50 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  51 {
  52         drm_i915_private_t *dev_priv = dev->dev_private;
  53         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  54         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  55         int i;
  56
  57         for (i = 0; i < 10000; i++) {
  58                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  59                 ring->space = ring->head - (ring->tail + 8);
  60                 if (ring->space < 0)
  61                         ring->space += ring->Size;
  62                 if (ring->space >= n)
  63                         return 0;
  64
  65                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  66
  67                 if (ring->head != last_head)
  68                         i = 0;
  69
  70                 last_head = ring->head;
  71                 DRM_UDELAY(1);
  72         }
  73
  74         return -EBUSY;
  75 }
  76
  77 void i915_kernel_lost_context(struct drm_device * dev)
  78 {
  79         drm_i915_private_t *dev_priv = dev->dev_private;
  80         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  81
  82         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  83         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  84         ring->space = ring->head - (ring->tail + 8);
  85         if (ring->space < 0)
  86                 ring->space += ring->Size;
  87
  88         if (ring->head == ring->tail)
  89                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  90 }
  91
  92 static int i915_dma_cleanup(struct drm_device * dev)
  93 {
  94         /* Make sure interrupts are disabled here because the uninstall ioctl
  95          * may not have been called from userspace and after dev_private
  96          * is freed, it's too late.
  97          */
  98         if (dev->irq)
  99                 drm_irq_uninstall(dev);
 100
 101         if (dev->dev_private) {
 102                 drm_i915_private_t *dev_priv =
 103                     (drm_i915_private_t *) dev->dev_private;
 104
 105                 if (dev_priv->ring.virtual_start) {
 106                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 107                 }
 108
 109                 if (dev_priv->status_page_dmah) {
 110                         drm_pci_free(dev, dev_priv->status_page_dmah);
 111                         /* Need to rewrite hardware status page */
 112                         I915_WRITE(0x02080, 0x1ffff000);
 113                 }
 114                 if (dev_priv->status_gfx_addr) {
 115                         dev_priv->status_gfx_addr = 0;
 116                         drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117                         I915_WRITE(0x02080, 0x1ffff000);
 118                 }
 119                 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
 120                          DRM_MEM_DRIVER);
 121
 122                 dev->dev_private = NULL;
 123         }
 124
 125         return 0;
 126 }
 127
 128 static int i915_initialize(struct drm_device * dev,
 129                            drm_i915_private_t * dev_priv,
 130                            drm_i915_init_t * init)
 131 {
 132         memset(dev_priv, 0, sizeof(drm_i915_private_t));
 133
 134         dev_priv->sarea = drm_getsarea(dev);
 135         if (!dev_priv->sarea) {
 136                 DRM_ERROR("can not find sarea!\n");
 137                 dev->dev_private = (void *)dev_priv;
 138                 i915_dma_cleanup(dev);
 139                 return -EINVAL;
 140         }
 141
 142         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 143         if (!dev_priv->mmio_map) {
 144                 dev->dev_private = (void *)dev_priv;
 145                 i915_dma_cleanup(dev);
 146                 DRM_ERROR("can not find mmio map!\n");
 147                 return -EINVAL;
 148         }
 149
 150         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 151             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 152
 153         dev_priv->ring.Start = init->ring_start;
 154         dev_priv->ring.End = init->ring_end;
 155         dev_priv->ring.Size = init->ring_size;
 156         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 157
 158         dev_priv->ring.map.offset = init->ring_start;
 159         dev_priv->ring.map.size = init->ring_size;
 160         dev_priv->ring.map.type = 0;
 161         dev_priv->ring.map.flags = 0;
 162         dev_priv->ring.map.mtrr = 0;
 163
 164         drm_core_ioremap(&dev_priv->ring.map, dev);
 165
 166         if (dev_priv->ring.map.handle == NULL) {
 167                 dev->dev_private = (void *)dev_priv;
 168                 i915_dma_cleanup(dev);
 169                 DRM_ERROR("can not ioremap virtual address for"
 170                           " ring buffer\n");
 171                 return -ENOMEM;
 172         }
 173
 174         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 175
 176         dev_priv->cpp = init->cpp;
 177         dev_priv->sarea_priv->pf_current_page = 0;
 178
 179         /* We are using separate values as placeholders for mechanisms for
 180          * private backbuffer/depthbuffer usage.
 181          */
 182         dev_priv->use_mi_batchbuffer_start = 0;
 183
 184         /* Allow hardware batchbuffers unless told otherwise.
 185          */
 186         dev_priv->allow_batchbuffer = 1;
 187
 188         /* Enable vblank on pipe A for older X servers
 189          */
 190         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 191
 192         /* Program Hardware Status Page */
 193         if (!IS_G33(dev)) {
 194                 dev_priv->status_page_dmah =
 195                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 196
 197                 if (!dev_priv->status_page_dmah) {
 198                         dev->dev_private = (void *)dev_priv;
 199                         i915_dma_cleanup(dev);
 200                         DRM_ERROR("Can not allocate hardware status page\n");
 201                         return -ENOMEM;
 202                 }
 203                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 204                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 205
 206                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 207
 208                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 209         }
 210         DRM_DEBUG("Enabled hardware status page\n");
 211         dev->dev_private = (void *)dev_priv;
 212         return 0;
 213 }
 214
 215 static int i915_dma_resume(struct drm_device * dev)
 216 {
 217         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 218
 219         DRM_DEBUG("%s\n", __FUNCTION__);
 220
 221         if (!dev_priv->sarea) {
 222                 DRM_ERROR("can not find sarea!\n");
 223                 return -EINVAL;
 224         }
 225
 226         if (!dev_priv->mmio_map) {
 227                 DRM_ERROR("can not find mmio map!\n");
 228                 return -EINVAL;
 229         }
 230
 231         if (dev_priv->ring.map.handle == NULL) {
 232                 DRM_ERROR("can not ioremap virtual address for"
 233                           " ring buffer\n");
 234                 return -ENOMEM;
 235         }
 236
 237         /* Program Hardware Status Page */
 238         if (!dev_priv->hw_status_page) {
 239                 DRM_ERROR("Can not find hardware status page\n");
 240                 return -EINVAL;
 241         }
 242         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 243
 244         if (dev_priv->status_gfx_addr != 0)
 245                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 246         else
 247                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 248         DRM_DEBUG("Enabled hardware status page\n");
 249
 250         return 0;
 251 }
 252
 253 static int i915_dma_init(struct drm_device *dev, void *data,
 254                          struct drm_file *file_priv)
 255 {
 256         drm_i915_private_t *dev_priv;
 257         drm_i915_init_t *init = data;
 258         int retcode = 0;
 259
 260         switch (init->func) {
 261         case I915_INIT_DMA:
 262                 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
 263                                      DRM_MEM_DRIVER);
 264                 if (dev_priv == NULL)
 265                         return -ENOMEM;
 266                 retcode = i915_initialize(dev, dev_priv, init);
 267                 break;
 268         case I915_CLEANUP_DMA:
 269                 retcode = i915_dma_cleanup(dev);
 270                 break;
 271         case I915_RESUME_DMA:
 272                 retcode = i915_dma_resume(dev);
 273                 break;
 274         default:
 275                 retcode = -EINVAL;
 276                 break;
 277         }
 278
 279         return retcode;
 280 }
 281
 282 /* Implement basically the same security restrictions as hardware does
 283  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 284  *
 285  * Most of the calculations below involve calculating the size of a
 286  * particular instruction.  It's important to get the size right as
 287  * that tells us where the next instruction to check is.  Any illegal
 288  * instruction detected will be given a size of zero, which is a
 289  * signal to abort the rest of the buffer.
 290  */
 291 static int do_validate_cmd(int cmd)
 292 {
 293         switch (((cmd >> 29) & 0x7)) {
 294         case 0x0:
 295                 switch ((cmd >> 23) & 0x3f) {
 296                 case 0x0:
 297                         return 1;       /* MI_NOOP */
 298                 case 0x4:
 299                         return 1;       /* MI_FLUSH */
 300                 default:
 301                         return 0;       /* disallow everything else */
 302                 }
 303                 break;
 304         case 0x1:
 305                 return 0;       /* reserved */
 306         case 0x2:
 307                 return (cmd & 0xff) + 2;        /* 2d commands */
 308         case 0x3:
 309                 if (((cmd >> 24) & 0x1f) <= 0x18)
 310                         return 1;
 311
 312                 switch ((cmd >> 24) & 0x1f) {
 313                 case 0x1c:
 314                         return 1;
 315                 case 0x1d:
 316                         switch ((cmd >> 16) & 0xff) {
 317                         case 0x3:
 318                                 return (cmd & 0x1f) + 2;
 319                         case 0x4:
 320                                 return (cmd & 0xf) + 2;
 321                         default:
 322                                 return (cmd & 0xffff) + 2;
 323                         }
 324                 case 0x1e:
 325                         if (cmd & (1 << 23))
 326                                 return (cmd & 0xffff) + 1;
 327                         else
 328                                 return 1;
 329                 case 0x1f:
 330                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 331                                 return (cmd & 0x1ffff) + 2;
 332                         else if (cmd & (1 << 17))       /* indirect random */
 333                                 if ((cmd & 0xffff) == 0)
 334                                         return 0;       /* unknown length, too hard */
 335                                 else
 336                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 337                         else
 338                                 return 2;       /* indirect sequential */
 339                 default:
 340                         return 0;
 341                 }
 342         default:
 343                 return 0;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int validate_cmd(int cmd)
 350 {
 351         int ret = do_validate_cmd(cmd);
 352
 353 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 354
 355         return ret;
 356 }
 357
 358 static int i915_emit_cmds(struct drm_device * dev, int __user * buffer,
 359                           int dwords)
 360 {
 361         drm_i915_private_t *dev_priv = dev->dev_private;
 362         int i;
 363         RING_LOCALS;
 364
 365         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 366                 return -EINVAL;
 367
 368         BEGIN_LP_RING((dwords+1)&~1);
 369
 370         for (i = 0; i < dwords;) {
 371                 int cmd, sz;
 372
 373                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 374                         return -EINVAL;
 375
 376                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 377                         return -EINVAL;
 378
 379                 OUT_RING(cmd);
 380
 381                 while (++i, --sz) {
 382                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 383                                                          sizeof(cmd))) {
 384                                 return -EINVAL;
 385                         }
 386                         OUT_RING(cmd);
 387                 }
 388         }
 389
 390         if (dwords & 1)
 391                 OUT_RING(0);
 392
 393         ADVANCE_LP_RING();
 394
 395         return 0;
 396 }
 397
 398 static int i915_emit_box(struct drm_device * dev,
 399                          struct drm_clip_rect __user * boxes,
 400                          int i, int DR1, int DR4)
 401 {
 402         drm_i915_private_t *dev_priv = dev->dev_private;
 403         struct drm_clip_rect box;
 404         RING_LOCALS;
 405
 406         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 407                 return -EFAULT;
 408         }
 409
 410         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 411                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 412                           box.x1, box.y1, box.x2, box.y2);
 413                 return -EINVAL;
 414         }
 415
 416         if (IS_I965G(dev)) {
 417                 BEGIN_LP_RING(4);
 418                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 419                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 420                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 421                 OUT_RING(DR4);
 422                 ADVANCE_LP_RING();
 423         } else {
 424                 BEGIN_LP_RING(6);
 425                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 426                 OUT_RING(DR1);
 427                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 428                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 429                 OUT_RING(DR4);
 430                 OUT_RING(0);
 431                 ADVANCE_LP_RING();
 432         }
 433
 434         return 0;
 435 }
 436
 437 /* XXX: Emitting the counter should really be moved to part of the IRQ
 438  * emit.  For now, do it in both places:
 439  */
 440
 441 void i915_emit_breadcrumb(struct drm_device *dev)
 442 {
 443         drm_i915_private_t *dev_priv = dev->dev_private;
 444         RING_LOCALS;
 445
 446         if (++dev_priv->counter > BREADCRUMB_MASK) {
 447                  dev_priv->counter = 1;
 448                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 449         }
 450
 451         dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 452
 453         BEGIN_LP_RING(4);
 454         OUT_RING(CMD_STORE_DWORD_IDX);
 455         OUT_RING(20);
 456         OUT_RING(dev_priv->counter);
 457         OUT_RING(0);
 458         ADVANCE_LP_RING();
 459 }
 460
 461
 462 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 463 {
 464         drm_i915_private_t *dev_priv = dev->dev_private;
 465         uint32_t flush_cmd = CMD_MI_FLUSH;
 466         RING_LOCALS;
 467
 468         flush_cmd |= flush;
 469
 470         i915_kernel_lost_context(dev);
 471
 472         BEGIN_LP_RING(4);
 473         OUT_RING(flush_cmd);
 474         OUT_RING(0);
 475         OUT_RING(0);
 476         OUT_RING(0);
 477         ADVANCE_LP_RING();
 478
 479         return 0;
 480 }
 481
 482
 483 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 484                                    drm_i915_cmdbuffer_t * cmd)
 485 {
 486 #ifdef I915_HAVE_FENCE
 487         drm_i915_private_t *dev_priv = dev->dev_private;
 488 #endif
 489         int nbox = cmd->num_cliprects;
 490         int i = 0, count, ret;
 491
 492         if (cmd->sz & 0x3) {
 493                 DRM_ERROR("alignment");
 494                 return -EINVAL;
 495         }
 496
 497         i915_kernel_lost_context(dev);
 498
 499         count = nbox ? nbox : 1;
 500
 501         for (i = 0; i < count; i++) {
 502                 if (i < nbox) {
 503                         ret = i915_emit_box(dev, cmd->cliprects, i,
 504                                             cmd->DR1, cmd->DR4);
 505                         if (ret)
 506                                 return ret;
 507                 }
 508
 509                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 510                 if (ret)
 511                         return ret;
 512         }
 513
 514         i915_emit_breadcrumb( dev );
 515 #ifdef I915_HAVE_FENCE
 516         drm_fence_flush_old(dev, 0, dev_priv->counter);
 517 #endif
 518         return 0;
 519 }
 520
 521 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 522                                      drm_i915_batchbuffer_t * batch)
 523 {
 524         drm_i915_private_t *dev_priv = dev->dev_private;
 525         struct drm_clip_rect __user *boxes = batch->cliprects;
 526         int nbox = batch->num_cliprects;
 527         int i = 0, count;
 528         RING_LOCALS;
 529
 530         if ((batch->start | batch->used) & 0x7) {
 531                 DRM_ERROR("alignment");
 532                 return -EINVAL;
 533         }
 534
 535         i915_kernel_lost_context(dev);
 536
 537         count = nbox ? nbox : 1;
 538
 539         for (i = 0; i < count; i++) {
 540                 if (i < nbox) {
 541                         int ret = i915_emit_box(dev, boxes, i,
 542                                                 batch->DR1, batch->DR4);
 543                         if (ret)
 544                                 return ret;
 545                 }
 546
 547                 if (dev_priv->use_mi_batchbuffer_start) {
 548                         BEGIN_LP_RING(2);
 549                         if (IS_I965G(dev)) {
 550                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 551                                 OUT_RING(batch->start);
 552                         } else {
 553                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 554                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 555                         }
 556                         ADVANCE_LP_RING();
 557
 558                 } else {
 559                         BEGIN_LP_RING(4);
 560                         OUT_RING(MI_BATCH_BUFFER);
 561                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 562                         OUT_RING(batch->start + batch->used - 4);
 563                         OUT_RING(0);
 564                         ADVANCE_LP_RING();
 565                 }
 566         }
 567
 568         i915_emit_breadcrumb( dev );
 569 #ifdef I915_HAVE_FENCE
 570         drm_fence_flush_old(dev, 0, dev_priv->counter);
 571 #endif
 572         return 0;
 573 }
 574
 575 static void i915_do_dispatch_flip(struct drm_device * dev, int pipe, int sync)
 576 {
 577         drm_i915_private_t *dev_priv = dev->dev_private;
 578         u32 num_pages, current_page, next_page, dspbase;
 579         int shift = 2 * pipe, x, y;
 580         RING_LOCALS;
 581
 582         /* Calculate display base offset */
 583         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 584         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 585         next_page = (current_page + 1) % num_pages;
 586
 587         switch (next_page) {
 588         default:
 589         case 0:
 590                 dspbase = dev_priv->sarea_priv->front_offset;
 591                 break;
 592         case 1:
 593                 dspbase = dev_priv->sarea_priv->back_offset;
 594                 break;
 595         case 2:
 596                 dspbase = dev_priv->sarea_priv->third_offset;
 597                 break;
 598         }
 599
 600         if (pipe == 0) {
 601                 x = dev_priv->sarea_priv->pipeA_x;
 602                 y = dev_priv->sarea_priv->pipeA_y;
 603         } else {
 604                 x = dev_priv->sarea_priv->pipeB_x;
 605                 y = dev_priv->sarea_priv->pipeB_y;
 606         }
 607
 608         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 609
 610         DRM_DEBUG("pipe=%d current_page=%d dspbase=0x%x\n", pipe, current_page,
 611                   dspbase);
 612
 613         BEGIN_LP_RING(4);
 614         OUT_RING(sync ? 0 :
 615                  (MI_WAIT_FOR_EVENT | (pipe ? MI_WAIT_FOR_PLANE_B_FLIP :
 616                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 617         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 618                  (pipe ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 619         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 620         OUT_RING(dspbase);
 621         ADVANCE_LP_RING();
 622
 623         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 624         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 625 }
 626
 627 void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync)
 628 {
 629         drm_i915_private_t *dev_priv = dev->dev_private;
 630         int i;
 631
 632         DRM_DEBUG("%s: pipes=0x%x pfCurrentPage=%d\n",
 633                   __FUNCTION__,
 634                   pipes, dev_priv->sarea_priv->pf_current_page);
 635
 636         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 637
 638         for (i = 0; i < 2; i++)
 639                 if (pipes & (1 << i))
 640                         i915_do_dispatch_flip(dev, i, sync);
 641
 642         i915_emit_breadcrumb(dev);
 643 #ifdef I915_HAVE_FENCE
 644         if (!sync)
 645                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 646 #endif
 647 }
 648
 649 static int i915_quiescent(struct drm_device * dev)
 650 {
 651         drm_i915_private_t *dev_priv = dev->dev_private;
 652
 653         i915_kernel_lost_context(dev);
 654         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 655 }
 656
 657 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 658                             struct drm_file *file_priv)
 659 {
 660
 661         LOCK_TEST_WITH_RETURN(dev, file_priv);
 662
 663         return i915_quiescent(dev);
 664 }
 665
 666 static int i915_batchbuffer(struct drm_device *dev, void *data,
 667                             struct drm_file *file_priv)
 668 {
 669         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 670         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 671             dev_priv->sarea_priv;
 672         drm_i915_batchbuffer_t *batch = data;
 673         int ret;
 674
 675         if (!dev_priv->allow_batchbuffer) {
 676                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 677                 return -EINVAL;
 678         }
 679
 680         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 681                   batch->start, batch->used, batch->num_cliprects);
 682
 683         LOCK_TEST_WITH_RETURN(dev, file_priv);
 684
 685         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 686                                                         batch->num_cliprects *
 687                                                         sizeof(struct drm_clip_rect)))
 688                 return -EFAULT;
 689
 690         ret = i915_dispatch_batchbuffer(dev, batch);
 691
 692         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 693         return ret;
 694 }
 695
 696 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 697                           struct drm_file *file_priv)
 698 {
 699         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 700         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 701             dev_priv->sarea_priv;
 702         drm_i915_cmdbuffer_t *cmdbuf = data;
 703         int ret;
 704
 705         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 706                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 707
 708         LOCK_TEST_WITH_RETURN(dev, file_priv);
 709
 710         if (cmdbuf->num_cliprects &&
 711             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 712                                 cmdbuf->num_cliprects *
 713                                 sizeof(struct drm_clip_rect))) {
 714                 DRM_ERROR("Fault accessing cliprects\n");
 715                 return -EFAULT;
 716         }
 717
 718         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 719         if (ret) {
 720                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 721                 return ret;
 722         }
 723
 724         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 725         return 0;
 726 }
 727
 728 static int i915_do_cleanup_pageflip(struct drm_device * dev)
 729 {
 730         drm_i915_private_t *dev_priv = dev->dev_private;
 731         int i, pipes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 732
 733         DRM_DEBUG("%s\n", __FUNCTION__);
 734
 735         for (i = 0, pipes = 0; i < 2; i++)
 736                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 737                         dev_priv->sarea_priv->pf_current_page =
 738                                 (dev_priv->sarea_priv->pf_current_page &
 739                                  ~(0x3 << (2 * i))) | (num_pages - 1) << (2 * i);
 740
 741                         pipes |= 1 << i;
 742                 }
 743
 744         if (pipes)
 745                 i915_dispatch_flip(dev, pipes, 0);
 746
 747         return 0;
 748 }
 749
 750 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 751 {
 752         drm_i915_flip_t *param = data;
 753
 754         DRM_DEBUG("%s\n", __FUNCTION__);
 755
 756         LOCK_TEST_WITH_RETURN(dev, file_priv);
 757
 758         if (param->pipes & ~0x3) {
 759                 DRM_ERROR("Invalid pipes 0x%x, only <= 0x3 is valid\n",
 760                           param->pipes);
 761                 return -EINVAL;
 762         }
 763
 764         i915_dispatch_flip(dev, param->pipes, 0);
 765
 766         return 0;
 767 }
 768
 769
 770 static int i915_getparam(struct drm_device *dev, void *data,
 771                          struct drm_file *file_priv)
 772 {
 773         drm_i915_private_t *dev_priv = dev->dev_private;
 774         drm_i915_getparam_t *param = data;
 775         int value;
 776
 777         if (!dev_priv) {
 778                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 779                 return -EINVAL;
 780         }
 781
 782         switch (param->param) {
 783         case I915_PARAM_IRQ_ACTIVE:
 784                 value = dev->irq ? 1 : 0;
 785                 break;
 786         case I915_PARAM_ALLOW_BATCHBUFFER:
 787                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 788                 break;
 789         case I915_PARAM_LAST_DISPATCH:
 790                 value = READ_BREADCRUMB(dev_priv);
 791                 break;
 792         default:
 793                 DRM_ERROR("Unknown parameter %d\n", param->param);
 794                 return -EINVAL;
 795         }
 796
 797         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 798                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 799                 return -EFAULT;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static int i915_setparam(struct drm_device *dev, void *data,
 806                          struct drm_file *file_priv)
 807 {
 808         drm_i915_private_t *dev_priv = dev->dev_private;
 809         drm_i915_setparam_t *param = data;
 810
 811         if (!dev_priv) {
 812                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 813                 return -EINVAL;
 814         }
 815
 816         switch (param->param) {
 817         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 818                 dev_priv->use_mi_batchbuffer_start = param->value;
 819                 break;
 820         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 821                 dev_priv->tex_lru_log_granularity = param->value;
 822                 break;
 823         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 824                 dev_priv->allow_batchbuffer = param->value;
 825                 break;
 826         default:
 827                 DRM_ERROR("unknown parameter %d\n", param->param);
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 drm_i915_mmio_entry_t mmio_table[] = {
 835         [MMIO_REGS_PS_DEPTH_COUNT] = {
 836                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 837                 0x2350,
 838                 8
 839         }
 840 };
 841
 842 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 843
 844 static int i915_mmio(struct drm_device *dev, void *data,
 845                      struct drm_file *file_priv)
 846 {
 847         uint32_t buf[8];
 848         drm_i915_private_t *dev_priv = dev->dev_private;
 849         drm_i915_mmio_entry_t *e;
 850         drm_i915_mmio_t *mmio = data;
 851         void __iomem *base;
 852         int i;
 853
 854         if (!dev_priv) {
 855                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 856                 return -EINVAL;
 857         }
 858
 859         if (mmio->reg >= mmio_table_size)
 860                 return -EINVAL;
 861
 862         e = &mmio_table[mmio->reg];
 863         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 864
 865         switch (mmio->read_write) {
 866                 case I915_MMIO_READ:
 867                         if (!(e->flag & I915_MMIO_MAY_READ))
 868                                 return -EINVAL;
 869                         for (i = 0; i < e->size / 4; i++)
 870                                 buf[i] = I915_READ(e->offset + i * 4);
 871                         if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 872                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 873                                 return -EFAULT;
 874                         }
 875                         break;
 876
 877                 case I915_MMIO_WRITE:
 878                         if (!(e->flag & I915_MMIO_MAY_WRITE))
 879                                 return -EINVAL;
 880                         if(DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 881                                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 882                                 return -EFAULT;
 883                         }
 884                         for (i = 0; i < e->size / 4; i++)
 885                                 I915_WRITE(e->offset + i * 4, buf[i]);
 886                         break;
 887         }
 888         return 0;
 889 }
 890
 891 static int i915_set_status_page(struct drm_device *dev, void *data,
 892                                 struct drm_file *file_priv)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         drm_i915_hws_addr_t *hws = data;
 896
 897         if (!dev_priv) {
 898                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 899                 return -EINVAL;
 900         }
 901         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 902
 903         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 904
 905         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 906         dev_priv->hws_map.size = 4*1024;
 907         dev_priv->hws_map.type = 0;
 908         dev_priv->hws_map.flags = 0;
 909         dev_priv->hws_map.mtrr = 0;
 910
 911         drm_core_ioremap(&dev_priv->hws_map, dev);
 912         if (dev_priv->hws_map.handle == NULL) {
 913                 dev->dev_private = (void *)dev_priv;
 914                 i915_dma_cleanup(dev);
 915                 dev_priv->status_gfx_addr = 0;
 916                 DRM_ERROR("can not ioremap virtual address for"
 917                                 " G33 hw status page\n");
 918                 return -ENOMEM;
 919         }
 920         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 921
 922         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 923         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 924         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
 925                         dev_priv->status_gfx_addr);
 926         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 927         return 0;
 928 }
 929
 930 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 931 {
 932         /* i915 has 4 more counters */
 933         dev->counters += 4;
 934         dev->types[6] = _DRM_STAT_IRQ;
 935         dev->types[7] = _DRM_STAT_PRIMARY;
 936         dev->types[8] = _DRM_STAT_SECONDARY;
 937         dev->types[9] = _DRM_STAT_DMA;
 938
 939         return 0;
 940 }
 941
 942 void i915_driver_lastclose(struct drm_device * dev)
 943 {
 944         if (dev->dev_private) {
 945                 drm_i915_private_t *dev_priv = dev->dev_private;
 946                 i915_do_cleanup_pageflip(dev);
 947                 i915_mem_takedown(&(dev_priv->agp_heap));
 948         }
 949         i915_dma_cleanup(dev);
 950 }
 951
 952 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 953 {
 954         if (dev->dev_private) {
 955                 drm_i915_private_t *dev_priv = dev->dev_private;
 956                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 957         }
 958 }
 959
 960 struct drm_ioctl_desc i915_ioctls[] = {
 961         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 962         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
 963         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
 964         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
 965         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
 966         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
 967         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
 968         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 969         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
 970         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
 971         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 972         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
 973         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 974         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 975         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 976         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
 977         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
 978         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
 979 };
 980
 981 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
 982
 983 /**
 984  * Determine if the device really is AGP or not.
 985  *
 986  * All Intel graphics chipsets are treated as AGP, even if they are really
 987  * PCI-e.
 988  *
 989  * \param dev   The device to be tested.
 990  *
 991  * \returns
 992  * A value of 1 is always retured to indictate every i9x5 is AGP.
 993  */
 994 int i915_driver_device_is_agp(struct drm_device * dev)
 995 {
 996         return 1;
 997 }
 998
 999 int i915_driver_firstopen(struct drm_device *dev)
1000 {
1001 #ifdef I915_HAVE_BUFFER
1002         drm_bo_driver_init(dev);
1003 #endif
1004         return 0;
1005 }