shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         struct drm_i915_private *dev_priv = dev->dev_private;
  42         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  44         u32 acthd_reg = IS_I965G(dev) ? I965REG_ACTHD : I915REG_ACTHD;
  45         u32 last_acthd = I915_READ(acthd_reg);
  46         u32 acthd;
  47         int i;
  48
  49         for (i = 0; i < 10000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 if (ring->head != last_head)
  59                         i = 0;
  60
  61                 if (acthd != last_acthd)
  62                         i = 0;
  63
  64                 last_head = ring->head;
  65                 last_acthd = acthd;
  66                 msleep_interruptible (10);
  67         }
  68
  69         return -EBUSY;
  70 }
  71
  72 #if I915_RING_VALIDATE
  73 /**
  74  * Validate the cached ring tail value
  75  *
  76  * If the X server writes to the ring and DRM doesn't
  77  * reload the head and tail pointers, it will end up writing
  78  * data to the wrong place in the ring, causing havoc.
  79  */
  80 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
  81 {
  82         struct drm_i915_private *dev_priv = dev->dev_private;
  83         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  84         u32     tail = I915_READ(LP_RING+RING_TAIL) & HEAD_ADDR;
  85         u32     head = I915_READ(LP_RING+RING_HEAD) & HEAD_ADDR;
  86
  87         if (tail != ring->tail) {
  88                 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
  89                           func, line,
  90                           ring->head, head, ring->tail, tail);
  91                 BUG_ON(1);
  92         }
  93 }
  94 #endif
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         struct drm_i915_private *dev_priv = dev->dev_private;
  99         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
 100
 101         /* we should never lose context on the ring with modesetting
 102          * as we don't expose it to userspace */
 103         if (drm_core_check_feature(dev, DRIVER_MODESET))
 104                 return;
 105
 106         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 107         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 108         ring->space = ring->head - (ring->tail + 8);
 109         if (ring->space < 0)
 110                 ring->space += ring->Size;
 111 }
 112
 113 int i915_dma_cleanup(struct drm_device * dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         if (drm_core_check_feature(dev, DRIVER_MODESET))
 118                 return 0;
 119
 120         /* Make sure interrupts are disabled here because the uninstall ioctl
 121          * may not have been called from userspace and after dev_private
 122          * is freed, it's too late.
 123          */
 124         if (dev->irq_enabled)
 125                 drm_irq_uninstall(dev);
 126
 127         if (dev_priv->ring.virtual_start) {
 128                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 129                 dev_priv->ring.virtual_start = 0;
 130                 dev_priv->ring.map.handle = 0;
 131                 dev_priv->ring.map.size = 0;
 132                 dev_priv->ring.Size = 0;
 133         }
 134
 135         if (dev_priv->status_page_dmah) {
 136                 drm_pci_free(dev, dev_priv->status_page_dmah);
 137                 dev_priv->status_page_dmah = NULL;
 138                 /* Need to rewrite hardware status page */
 139                 I915_WRITE(0x02080, 0x1ffff000);
 140         }
 141
 142         if (dev_priv->hws_agpoffset) {
 143                 dev_priv->hws_agpoffset = 0;
 144                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 145                 I915_WRITE(0x02080, 0x1ffff000);
 146         }
 147
 148         return 0;
 149 }
 150
 151 #if defined(DRI2)
 152 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 153 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 154 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 155         ((void *) ((unsigned char *) (p) +                      \
 156                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 157
 158 #define DRI2_SAREA_BLOCK_END            0x0000
 159 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 160 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 161
 162 static int
 163 setup_dri2_sarea(struct drm_device * dev,
 164                  struct drm_file *file_priv,
 165                  drm_i915_init_t * init)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         int ret;
 169         unsigned int *p, *end, *next;
 170
 171         mutex_lock(&dev->struct_mutex);
 172         dev_priv->sarea_bo =
 173                 drm_lookup_buffer_object(file_priv,
 174                                          init->sarea_handle, 1);
 175         mutex_unlock(&dev->struct_mutex);
 176
 177         if (!dev_priv->sarea_bo) {
 178                 DRM_ERROR("did not find sarea bo\n");
 179                 return -EINVAL;
 180         }
 181
 182         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 183                           dev_priv->sarea_bo->num_pages,
 184                           &dev_priv->sarea_kmap);
 185         if (ret) {
 186                 DRM_ERROR("could not map sarea bo\n");
 187                 return ret;
 188         }
 189
 190         p = dev_priv->sarea_kmap.virtual;
 191         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 192         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 193                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 194                 case DRI2_SAREA_BLOCK_LOCK:
 195                         dev->primary->master->lock.hw_lock = (void *) (p + 1);
 196                         dev->sigdata.lock = dev->primary->master->lock.hw_lock;
 197                         break;
 198                 }
 199                 next = DRI2_SAREA_BLOCK_NEXT(p);
 200                 if (next <= p || end < next) {
 201                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 202                                   next, p, end);
 203                         return -EINVAL;
 204                 }
 205                 p = next;
 206         }
 207
 208         return 0;
 209 }
 210 #endif
 211
 212 static int i915_initialize(struct drm_device * dev,
 213                            struct drm_file *file_priv,
 214                            drm_i915_init_t * init)
 215 {
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 218
 219         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 220                 if (init->mmio_offset != 0)
 221                         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 222                 if (!dev_priv->mmio_map) {
 223                         i915_dma_cleanup(dev);
 224                         DRM_ERROR("can not find mmio map!\n");
 225                         return -EINVAL;
 226                 }
 227         }
 228
 229
 230         if (init->ring_size != 0) {
 231                 dev_priv->ring.Size = init->ring_size;
 232                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 233                 dev_priv->ring.map.offset = init->ring_start;
 234                 dev_priv->ring.map.size = init->ring_size;
 235                 dev_priv->ring.map.type = 0;
 236                 dev_priv->ring.map.flags = 0;
 237                 dev_priv->ring.map.mtrr = 0;
 238                 drm_core_ioremap(&dev_priv->ring.map, dev);
 239
 240                 if (dev_priv->ring.map.handle == NULL) {
 241                         i915_dma_cleanup(dev);
 242                         DRM_ERROR("can not ioremap virtual address for"
 243                                   " ring buffer\n");
 244                         return -ENOMEM;
 245                 }
 246                 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 247         }
 248
 249         dev_priv->cpp = init->cpp;
 250         master_priv->sarea_priv->pf_current_page = 0;
 251
 252         /* We are using separate values as placeholders for mechanisms for
 253          * private backbuffer/depthbuffer usage.
 254          */
 255
 256         /* Allow hardware batchbuffers unless told otherwise.
 257          */
 258         dev_priv->allow_batchbuffer = 1;
 259
 260         /* Enable vblank on pipe A for older X servers
 261          */
 262         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 263
 264         /* Program Hardware Status Page */
 265         if (!I915_NEED_GFX_HWS(dev)) {
 266                 dev_priv->status_page_dmah =
 267                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 268
 269                 if (!dev_priv->status_page_dmah) {
 270                         i915_dma_cleanup(dev);
 271                         DRM_ERROR("Can not allocate hardware status page\n");
 272                         return -ENOMEM;
 273                 }
 274                 dev_priv->hws_vaddr = dev_priv->status_page_dmah->vaddr;
 275                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 276
 277                 memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
 278
 279                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 280         }
 281         DRM_DEBUG("Enabled hardware status page\n");
 282
 283 #ifdef DRI2
 284         if (init->func == I915_INIT_DMA2) {
 285                 int ret = setup_dri2_sarea(dev, file_priv, init);
 286                 if (ret) {
 287                         i915_dma_cleanup(dev);
 288                         DRM_ERROR("could not set up dri2 sarea\n");
 289                         return ret;
 290                 }
 291         }
 292 #endif /* DRI2 */
 293
 294         return 0;
 295 }
 296
 297 static int i915_dma_resume(struct drm_device * dev)
 298 {
 299         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 300
 301         DRM_DEBUG("\n");
 302
 303         if (drm_core_check_feature(dev, DRIVER_MODESET))
 304                 return 0;
 305
 306         if (dev_priv->ring.map.handle == NULL) {
 307                 DRM_ERROR("can not ioremap virtual address for"
 308                           " ring buffer\n");
 309                 return -ENOMEM;
 310         }
 311
 312         /* Program Hardware Status Page */
 313         if (!dev_priv->hws_vaddr) {
 314                 DRM_ERROR("Can not find hardware status page\n");
 315                 return -EINVAL;
 316         }
 317         DRM_DEBUG("hw status page @ %p\n", dev_priv->hws_vaddr);
 318
 319         if (dev_priv->hws_agpoffset != 0)
 320                 I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
 321         else
 322                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 323         DRM_DEBUG("Enabled hardware status page\n");
 324
 325         return 0;
 326 }
 327
 328 static int i915_dma_init(struct drm_device *dev, void *data,
 329                          struct drm_file *file_priv)
 330 {
 331         struct drm_i915_init *init = data;
 332         int retcode = 0;
 333
 334         switch (init->func) {
 335         case I915_INIT_DMA:
 336         case I915_INIT_DMA2:
 337                 retcode = i915_initialize(dev, file_priv, init);
 338                 break;
 339         case I915_CLEANUP_DMA:
 340                 retcode = i915_dma_cleanup(dev);
 341                 break;
 342         case I915_RESUME_DMA:
 343                 retcode = i915_dma_resume(dev);
 344                 break;
 345         default:
 346                 retcode = -EINVAL;
 347                 break;
 348         }
 349
 350         return retcode;
 351 }
 352
 353 /* Implement basically the same security restrictions as hardware does
 354  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 355  *
 356  * Most of the calculations below involve calculating the size of a
 357  * particular instruction.  It's important to get the size right as
 358  * that tells us where the next instruction to check is.  Any illegal
 359  * instruction detected will be given a size of zero, which is a
 360  * signal to abort the rest of the buffer.
 361  */
 362 static int do_validate_cmd(int cmd)
 363 {
 364         switch (((cmd >> 29) & 0x7)) {
 365         case 0x0:
 366                 switch ((cmd >> 23) & 0x3f) {
 367                 case 0x0:
 368                         return 1;       /* MI_NOOP */
 369                 case 0x4:
 370                         return 1;       /* MI_FLUSH */
 371                 default:
 372                         return 0;       /* disallow everything else */
 373                 }
 374                 break;
 375         case 0x1:
 376                 return 0;       /* reserved */
 377         case 0x2:
 378                 return (cmd & 0xff) + 2;        /* 2d commands */
 379         case 0x3:
 380                 if (((cmd >> 24) & 0x1f) <= 0x18)
 381                         return 1;
 382
 383                 switch ((cmd >> 24) & 0x1f) {
 384                 case 0x1c:
 385                         return 1;
 386                 case 0x1d:
 387                         switch ((cmd >> 16) & 0xff) {
 388                         case 0x3:
 389                                 return (cmd & 0x1f) + 2;
 390                         case 0x4:
 391                                 return (cmd & 0xf) + 2;
 392                         default:
 393                                 return (cmd & 0xffff) + 2;
 394                         }
 395                 case 0x1e:
 396                         if (cmd & (1 << 23))
 397                                 return (cmd & 0xffff) + 1;
 398                         else
 399                                 return 1;
 400                 case 0x1f:
 401                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 402                                 return (cmd & 0x1ffff) + 2;
 403                         else if (cmd & (1 << 17))       /* indirect random */
 404                                 if ((cmd & 0xffff) == 0)
 405                                         return 0;       /* unknown length, too hard */
 406                                 else
 407                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 408                         else
 409                                 return 2;       /* indirect sequential */
 410                 default:
 411                         return 0;
 412                 }
 413         default:
 414                 return 0;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int validate_cmd(int cmd)
 421 {
 422         int ret = do_validate_cmd(cmd);
 423
 424 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 425
 426         return ret;
 427 }
 428
 429 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 430                           int dwords)
 431 {
 432         struct drm_i915_private *dev_priv = dev->dev_private;
 433         int i;
 434         RING_LOCALS;
 435
 436         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 437                 return -EINVAL;
 438
 439         BEGIN_LP_RING((dwords+1)&~1);
 440
 441         for (i = 0; i < dwords;) {
 442                 int cmd, sz;
 443
 444                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 445                         return -EINVAL;
 446
 447                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 448                         return -EINVAL;
 449
 450                 OUT_RING(cmd);
 451
 452                 while (++i, --sz) {
 453                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 454                                                          sizeof(cmd))) {
 455                                 return -EINVAL;
 456                         }
 457                         OUT_RING(cmd);
 458                 }
 459         }
 460
 461         if (dwords & 1)
 462                 OUT_RING(0);
 463
 464         ADVANCE_LP_RING();
 465
 466         return 0;
 467 }
 468
 469 int i915_emit_box(struct drm_device * dev,
 470                   struct drm_clip_rect __user * boxes,
 471                   int i, int DR1, int DR4)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474         struct drm_clip_rect box;
 475         RING_LOCALS;
 476
 477         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 478                 return -EFAULT;
 479         }
 480
 481         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 482                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 483                           box.x1, box.y1, box.x2, box.y2);
 484                 return -EINVAL;
 485         }
 486
 487         if (IS_I965G(dev)) {
 488                 BEGIN_LP_RING(4);
 489                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 490                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 491                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 492                 OUT_RING(DR4);
 493                 ADVANCE_LP_RING();
 494         } else {
 495                 BEGIN_LP_RING(6);
 496                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 497                 OUT_RING(DR1);
 498                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 499                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 500                 OUT_RING(DR4);
 501                 OUT_RING(0);
 502                 ADVANCE_LP_RING();
 503         }
 504
 505         return 0;
 506 }
 507
 508 /* XXX: Emitting the counter should really be moved to part of the IRQ
 509  * emit. For now, do it in both places:
 510  */
 511
 512 void i915_emit_breadcrumb(struct drm_device *dev)
 513 {
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 516         RING_LOCALS;
 517
 518         if (++dev_priv->counter > BREADCRUMB_MASK) {
 519                  dev_priv->counter = 1;
 520                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 521         }
 522
 523         master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 524
 525         BEGIN_LP_RING(4);
 526         OUT_RING(MI_STORE_DWORD_INDEX);
 527         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 528         OUT_RING(dev_priv->counter);
 529         OUT_RING(0);
 530         ADVANCE_LP_RING();
 531 }
 532
 533
 534 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 535 {
 536         struct drm_i915_private *dev_priv = dev->dev_private;
 537         uint32_t flush_cmd = MI_FLUSH;
 538         RING_LOCALS;
 539
 540         flush_cmd |= flush;
 541
 542         i915_kernel_lost_context(dev);
 543
 544         BEGIN_LP_RING(4);
 545         OUT_RING(flush_cmd);
 546         OUT_RING(0);
 547         OUT_RING(0);
 548         OUT_RING(0);
 549         ADVANCE_LP_RING();
 550
 551         return 0;
 552 }
 553
 554
 555 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 556                                    struct drm_i915_cmdbuffer * cmd)
 557 {
 558         int nbox = cmd->num_cliprects;
 559         int i = 0, count, ret;
 560
 561         if (cmd->sz & 0x3) {
 562                 DRM_ERROR("alignment\n");
 563                 return -EINVAL;
 564         }
 565
 566         i915_kernel_lost_context(dev);
 567
 568         count = nbox ? nbox : 1;
 569
 570         for (i = 0; i < count; i++) {
 571                 if (i < nbox) {
 572                         ret = i915_emit_box(dev, cmd->cliprects, i,
 573                                             cmd->DR1, cmd->DR4);
 574                         if (ret)
 575                                 return ret;
 576                 }
 577
 578                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 579                 if (ret)
 580                         return ret;
 581         }
 582
 583         i915_emit_breadcrumb(dev);
 584         return 0;
 585 }
 586
 587 int i915_dispatch_batchbuffer(struct drm_device * dev,
 588                               drm_i915_batchbuffer_t * batch)
 589 {
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         struct drm_clip_rect __user *boxes = batch->cliprects;
 592         int nbox = batch->num_cliprects;
 593         int i = 0, count;
 594         RING_LOCALS;
 595
 596         if ((batch->start | batch->used) & 0x7) {
 597                 DRM_ERROR("alignment\n");
 598                 return -EINVAL;
 599         }
 600
 601         i915_kernel_lost_context(dev);
 602
 603         count = nbox ? nbox : 1;
 604
 605         for (i = 0; i < count; i++) {
 606                 if (i < nbox) {
 607                         int ret = i915_emit_box(dev, boxes, i,
 608                                                 batch->DR1, batch->DR4);
 609                         if (ret)
 610                                 return ret;
 611                 }
 612
 613                 if (IS_I830(dev) || IS_845G(dev)) {
 614                         BEGIN_LP_RING(4);
 615                         OUT_RING(MI_BATCH_BUFFER);
 616                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 617                         OUT_RING(batch->start + batch->used - 4);
 618                         OUT_RING(0);
 619                         ADVANCE_LP_RING();
 620                 } else {
 621                         BEGIN_LP_RING(2);
 622                         if (IS_I965G(dev)) {
 623                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 624                                 OUT_RING(batch->start);
 625                         } else {
 626                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 627                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 628                         }
 629                         ADVANCE_LP_RING();
 630                 }
 631         }
 632
 633         i915_emit_breadcrumb(dev);
 634         return 0;
 635 }
 636
 637 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 641         u32 num_pages, current_page, next_page, dspbase;
 642         int shift = 2 * plane, x, y;
 643         RING_LOCALS;
 644
 645         /* Calculate display base offset */
 646         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 647         current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 648         next_page = (current_page + 1) % num_pages;
 649
 650         switch (next_page) {
 651         default:
 652         case 0:
 653                 dspbase = master_priv->sarea_priv->front_offset;
 654                 break;
 655         case 1:
 656                 dspbase = master_priv->sarea_priv->back_offset;
 657                 break;
 658         case 2:
 659                 dspbase = master_priv->sarea_priv->third_offset;
 660                 break;
 661         }
 662
 663         if (plane == 0) {
 664                 x = master_priv->sarea_priv->planeA_x;
 665                 y = master_priv->sarea_priv->planeA_y;
 666         } else {
 667                 x = master_priv->sarea_priv->planeB_x;
 668                 y = master_priv->sarea_priv->planeB_y;
 669         }
 670
 671         dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 672
 673         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 674                   dspbase);
 675
 676         BEGIN_LP_RING(4);
 677         OUT_RING(sync ? 0 :
 678                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 679                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 680         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 681                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 682         OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
 683         OUT_RING(dspbase);
 684         ADVANCE_LP_RING();
 685
 686         master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 687         master_priv->sarea_priv->pf_current_page |= next_page << shift;
 688 }
 689
 690 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 691 {
 692         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 693         int i;
 694
 695         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 696                   planes, master_priv->sarea_priv->pf_current_page);
 697
 698         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 699
 700         for (i = 0; i < 2; i++)
 701                 if (planes & (1 << i))
 702                         i915_do_dispatch_flip(dev, i, sync);
 703
 704         i915_emit_breadcrumb(dev);
 705 }
 706
 707 int i915_quiescent(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         int ret;
 711
 712         i915_kernel_lost_context(dev);
 713         ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 714         if (ret)
 715         {
 716                 i915_kernel_lost_context (dev);
 717                 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
 718                            dev_priv->ring.head,
 719                            dev_priv->ring.tail,
 720                            dev_priv->ring.space);
 721         }
 722         return ret;
 723 }
 724
 725 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 726                             struct drm_file *file_priv)
 727 {
 728
 729         LOCK_TEST_WITH_RETURN(dev, file_priv);
 730
 731         return i915_quiescent(dev);
 732 }
 733
 734 static int i915_batchbuffer(struct drm_device *dev, void *data,
 735                             struct drm_file *file_priv)
 736 {
 737         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 738         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 739         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 740             master_priv->sarea_priv;
 741         drm_i915_batchbuffer_t *batch = data;
 742         int ret;
 743
 744         if (!dev_priv->allow_batchbuffer) {
 745                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 746                 return -EINVAL;
 747         }
 748
 749         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 750                   batch->start, batch->used, batch->num_cliprects);
 751
 752         LOCK_TEST_WITH_RETURN(dev, file_priv);
 753
 754         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 755                                                         batch->num_cliprects *
 756                                                         sizeof(struct drm_clip_rect)))
 757                 return -EFAULT;
 758
 759         ret = i915_dispatch_batchbuffer(dev, batch);
 760
 761         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 762         return ret;
 763 }
 764
 765 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 766                           struct drm_file *file_priv)
 767 {
 768         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 769         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 770         struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
 771                 master_priv->sarea_priv;
 772         struct drm_i915_cmdbuffer *cmdbuf = data;
 773         int ret;
 774
 775         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 776                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 777
 778         LOCK_TEST_WITH_RETURN(dev, file_priv);
 779
 780         if (cmdbuf->num_cliprects &&
 781             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 782                                 cmdbuf->num_cliprects *
 783                                 sizeof(struct drm_clip_rect))) {
 784                 DRM_ERROR("Fault accessing cliprects\n");
 785                 return -EFAULT;
 786         }
 787
 788         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 789         if (ret) {
 790                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 791                 return ret;
 792         }
 793
 794         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 795         return 0;
 796 }
 797
 798 #if defined(DRM_DEBUG_CODE)
 799 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 800 #else
 801 #define DRM_DEBUG_RELOCATION    0
 802 #endif
 803
 804 int i915_do_cleanup_pageflip(struct drm_device * dev)
 805 {
 806         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 807         int i, planes, num_pages;
 808
 809         DRM_DEBUG("\n");
 810         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 811         for (i = 0, planes = 0; i < 2; i++) {
 812                 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 813                         master_priv->sarea_priv->pf_current_page =
 814                                 (master_priv->sarea_priv->pf_current_page &
 815                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 816
 817                         planes |= 1 << i;
 818                 }
 819         }
 820
 821         if (planes)
 822                 i915_dispatch_flip(dev, planes, 0);
 823
 824         return 0;
 825 }
 826
 827 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 828 {
 829         struct drm_i915_flip *param = data;
 830
 831         DRM_DEBUG("\n");
 832
 833         LOCK_TEST_WITH_RETURN(dev, file_priv);
 834
 835         /* This is really planes */
 836         if (param->pipes & ~0x3) {
 837                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 838                           param->pipes);
 839                 return -EINVAL;
 840         }
 841
 842         i915_dispatch_flip(dev, param->pipes, 0);
 843
 844         return 0;
 845 }
 846
 847
 848 static int i915_getparam(struct drm_device *dev, void *data,
 849                          struct drm_file *file_priv)
 850 {
 851         struct drm_i915_private *dev_priv = dev->dev_private;
 852         struct drm_i915_getparam *param = data;
 853         int value;
 854
 855         if (!dev_priv) {
 856                 DRM_ERROR("called with no initialization\n");
 857                 return -EINVAL;
 858         }
 859
 860         switch (param->param) {
 861         case I915_PARAM_IRQ_ACTIVE:
 862                 value = dev->irq_enabled ? 1 : 0;
 863                 break;
 864         case I915_PARAM_ALLOW_BATCHBUFFER:
 865                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 866                 break;
 867         case I915_PARAM_LAST_DISPATCH:
 868                 value = READ_BREADCRUMB(dev_priv);
 869                 break;
 870         case I915_PARAM_CHIPSET_ID:
 871                 value = dev->pci_device;
 872                 break;
 873         default:
 874                 DRM_ERROR("Unknown parameter %d\n", param->param);
 875                 return -EINVAL;
 876         }
 877
 878         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 879                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 880                 return -EFAULT;
 881         }
 882
 883         return 0;
 884 }
 885
 886 static int i915_setparam(struct drm_device *dev, void *data,
 887                          struct drm_file *file_priv)
 888 {
 889         struct drm_i915_private *dev_priv = dev->dev_private;
 890         drm_i915_setparam_t *param = data;
 891
 892         if (!dev_priv) {
 893                 DRM_ERROR("called with no initialization\n");
 894                 return -EINVAL;
 895         }
 896
 897         switch (param->param) {
 898         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 899                 break;
 900         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 901                 dev_priv->tex_lru_log_granularity = param->value;
 902                 break;
 903         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 904                 dev_priv->allow_batchbuffer = param->value;
 905                 break;
 906         default:
 907                 DRM_ERROR("unknown parameter %d\n", param->param);
 908                 return -EINVAL;
 909         }
 910
 911         return 0;
 912 }
 913
 914 drm_i915_mmio_entry_t mmio_table[] = {
 915         [MMIO_REGS_PS_DEPTH_COUNT] = {
 916                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 917                 0x2350,
 918                 8
 919         },
 920         [MMIO_REGS_DOVSTA] = {
 921                 I915_MMIO_MAY_READ,
 922                 0x30008,
 923                 1
 924         },
 925         [MMIO_REGS_GAMMA] = {
 926                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 927                 0x30010,
 928                 6
 929         },
 930         [MMIO_REGS_FENCE] = {
 931                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 932                 0x2000,
 933                 8
 934         },
 935         [MMIO_REGS_FENCE_NEW] = {
 936                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 937                 0x3000,
 938                 16
 939         }
 940 };
 941
 942 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 943
 944 static int i915_mmio(struct drm_device *dev, void *data,
 945                      struct drm_file *file_priv)
 946 {
 947         uint32_t buf[8];
 948         struct drm_i915_private *dev_priv = dev->dev_private;
 949         drm_i915_mmio_entry_t *e;
 950         drm_i915_mmio_t *mmio = data;
 951         void __iomem *base;
 952         int i;
 953
 954         if (!dev_priv) {
 955                 DRM_ERROR("called with no initialization\n");
 956                 return -EINVAL;
 957         }
 958
 959         if (mmio->reg >= mmio_table_size)
 960                 return -EINVAL;
 961
 962         e = &mmio_table[mmio->reg];
 963         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 964
 965         switch (mmio->read_write) {
 966         case I915_MMIO_READ:
 967                 if (!(e->flag & I915_MMIO_MAY_READ))
 968                         return -EINVAL;
 969                 for (i = 0; i < e->size / 4; i++)
 970                         buf[i] = I915_READ(e->offset + i * 4);
 971                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 972                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 973                         return -EFAULT;
 974                 }
 975                 break;
 976
 977         case I915_MMIO_WRITE:
 978                 if (!(e->flag & I915_MMIO_MAY_WRITE))
 979                         return -EINVAL;
 980                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 981                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 982                         return -EFAULT;
 983                 }
 984                 for (i = 0; i < e->size / 4; i++)
 985                         I915_WRITE(e->offset + i * 4, buf[i]);
 986                 break;
 987         }
 988         return 0;
 989 }
 990
 991 static int i915_set_status_page(struct drm_device *dev, void *data,
 992                                 struct drm_file *file_priv)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         drm_i915_hws_addr_t *hws = data;
 996
 997         if (!I915_NEED_GFX_HWS(dev))
 998                 return -EINVAL;
 999
1000         if (!dev_priv) {
1001                 DRM_ERROR("called with no initialization\n");
1002                 return -EINVAL;
1003         }
1004
1005         if (drm_core_check_feature(dev, DRIVER_MODESET))
1006                 return 0;
1007
1008         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1009
1010         dev_priv->hws_agpoffset = hws->addr & (0x1ffff<<12);
1011
1012         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1013         dev_priv->hws_map.size = 4*1024;
1014         dev_priv->hws_map.type = 0;
1015         dev_priv->hws_map.flags = 0;
1016         dev_priv->hws_map.mtrr = 0;
1017
1018         drm_core_ioremap(&dev_priv->hws_map, dev);
1019         if (dev_priv->hws_map.handle == NULL) {
1020                 i915_dma_cleanup(dev);
1021                 dev_priv->hws_agpoffset = 0;
1022                 DRM_ERROR("can not ioremap virtual address for"
1023                                 " G33 hw status page\n");
1024                 return -ENOMEM;
1025         }
1026         dev_priv->hws_vaddr = dev_priv->hws_map.handle;
1027
1028         memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
1029         I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
1030         DRM_DEBUG("load hws at %p\n", dev_priv->hws_vaddr);
1031
1032         return 0;
1033 }
1034
1035 struct drm_ioctl_desc i915_ioctls[] = {
1036         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER),
1037         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1038         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1039         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1040         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1041         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1042         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1043         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER),
1044         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1045         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1046         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1047         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1048         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1049         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1050         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1051         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1052         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1053         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1054         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1055         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1056         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1057         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1058         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1059         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1060         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
1061         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
1062         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1063         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1064         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1065         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1066         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1067         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1068 };
1069
1070 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1071
1072 /**
1073  * Determine if the device really is AGP or not.
1074  *
1075  * All Intel graphics chipsets are treated as AGP, even if they are really
1076  * PCI-e.
1077  *
1078  * \param dev   The device to be tested.
1079  *
1080  * \returns
1081  * A value of 1 is always retured to indictate every i9x5 is AGP.
1082  */
1083 int i915_driver_device_is_agp(struct drm_device * dev)
1084 {
1085         return 1;
1086 }
1087