1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
41 struct drm_i915_private *dev_priv = dev->dev_private;
42 struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
44 u32 acthd_reg = IS_I965G(dev) ? I965REG_ACTHD : I915REG_ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
49 for (i = 0; i < 10000; i++) {
50 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
51 acthd = I915_READ(acthd_reg);
52 ring->space = ring->head - (ring->tail + 8);
54 ring->space += ring->Size;
58 if (ring->head != last_head)
61 if (acthd != last_acthd)
64 last_head = ring->head;
66 msleep_interruptible (10);
72 #if I915_RING_VALIDATE
74 * Validate the cached ring tail value
76 * If the X server writes to the ring and DRM doesn't
77 * reload the head and tail pointers, it will end up writing
78 * data to the wrong place in the ring, causing havoc.
80 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
82 struct drm_i915_private *dev_priv = dev->dev_private;
83 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
84 u32 tail = I915_READ(LP_RING+RING_TAIL) & HEAD_ADDR;
85 u32 head = I915_READ(LP_RING+RING_HEAD) & HEAD_ADDR;
87 if (tail != ring->tail) {
88 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
90 ring->head, head, ring->tail, tail);
96 void i915_kernel_lost_context(struct drm_device * dev)
98 struct drm_i915_private *dev_priv = dev->dev_private;
99 struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
101 /* we should never lose context on the ring with modesetting
102 * as we don't expose it to userspace */
103 if (drm_core_check_feature(dev, DRIVER_MODESET))
106 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
107 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
108 ring->space = ring->head - (ring->tail + 8);
110 ring->space += ring->Size;
113 int i915_dma_cleanup(struct drm_device * dev)
115 struct drm_i915_private *dev_priv = dev->dev_private;
117 if (drm_core_check_feature(dev, DRIVER_MODESET))
120 /* Make sure interrupts are disabled here because the uninstall ioctl
121 * may not have been called from userspace and after dev_private
122 * is freed, it's too late.
124 if (dev->irq_enabled)
125 drm_irq_uninstall(dev);
127 if (dev_priv->ring.virtual_start) {
128 drm_core_ioremapfree(&dev_priv->ring.map, dev);
129 dev_priv->ring.virtual_start = 0;
130 dev_priv->ring.map.handle = 0;
131 dev_priv->ring.map.size = 0;
132 dev_priv->ring.Size = 0;
135 if (dev_priv->status_page_dmah) {
136 drm_pci_free(dev, dev_priv->status_page_dmah);
137 dev_priv->status_page_dmah = NULL;
138 /* Need to rewrite hardware status page */
139 I915_WRITE(0x02080, 0x1ffff000);
142 if (dev_priv->hws_agpoffset) {
143 dev_priv->hws_agpoffset = 0;
144 drm_core_ioremapfree(&dev_priv->hws_map, dev);
145 I915_WRITE(0x02080, 0x1ffff000);
151 #if defined(I915_HAVE_BUFFER) && defined(DRI2)
152 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
153 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
154 #define DRI2_SAREA_BLOCK_NEXT(p) \
155 ((void *) ((unsigned char *) (p) + \
156 DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
158 #define DRI2_SAREA_BLOCK_END 0x0000
159 #define DRI2_SAREA_BLOCK_LOCK 0x0001
160 #define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002
163 setup_dri2_sarea(struct drm_device * dev,
164 struct drm_file *file_priv,
165 drm_i915_init_t * init)
167 struct drm_i915_private *dev_priv = dev->dev_private;
169 unsigned int *p, *end, *next;
171 mutex_lock(&dev->struct_mutex);
173 drm_lookup_buffer_object(file_priv,
174 init->sarea_handle, 1);
175 mutex_unlock(&dev->struct_mutex);
177 if (!dev_priv->sarea_bo) {
178 DRM_ERROR("did not find sarea bo\n");
182 ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
183 dev_priv->sarea_bo->num_pages,
184 &dev_priv->sarea_kmap);
186 DRM_ERROR("could not map sarea bo\n");
190 p = dev_priv->sarea_kmap.virtual;
191 end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
192 while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
193 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
194 case DRI2_SAREA_BLOCK_LOCK:
195 dev->primary->master->lock.hw_lock = (void *) (p + 1);
196 dev->sigdata.lock = dev->primary->master->lock.hw_lock;
199 next = DRI2_SAREA_BLOCK_NEXT(p);
200 if (next <= p || end < next) {
201 DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
212 static int i915_initialize(struct drm_device * dev,
213 struct drm_file *file_priv,
214 drm_i915_init_t * init)
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
219 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
220 if (init->mmio_offset != 0)
221 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
222 if (!dev_priv->mmio_map) {
223 i915_dma_cleanup(dev);
224 DRM_ERROR("can not find mmio map!\n");
229 #ifdef I915_HAVE_BUFFER
230 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
231 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
235 if (init->ring_size != 0) {
236 dev_priv->ring.Size = init->ring_size;
237 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
238 dev_priv->ring.map.offset = init->ring_start;
239 dev_priv->ring.map.size = init->ring_size;
240 dev_priv->ring.map.type = 0;
241 dev_priv->ring.map.flags = 0;
242 dev_priv->ring.map.mtrr = 0;
243 drm_core_ioremap(&dev_priv->ring.map, dev);
245 if (dev_priv->ring.map.handle == NULL) {
246 i915_dma_cleanup(dev);
247 DRM_ERROR("can not ioremap virtual address for"
251 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
254 dev_priv->cpp = init->cpp;
255 master_priv->sarea_priv->pf_current_page = 0;
257 /* We are using separate values as placeholders for mechanisms for
258 * private backbuffer/depthbuffer usage.
261 /* Allow hardware batchbuffers unless told otherwise.
263 dev_priv->allow_batchbuffer = 1;
265 /* Enable vblank on pipe A for older X servers
267 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
269 /* Program Hardware Status Page */
270 if (!I915_NEED_GFX_HWS(dev)) {
271 dev_priv->status_page_dmah =
272 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
274 if (!dev_priv->status_page_dmah) {
275 i915_dma_cleanup(dev);
276 DRM_ERROR("Can not allocate hardware status page\n");
279 dev_priv->hws_vaddr = dev_priv->status_page_dmah->vaddr;
280 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
282 memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
284 I915_WRITE(0x02080, dev_priv->dma_status_page);
286 DRM_DEBUG("Enabled hardware status page\n");
288 #ifdef I915_HAVE_BUFFER
289 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
290 mutex_init(&dev_priv->cmdbuf_mutex);
293 if (init->func == I915_INIT_DMA2) {
294 int ret = setup_dri2_sarea(dev, file_priv, init);
296 i915_dma_cleanup(dev);
297 DRM_ERROR("could not set up dri2 sarea\n");
302 #endif /* I915_HAVE_BUFFER */
307 static int i915_dma_resume(struct drm_device * dev)
309 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
313 if (drm_core_check_feature(dev, DRIVER_MODESET))
316 if (dev_priv->ring.map.handle == NULL) {
317 DRM_ERROR("can not ioremap virtual address for"
322 /* Program Hardware Status Page */
323 if (!dev_priv->hws_vaddr) {
324 DRM_ERROR("Can not find hardware status page\n");
327 DRM_DEBUG("hw status page @ %p\n", dev_priv->hws_vaddr);
329 if (dev_priv->hws_agpoffset != 0)
330 I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
332 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
333 DRM_DEBUG("Enabled hardware status page\n");
338 static int i915_dma_init(struct drm_device *dev, void *data,
339 struct drm_file *file_priv)
341 struct drm_i915_init *init = data;
344 switch (init->func) {
347 retcode = i915_initialize(dev, file_priv, init);
349 case I915_CLEANUP_DMA:
350 retcode = i915_dma_cleanup(dev);
352 case I915_RESUME_DMA:
353 retcode = i915_dma_resume(dev);
363 /* Implement basically the same security restrictions as hardware does
364 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
366 * Most of the calculations below involve calculating the size of a
367 * particular instruction. It's important to get the size right as
368 * that tells us where the next instruction to check is. Any illegal
369 * instruction detected will be given a size of zero, which is a
370 * signal to abort the rest of the buffer.
372 static int do_validate_cmd(int cmd)
374 switch (((cmd >> 29) & 0x7)) {
376 switch ((cmd >> 23) & 0x3f) {
378 return 1; /* MI_NOOP */
380 return 1; /* MI_FLUSH */
382 return 0; /* disallow everything else */
386 return 0; /* reserved */
388 return (cmd & 0xff) + 2; /* 2d commands */
390 if (((cmd >> 24) & 0x1f) <= 0x18)
393 switch ((cmd >> 24) & 0x1f) {
397 switch ((cmd >> 16) & 0xff) {
399 return (cmd & 0x1f) + 2;
401 return (cmd & 0xf) + 2;
403 return (cmd & 0xffff) + 2;
407 return (cmd & 0xffff) + 1;
411 if ((cmd & (1 << 23)) == 0) /* inline vertices */
412 return (cmd & 0x1ffff) + 2;
413 else if (cmd & (1 << 17)) /* indirect random */
414 if ((cmd & 0xffff) == 0)
415 return 0; /* unknown length, too hard */
417 return (((cmd & 0xffff) + 1) / 2) + 1;
419 return 2; /* indirect sequential */
430 static int validate_cmd(int cmd)
432 int ret = do_validate_cmd(cmd);
434 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
439 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
442 struct drm_i915_private *dev_priv = dev->dev_private;
446 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
449 BEGIN_LP_RING((dwords+1)&~1);
451 for (i = 0; i < dwords;) {
454 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
457 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
463 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
479 int i915_emit_box(struct drm_device * dev,
480 struct drm_clip_rect __user * boxes,
481 int i, int DR1, int DR4)
483 struct drm_i915_private *dev_priv = dev->dev_private;
484 struct drm_clip_rect box;
487 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
491 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
492 DRM_ERROR("Bad box %d,%d..%d,%d\n",
493 box.x1, box.y1, box.x2, box.y2);
499 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
500 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
501 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
506 OUT_RING(GFX_OP_DRAWRECT_INFO);
508 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
509 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
518 /* XXX: Emitting the counter should really be moved to part of the IRQ
519 * emit. For now, do it in both places:
522 void i915_emit_breadcrumb(struct drm_device *dev)
524 struct drm_i915_private *dev_priv = dev->dev_private;
525 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
528 if (++dev_priv->counter > BREADCRUMB_MASK) {
529 dev_priv->counter = 1;
530 DRM_DEBUG("Breadcrumb counter wrapped around\n");
533 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
536 OUT_RING(MI_STORE_DWORD_INDEX);
537 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
538 OUT_RING(dev_priv->counter);
544 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
546 struct drm_i915_private *dev_priv = dev->dev_private;
547 uint32_t flush_cmd = MI_FLUSH;
552 i915_kernel_lost_context(dev);
565 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
566 struct drm_i915_cmdbuffer * cmd)
568 #ifdef I915_HAVE_FENCE
569 struct drm_i915_private *dev_priv = dev->dev_private;
571 int nbox = cmd->num_cliprects;
572 int i = 0, count, ret;
575 DRM_ERROR("alignment\n");
579 i915_kernel_lost_context(dev);
581 count = nbox ? nbox : 1;
583 for (i = 0; i < count; i++) {
585 ret = i915_emit_box(dev, cmd->cliprects, i,
591 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
596 i915_emit_breadcrumb(dev);
597 #ifdef I915_HAVE_FENCE
598 if (unlikely((dev_priv->counter & 0xFF) == 0))
599 drm_fence_flush_old(dev, 0, dev_priv->counter);
604 int i915_dispatch_batchbuffer(struct drm_device * dev,
605 drm_i915_batchbuffer_t * batch)
607 struct drm_i915_private *dev_priv = dev->dev_private;
608 struct drm_clip_rect __user *boxes = batch->cliprects;
609 int nbox = batch->num_cliprects;
613 if ((batch->start | batch->used) & 0x7) {
614 DRM_ERROR("alignment\n");
618 i915_kernel_lost_context(dev);
620 count = nbox ? nbox : 1;
622 for (i = 0; i < count; i++) {
624 int ret = i915_emit_box(dev, boxes, i,
625 batch->DR1, batch->DR4);
630 if (IS_I830(dev) || IS_845G(dev)) {
632 OUT_RING(MI_BATCH_BUFFER);
633 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
634 OUT_RING(batch->start + batch->used - 4);
640 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
641 OUT_RING(batch->start);
643 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
644 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
650 i915_emit_breadcrumb(dev);
651 #ifdef I915_HAVE_FENCE
652 if (unlikely((dev_priv->counter & 0xFF) == 0))
653 drm_fence_flush_old(dev, 0, dev_priv->counter);
658 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
660 struct drm_i915_private *dev_priv = dev->dev_private;
661 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
662 u32 num_pages, current_page, next_page, dspbase;
663 int shift = 2 * plane, x, y;
666 /* Calculate display base offset */
667 num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
668 current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
669 next_page = (current_page + 1) % num_pages;
674 dspbase = master_priv->sarea_priv->front_offset;
677 dspbase = master_priv->sarea_priv->back_offset;
680 dspbase = master_priv->sarea_priv->third_offset;
685 x = master_priv->sarea_priv->planeA_x;
686 y = master_priv->sarea_priv->planeA_y;
688 x = master_priv->sarea_priv->planeB_x;
689 y = master_priv->sarea_priv->planeB_y;
692 dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
694 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
699 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
700 MI_WAIT_FOR_PLANE_A_FLIP)));
701 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
702 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
703 OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
707 master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
708 master_priv->sarea_priv->pf_current_page |= next_page << shift;
711 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
713 struct drm_i915_private *dev_priv = dev->dev_private;
714 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
717 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
718 planes, master_priv->sarea_priv->pf_current_page);
720 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
722 for (i = 0; i < 2; i++)
723 if (planes & (1 << i))
724 i915_do_dispatch_flip(dev, i, sync);
726 i915_emit_breadcrumb(dev);
727 #ifdef I915_HAVE_FENCE
728 if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
729 drm_fence_flush_old(dev, 0, dev_priv->counter);
733 int i915_quiescent(struct drm_device *dev)
735 struct drm_i915_private *dev_priv = dev->dev_private;
738 i915_kernel_lost_context(dev);
739 ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
742 i915_kernel_lost_context (dev);
743 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
746 dev_priv->ring.space);
751 static int i915_flush_ioctl(struct drm_device *dev, void *data,
752 struct drm_file *file_priv)
755 LOCK_TEST_WITH_RETURN(dev, file_priv);
757 return i915_quiescent(dev);
760 static int i915_batchbuffer(struct drm_device *dev, void *data,
761 struct drm_file *file_priv)
763 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
764 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
765 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
766 master_priv->sarea_priv;
767 drm_i915_batchbuffer_t *batch = data;
770 if (!dev_priv->allow_batchbuffer) {
771 DRM_ERROR("Batchbuffer ioctl disabled\n");
775 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
776 batch->start, batch->used, batch->num_cliprects);
778 LOCK_TEST_WITH_RETURN(dev, file_priv);
780 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
781 batch->num_cliprects *
782 sizeof(struct drm_clip_rect)))
785 ret = i915_dispatch_batchbuffer(dev, batch);
787 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
791 static int i915_cmdbuffer(struct drm_device *dev, void *data,
792 struct drm_file *file_priv)
794 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
795 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
796 struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
797 master_priv->sarea_priv;
798 struct drm_i915_cmdbuffer *cmdbuf = data;
801 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
802 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
804 LOCK_TEST_WITH_RETURN(dev, file_priv);
806 if (cmdbuf->num_cliprects &&
807 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
808 cmdbuf->num_cliprects *
809 sizeof(struct drm_clip_rect))) {
810 DRM_ERROR("Fault accessing cliprects\n");
814 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
816 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
820 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
824 #if defined(DRM_DEBUG_CODE)
825 #define DRM_DEBUG_RELOCATION (drm_debug != 0)
827 #define DRM_DEBUG_RELOCATION 0
830 int i915_do_cleanup_pageflip(struct drm_device * dev)
832 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
833 int i, planes, num_pages;
836 num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
837 for (i = 0, planes = 0; i < 2; i++) {
838 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
839 master_priv->sarea_priv->pf_current_page =
840 (master_priv->sarea_priv->pf_current_page &
841 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
848 i915_dispatch_flip(dev, planes, 0);
853 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
855 struct drm_i915_flip *param = data;
859 LOCK_TEST_WITH_RETURN(dev, file_priv);
861 /* This is really planes */
862 if (param->pipes & ~0x3) {
863 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
868 i915_dispatch_flip(dev, param->pipes, 0);
874 static int i915_getparam(struct drm_device *dev, void *data,
875 struct drm_file *file_priv)
877 struct drm_i915_private *dev_priv = dev->dev_private;
878 struct drm_i915_getparam *param = data;
882 DRM_ERROR("called with no initialization\n");
886 switch (param->param) {
887 case I915_PARAM_IRQ_ACTIVE:
888 value = dev->irq_enabled ? 1 : 0;
890 case I915_PARAM_ALLOW_BATCHBUFFER:
891 value = dev_priv->allow_batchbuffer ? 1 : 0;
893 case I915_PARAM_LAST_DISPATCH:
894 value = READ_BREADCRUMB(dev_priv);
896 case I915_PARAM_CHIPSET_ID:
897 value = dev->pci_device;
900 DRM_ERROR("Unknown parameter %d\n", param->param);
904 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
905 DRM_ERROR("DRM_COPY_TO_USER failed\n");
912 static int i915_setparam(struct drm_device *dev, void *data,
913 struct drm_file *file_priv)
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 drm_i915_setparam_t *param = data;
919 DRM_ERROR("called with no initialization\n");
923 switch (param->param) {
924 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
926 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
927 dev_priv->tex_lru_log_granularity = param->value;
929 case I915_SETPARAM_ALLOW_BATCHBUFFER:
930 dev_priv->allow_batchbuffer = param->value;
933 DRM_ERROR("unknown parameter %d\n", param->param);
940 drm_i915_mmio_entry_t mmio_table[] = {
941 [MMIO_REGS_PS_DEPTH_COUNT] = {
942 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
946 [MMIO_REGS_DOVSTA] = {
951 [MMIO_REGS_GAMMA] = {
952 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
956 [MMIO_REGS_FENCE] = {
957 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
961 [MMIO_REGS_FENCE_NEW] = {
962 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
968 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
970 static int i915_mmio(struct drm_device *dev, void *data,
971 struct drm_file *file_priv)
974 struct drm_i915_private *dev_priv = dev->dev_private;
975 drm_i915_mmio_entry_t *e;
976 drm_i915_mmio_t *mmio = data;
981 DRM_ERROR("called with no initialization\n");
985 if (mmio->reg >= mmio_table_size)
988 e = &mmio_table[mmio->reg];
989 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
991 switch (mmio->read_write) {
993 if (!(e->flag & I915_MMIO_MAY_READ))
995 for (i = 0; i < e->size / 4; i++)
996 buf[i] = I915_READ(e->offset + i * 4);
997 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
998 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1003 case I915_MMIO_WRITE:
1004 if (!(e->flag & I915_MMIO_MAY_WRITE))
1006 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
1007 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1010 for (i = 0; i < e->size / 4; i++)
1011 I915_WRITE(e->offset + i * 4, buf[i]);
1017 static int i915_set_status_page(struct drm_device *dev, void *data,
1018 struct drm_file *file_priv)
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 drm_i915_hws_addr_t *hws = data;
1023 if (!I915_NEED_GFX_HWS(dev))
1027 DRM_ERROR("called with no initialization\n");
1031 if (drm_core_check_feature(dev, DRIVER_MODESET))
1034 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1036 dev_priv->hws_agpoffset = hws->addr & (0x1ffff<<12);
1038 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1039 dev_priv->hws_map.size = 4*1024;
1040 dev_priv->hws_map.type = 0;
1041 dev_priv->hws_map.flags = 0;
1042 dev_priv->hws_map.mtrr = 0;
1044 drm_core_ioremap(&dev_priv->hws_map, dev);
1045 if (dev_priv->hws_map.handle == NULL) {
1046 i915_dma_cleanup(dev);
1047 dev_priv->hws_agpoffset = 0;
1048 DRM_ERROR("can not ioremap virtual address for"
1049 " G33 hw status page\n");
1053 dev_priv->hws_vaddr = dev_priv->hws_map.handle;
1055 memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
1056 I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
1057 DRM_DEBUG("load hws at %p\n", dev_priv->hws_vaddr);
1062 struct drm_ioctl_desc i915_ioctls[] = {
1063 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER),
1064 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1065 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1066 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1067 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1068 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1069 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1070 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER),
1071 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1072 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1073 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1074 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1075 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1076 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1077 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1078 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1079 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1080 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1081 #ifdef I915_HAVE_BUFFER
1082 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1084 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1085 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1086 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1087 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1088 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1089 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1090 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
1091 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
1092 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1093 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1094 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1095 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1096 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1097 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1100 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1103 * Determine if the device really is AGP or not.
1105 * All Intel graphics chipsets are treated as AGP, even if they are really
1108 * \param dev The device to be tested.
1111 * A value of 1 is always retured to indictate every i9x5 is AGP.
1113 int i915_driver_device_is_agp(struct drm_device * dev)