shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         struct drm_i915_private *dev_priv = dev->dev_private;
  42         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  44         int i;
  45
  46         for (i = 0; i < 10000; i++) {
  47                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  48                 ring->space = ring->head - (ring->tail + 8);
  49                 if (ring->space < 0)
  50                         ring->space += ring->Size;
  51                 if (ring->space >= n)
  52                         return 0;
  53
  54                 if (ring->head != last_head)
  55                         i = 0;
  56
  57                 last_head = ring->head;
  58                 DRM_UDELAY(1);
  59         }
  60
  61         return -EBUSY;
  62 }
  63
  64 void i915_kernel_lost_context(struct drm_device * dev)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  68
  69         /* we should never lose context on the ring with modesetting
  70          * as we don't expose it to userspace */
  71         if (drm_core_check_feature(dev, DRIVER_MODESET))
  72                 return;
  73
  74         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  75         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  76         ring->space = ring->head - (ring->tail + 8);
  77         if (ring->space < 0)
  78                 ring->space += ring->Size;
  79 }
  80
  81 int i915_dma_cleanup(struct drm_device * dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84
  85         if (drm_core_check_feature(dev, DRIVER_MODESET))
  86                 return 0;
  87
  88         /* Make sure interrupts are disabled here because the uninstall ioctl
  89          * may not have been called from userspace and after dev_private
  90          * is freed, it's too late.
  91          */
  92         if (dev->irq)
  93                 drm_irq_uninstall(dev);
  94
  95         if (dev_priv->ring.virtual_start) {
  96                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
  97                 dev_priv->ring.virtual_start = 0;
  98                 dev_priv->ring.map.handle = 0;
  99                 dev_priv->ring.map.size = 0;
 100                 dev_priv->ring.Size = 0;
 101         }
 102
 103         if (dev_priv->status_page_dmah) {
 104                 drm_pci_free(dev, dev_priv->status_page_dmah);
 105                 dev_priv->status_page_dmah = NULL;
 106                 /* Need to rewrite hardware status page */
 107                 I915_WRITE(0x02080, 0x1ffff000);
 108         }
 109
 110         if (dev_priv->status_gfx_addr) {
 111                 dev_priv->status_gfx_addr = 0;
 112                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 113                 I915_WRITE(0x02080, 0x1ffff000);
 114         }
 115
 116
 117         return 0;
 118 }
 119
 120
 121 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 122 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 123 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 124         ((void *) ((unsigned char *) (p) +                      \
 125                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 126
 127 #define DRI2_SAREA_BLOCK_END            0x0000
 128 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 129 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 130
 131 static int
 132 setup_dri2_sarea(struct drm_device * dev,
 133                  struct drm_file *file_priv,
 134                  drm_i915_init_t * init)
 135 {
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         int ret;
 138         unsigned int *p, *end, *next;
 139
 140         mutex_lock(&dev->struct_mutex);
 141         dev_priv->sarea_bo =
 142                 drm_lookup_buffer_object(file_priv,
 143                                          init->sarea_handle, 1);
 144         mutex_unlock(&dev->struct_mutex);
 145
 146         if (!dev_priv->sarea_bo) {
 147                 DRM_ERROR("did not find sarea bo\n");
 148                 return -EINVAL;
 149         }
 150
 151         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 152                           dev_priv->sarea_bo->num_pages,
 153                           &dev_priv->sarea_kmap);
 154         if (ret) {
 155                 DRM_ERROR("could not map sarea bo\n");
 156                 return ret;
 157         }
 158
 159         p = dev_priv->sarea_kmap.virtual;
 160         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 161         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 162                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 163                 case DRI2_SAREA_BLOCK_LOCK:
 164                         dev->primary->master->lock.hw_lock = (void *) (p + 1);
 165                         dev->sigdata.lock = dev->primary->master->lock.hw_lock;
 166                         break;
 167                 }
 168                 next = DRI2_SAREA_BLOCK_NEXT(p);
 169                 if (next <= p || end < next) {
 170                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 171                                   next, p, end);
 172                         return -EINVAL;
 173                 }
 174                 p = next;
 175         }
 176
 177         return 0;
 178 }
 179
 180
 181 static int i915_initialize(struct drm_device * dev,
 182                            struct drm_file *file_priv,
 183                            drm_i915_init_t * init)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 187
 188         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 189                 if (init->mmio_offset != 0)
 190                         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 191                 if (!dev_priv->mmio_map) {
 192                         i915_dma_cleanup(dev);
 193                         DRM_ERROR("can not find mmio map!\n");
 194                         return -EINVAL;
 195                 }
 196         }
 197
 198
 199 #ifdef I915_HAVE_BUFFER
 200         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 201                 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 202         }
 203 #endif
 204
 205         if (!dev_priv->ring.Size) {
 206                 dev_priv->ring.Start = init->ring_start;
 207                 dev_priv->ring.End = init->ring_end;
 208                 dev_priv->ring.Size = init->ring_size;
 209                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 210
 211                 dev_priv->ring.map.offset = init->ring_start;
 212                 dev_priv->ring.map.size = init->ring_size;
 213                 dev_priv->ring.map.type = 0;
 214                 dev_priv->ring.map.flags = 0;
 215                 dev_priv->ring.map.mtrr = 0;
 216
 217                 drm_core_ioremap(&dev_priv->ring.map, dev);
 218
 219                 if (dev_priv->ring.map.handle == NULL) {
 220                         i915_dma_cleanup(dev);
 221                         DRM_ERROR("can not ioremap virtual address for"
 222                                   " ring buffer\n");
 223                         return -ENOMEM;
 224                 }
 225                 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 226         }
 227
 228
 229         dev_priv->cpp = init->cpp;
 230         master_priv->sarea_priv->pf_current_page = 0;
 231
 232         /* We are using separate values as placeholders for mechanisms for
 233          * private backbuffer/depthbuffer usage.
 234          */
 235         dev_priv->use_mi_batchbuffer_start = 0;
 236         if (IS_I965G(dev)) /* 965 doesn't support older method */
 237                 dev_priv->use_mi_batchbuffer_start = 1;
 238
 239         /* Allow hardware batchbuffers unless told otherwise.
 240          */
 241         dev_priv->allow_batchbuffer = 1;
 242
 243         /* Enable vblank on pipe A for older X servers
 244          */
 245         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 246
 247         /* Program Hardware Status Page */
 248         if (!I915_NEED_GFX_HWS(dev)) {
 249                 dev_priv->status_page_dmah =
 250                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 251
 252                 if (!dev_priv->status_page_dmah) {
 253                         i915_dma_cleanup(dev);
 254                         DRM_ERROR("Can not allocate hardware status page\n");
 255                         return -ENOMEM;
 256                 }
 257                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 258                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 259
 260                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 261
 262                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 263         }
 264         DRM_DEBUG("Enabled hardware status page\n");
 265
 266 #ifdef I915_HAVE_BUFFER
 267         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 268                 mutex_init(&dev_priv->cmdbuf_mutex);
 269         }
 270 #endif
 271
 272         if (init->func == I915_INIT_DMA2) {
 273                 int ret = setup_dri2_sarea(dev, file_priv, init);
 274                 if (ret) {
 275                         i915_dma_cleanup(dev);
 276                         DRM_ERROR("could not set up dri2 sarea\n");
 277                         return ret;
 278                 }
 279         }
 280
 281         return 0;
 282 }
 283
 284 static int i915_dma_resume(struct drm_device * dev)
 285 {
 286         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 287
 288         DRM_DEBUG("\n");
 289
 290         if (drm_core_check_feature(dev, DRIVER_MODESET))
 291                 return 0;
 292
 293         if (!dev_priv->mmio_map) {
 294                 DRM_ERROR("can not find mmio map!\n");
 295                 return -EINVAL;
 296         }
 297
 298         if (dev_priv->ring.map.handle == NULL) {
 299                 DRM_ERROR("can not ioremap virtual address for"
 300                           " ring buffer\n");
 301                 return -ENOMEM;
 302         }
 303
 304         /* Program Hardware Status Page */
 305         if (!dev_priv->hw_status_page) {
 306                 DRM_ERROR("Can not find hardware status page\n");
 307                 return -EINVAL;
 308         }
 309         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 310
 311         if (dev_priv->status_gfx_addr != 0)
 312                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 313         else
 314                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 315         DRM_DEBUG("Enabled hardware status page\n");
 316
 317         return 0;
 318 }
 319
 320 static int i915_dma_init(struct drm_device *dev, void *data,
 321                          struct drm_file *file_priv)
 322 {
 323         struct drm_i915_init *init = data;
 324         int retcode = 0;
 325
 326         switch (init->func) {
 327         case I915_INIT_DMA:
 328         case I915_INIT_DMA2:
 329                 retcode = i915_initialize(dev, file_priv, init);
 330                 break;
 331         case I915_CLEANUP_DMA:
 332                 retcode = i915_dma_cleanup(dev);
 333                 break;
 334         case I915_RESUME_DMA:
 335                 retcode = i915_dma_resume(dev);
 336                 break;
 337         default:
 338                 retcode = -EINVAL;
 339                 break;
 340         }
 341
 342         return retcode;
 343 }
 344
 345 /* Implement basically the same security restrictions as hardware does
 346  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 347  *
 348  * Most of the calculations below involve calculating the size of a
 349  * particular instruction.  It's important to get the size right as
 350  * that tells us where the next instruction to check is.  Any illegal
 351  * instruction detected will be given a size of zero, which is a
 352  * signal to abort the rest of the buffer.
 353  */
 354 static int do_validate_cmd(int cmd)
 355 {
 356         switch (((cmd >> 29) & 0x7)) {
 357         case 0x0:
 358                 switch ((cmd >> 23) & 0x3f) {
 359                 case 0x0:
 360                         return 1;       /* MI_NOOP */
 361                 case 0x4:
 362                         return 1;       /* MI_FLUSH */
 363                 default:
 364                         return 0;       /* disallow everything else */
 365                 }
 366                 break;
 367         case 0x1:
 368                 return 0;       /* reserved */
 369         case 0x2:
 370                 return (cmd & 0xff) + 2;        /* 2d commands */
 371         case 0x3:
 372                 if (((cmd >> 24) & 0x1f) <= 0x18)
 373                         return 1;
 374
 375                 switch ((cmd >> 24) & 0x1f) {
 376                 case 0x1c:
 377                         return 1;
 378                 case 0x1d:
 379                         switch ((cmd >> 16) & 0xff) {
 380                         case 0x3:
 381                                 return (cmd & 0x1f) + 2;
 382                         case 0x4:
 383                                 return (cmd & 0xf) + 2;
 384                         default:
 385                                 return (cmd & 0xffff) + 2;
 386                         }
 387                 case 0x1e:
 388                         if (cmd & (1 << 23))
 389                                 return (cmd & 0xffff) + 1;
 390                         else
 391                                 return 1;
 392                 case 0x1f:
 393                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 394                                 return (cmd & 0x1ffff) + 2;
 395                         else if (cmd & (1 << 17))       /* indirect random */
 396                                 if ((cmd & 0xffff) == 0)
 397                                         return 0;       /* unknown length, too hard */
 398                                 else
 399                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 400                         else
 401                                 return 2;       /* indirect sequential */
 402                 default:
 403                         return 0;
 404                 }
 405         default:
 406                 return 0;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int validate_cmd(int cmd)
 413 {
 414         int ret = do_validate_cmd(cmd);
 415
 416 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 417
 418         return ret;
 419 }
 420
 421 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 422                           int dwords)
 423 {
 424         struct drm_i915_private *dev_priv = dev->dev_private;
 425         int i;
 426         RING_LOCALS;
 427
 428         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 429                 return -EINVAL;
 430
 431         BEGIN_LP_RING((dwords+1)&~1);
 432
 433         for (i = 0; i < dwords;) {
 434                 int cmd, sz;
 435
 436                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 437                         return -EINVAL;
 438
 439                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 440                         return -EINVAL;
 441
 442                 OUT_RING(cmd);
 443
 444                 while (++i, --sz) {
 445                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 446                                                          sizeof(cmd))) {
 447                                 return -EINVAL;
 448                         }
 449                         OUT_RING(cmd);
 450                 }
 451         }
 452
 453         if (dwords & 1)
 454                 OUT_RING(0);
 455
 456         ADVANCE_LP_RING();
 457
 458         return 0;
 459 }
 460
 461 static int i915_emit_box(struct drm_device * dev,
 462                          struct drm_clip_rect __user * boxes,
 463                          int i, int DR1, int DR4)
 464 {
 465         struct drm_i915_private *dev_priv = dev->dev_private;
 466         struct drm_clip_rect box;
 467         RING_LOCALS;
 468
 469         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 470                 return -EFAULT;
 471         }
 472
 473         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 474                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 475                           box.x1, box.y1, box.x2, box.y2);
 476                 return -EINVAL;
 477         }
 478
 479         if (IS_I965G(dev)) {
 480                 BEGIN_LP_RING(4);
 481                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 482                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 483                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 484                 OUT_RING(DR4);
 485                 ADVANCE_LP_RING();
 486         } else {
 487                 BEGIN_LP_RING(6);
 488                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 489                 OUT_RING(DR1);
 490                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 491                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 492                 OUT_RING(DR4);
 493                 OUT_RING(0);
 494                 ADVANCE_LP_RING();
 495         }
 496
 497         return 0;
 498 }
 499
 500 /* XXX: Emitting the counter should really be moved to part of the IRQ
 501  * emit. For now, do it in both places:
 502  */
 503
 504 void i915_emit_breadcrumb(struct drm_device *dev)
 505 {
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 508         RING_LOCALS;
 509
 510         if (++dev_priv->counter > BREADCRUMB_MASK) {
 511                  dev_priv->counter = 1;
 512                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 513         }
 514
 515         master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 516
 517         BEGIN_LP_RING(4);
 518         OUT_RING(CMD_STORE_DWORD_IDX);
 519         OUT_RING(20);
 520         OUT_RING(dev_priv->counter);
 521         OUT_RING(0);
 522         ADVANCE_LP_RING();
 523 }
 524
 525
 526 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 527 {
 528         struct drm_i915_private *dev_priv = dev->dev_private;
 529         uint32_t flush_cmd = CMD_MI_FLUSH;
 530         RING_LOCALS;
 531
 532         flush_cmd |= flush;
 533
 534         i915_kernel_lost_context(dev);
 535
 536         BEGIN_LP_RING(4);
 537         OUT_RING(flush_cmd);
 538         OUT_RING(0);
 539         OUT_RING(0);
 540         OUT_RING(0);
 541         ADVANCE_LP_RING();
 542
 543         return 0;
 544 }
 545
 546
 547 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 548                                    struct drm_i915_cmdbuffer * cmd)
 549 {
 550 #ifdef I915_HAVE_FENCE
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552 #endif
 553         int nbox = cmd->num_cliprects;
 554         int i = 0, count, ret;
 555
 556         if (cmd->sz & 0x3) {
 557                 DRM_ERROR("alignment\n");
 558                 return -EINVAL;
 559         }
 560
 561         i915_kernel_lost_context(dev);
 562
 563         count = nbox ? nbox : 1;
 564
 565         for (i = 0; i < count; i++) {
 566                 if (i < nbox) {
 567                         ret = i915_emit_box(dev, cmd->cliprects, i,
 568                                             cmd->DR1, cmd->DR4);
 569                         if (ret)
 570                                 return ret;
 571                 }
 572
 573                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 574                 if (ret)
 575                         return ret;
 576         }
 577
 578         i915_emit_breadcrumb(dev);
 579 #ifdef I915_HAVE_FENCE
 580         if (unlikely((dev_priv->counter & 0xFF) == 0))
 581                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 582 #endif
 583         return 0;
 584 }
 585
 586 int i915_dispatch_batchbuffer(struct drm_device * dev,
 587                               drm_i915_batchbuffer_t * batch)
 588 {
 589         struct drm_i915_private *dev_priv = dev->dev_private;
 590         struct drm_clip_rect __user *boxes = batch->cliprects;
 591         int nbox = batch->num_cliprects;
 592         int i = 0, count;
 593         RING_LOCALS;
 594
 595         if ((batch->start | batch->used) & 0x7) {
 596                 DRM_ERROR("alignment\n");
 597                 return -EINVAL;
 598         }
 599
 600         i915_kernel_lost_context(dev);
 601
 602         count = nbox ? nbox : 1;
 603
 604         for (i = 0; i < count; i++) {
 605                 if (i < nbox) {
 606                         int ret = i915_emit_box(dev, boxes, i,
 607                                                 batch->DR1, batch->DR4);
 608                         if (ret)
 609                                 return ret;
 610                 }
 611
 612                 if (dev_priv->use_mi_batchbuffer_start) {
 613                         BEGIN_LP_RING(2);
 614                         if (IS_I965G(dev)) {
 615                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 616                                 OUT_RING(batch->start);
 617                         } else {
 618                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 619                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 620                         }
 621                         ADVANCE_LP_RING();
 622
 623                 } else {
 624                         BEGIN_LP_RING(4);
 625                         OUT_RING(MI_BATCH_BUFFER);
 626                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 627                         OUT_RING(batch->start + batch->used - 4);
 628                         OUT_RING(0);
 629                         ADVANCE_LP_RING();
 630                 }
 631         }
 632
 633         i915_emit_breadcrumb(dev);
 634 #ifdef I915_HAVE_FENCE
 635         if (unlikely((dev_priv->counter & 0xFF) == 0))
 636                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 637 #endif
 638         return 0;
 639 }
 640
 641 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 642 {
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 645         u32 num_pages, current_page, next_page, dspbase;
 646         int shift = 2 * plane, x, y;
 647         RING_LOCALS;
 648
 649         /* Calculate display base offset */
 650         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 651         current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 652         next_page = (current_page + 1) % num_pages;
 653
 654         switch (next_page) {
 655         default:
 656         case 0:
 657                 dspbase = master_priv->sarea_priv->front_offset;
 658                 break;
 659         case 1:
 660                 dspbase = master_priv->sarea_priv->back_offset;
 661                 break;
 662         case 2:
 663                 dspbase = master_priv->sarea_priv->third_offset;
 664                 break;
 665         }
 666
 667         if (plane == 0) {
 668                 x = master_priv->sarea_priv->planeA_x;
 669                 y = master_priv->sarea_priv->planeA_y;
 670         } else {
 671                 x = master_priv->sarea_priv->planeB_x;
 672                 y = master_priv->sarea_priv->planeB_y;
 673         }
 674
 675         dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 676
 677         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 678                   dspbase);
 679
 680         BEGIN_LP_RING(4);
 681         OUT_RING(sync ? 0 :
 682                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 683                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 684         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 685                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 686         OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
 687         OUT_RING(dspbase);
 688         ADVANCE_LP_RING();
 689
 690         master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 691         master_priv->sarea_priv->pf_current_page |= next_page << shift;
 692 }
 693
 694 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 698         int i;
 699
 700         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 701                   planes, master_priv->sarea_priv->pf_current_page);
 702
 703         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 704
 705         for (i = 0; i < 2; i++)
 706                 if (planes & (1 << i))
 707                         i915_do_dispatch_flip(dev, i, sync);
 708
 709         i915_emit_breadcrumb(dev);
 710 #ifdef I915_HAVE_FENCE
 711         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 712                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 713 #endif
 714 }
 715
 716 int i915_quiescent(struct drm_device *dev)
 717 {
 718         struct drm_i915_private *dev_priv = dev->dev_private;
 719
 720         i915_kernel_lost_context(dev);
 721         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 722 }
 723
 724 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 725                             struct drm_file *file_priv)
 726 {
 727
 728         LOCK_TEST_WITH_RETURN(dev, file_priv);
 729
 730         return i915_quiescent(dev);
 731 }
 732
 733 static int i915_batchbuffer(struct drm_device *dev, void *data,
 734                             struct drm_file *file_priv)
 735 {
 736         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 737         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 738         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 739             master_priv->sarea_priv;
 740         drm_i915_batchbuffer_t *batch = data;
 741         int ret;
 742
 743         if (!dev_priv->allow_batchbuffer) {
 744                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 745                 return -EINVAL;
 746         }
 747
 748         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 749                   batch->start, batch->used, batch->num_cliprects);
 750
 751         LOCK_TEST_WITH_RETURN(dev, file_priv);
 752
 753         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 754                                                         batch->num_cliprects *
 755                                                         sizeof(struct drm_clip_rect)))
 756                 return -EFAULT;
 757
 758         ret = i915_dispatch_batchbuffer(dev, batch);
 759
 760         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 761         return ret;
 762 }
 763
 764 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 765                           struct drm_file *file_priv)
 766 {
 767         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 768         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 769         struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
 770                 master_priv->sarea_priv;
 771         struct drm_i915_cmdbuffer *cmdbuf = data;
 772         int ret;
 773
 774         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 775                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 776
 777         LOCK_TEST_WITH_RETURN(dev, file_priv);
 778
 779         if (cmdbuf->num_cliprects &&
 780             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 781                                 cmdbuf->num_cliprects *
 782                                 sizeof(struct drm_clip_rect))) {
 783                 DRM_ERROR("Fault accessing cliprects\n");
 784                 return -EFAULT;
 785         }
 786
 787         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 788         if (ret) {
 789                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 790                 return ret;
 791         }
 792
 793         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 794         return 0;
 795 }
 796
 797 #if DRM_DEBUG_CODE
 798 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 799 #else
 800 #define DRM_DEBUG_RELOCATION    0
 801 #endif
 802
 803 int i915_do_cleanup_pageflip(struct drm_device * dev)
 804 {
 805         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 806         int i, planes, num_pages;
 807
 808         DRM_DEBUG("\n");
 809         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 810         for (i = 0, planes = 0; i < 2; i++) {
 811                 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 812                         master_priv->sarea_priv->pf_current_page =
 813                                 (master_priv->sarea_priv->pf_current_page &
 814                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 815
 816                         planes |= 1 << i;
 817                 }
 818         }
 819
 820         if (planes)
 821                 i915_dispatch_flip(dev, planes, 0);
 822
 823         return 0;
 824 }
 825
 826 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 827 {
 828         struct drm_i915_flip *param = data;
 829
 830         DRM_DEBUG("\n");
 831
 832         LOCK_TEST_WITH_RETURN(dev, file_priv);
 833
 834         /* This is really planes */
 835         if (param->pipes & ~0x3) {
 836                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 837                           param->pipes);
 838                 return -EINVAL;
 839         }
 840
 841         i915_dispatch_flip(dev, param->pipes, 0);
 842
 843         return 0;
 844 }
 845
 846
 847 static int i915_getparam(struct drm_device *dev, void *data,
 848                          struct drm_file *file_priv)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         struct drm_i915_getparam *param = data;
 852         int value;
 853
 854         if (!dev_priv) {
 855                 DRM_ERROR("called with no initialization\n");
 856                 return -EINVAL;
 857         }
 858
 859         switch (param->param) {
 860         case I915_PARAM_IRQ_ACTIVE:
 861                 value = dev->irq ? 1 : 0;
 862                 break;
 863         case I915_PARAM_ALLOW_BATCHBUFFER:
 864                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 865                 break;
 866         case I915_PARAM_LAST_DISPATCH:
 867                 value = READ_BREADCRUMB(dev_priv);
 868                 break;
 869         case I915_PARAM_CHIPSET_ID:
 870                 value = dev->pci_device;
 871                 break;
 872         default:
 873                 DRM_ERROR("Unknown parameter %d\n", param->param);
 874                 return -EINVAL;
 875         }
 876
 877         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 878                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 879                 return -EFAULT;
 880         }
 881
 882         return 0;
 883 }
 884
 885 static int i915_setparam(struct drm_device *dev, void *data,
 886                          struct drm_file *file_priv)
 887 {
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889         drm_i915_setparam_t *param = data;
 890
 891         if (!dev_priv) {
 892                 DRM_ERROR("called with no initialization\n");
 893                 return -EINVAL;
 894         }
 895
 896         switch (param->param) {
 897         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 898                 if (!IS_I965G(dev))
 899                         dev_priv->use_mi_batchbuffer_start = param->value;
 900                 break;
 901         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 902                 dev_priv->tex_lru_log_granularity = param->value;
 903                 break;
 904         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 905                 dev_priv->allow_batchbuffer = param->value;
 906                 break;
 907         default:
 908                 DRM_ERROR("unknown parameter %d\n", param->param);
 909                 return -EINVAL;
 910         }
 911
 912         return 0;
 913 }
 914
 915 drm_i915_mmio_entry_t mmio_table[] = {
 916         [MMIO_REGS_PS_DEPTH_COUNT] = {
 917                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 918                 0x2350,
 919                 8
 920         },
 921         [MMIO_REGS_DOVSTA] = {
 922                 I915_MMIO_MAY_READ,
 923                 0x30008,
 924                 1
 925         },
 926         [MMIO_REGS_GAMMA] = {
 927                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 928                 0x30010,
 929                 6
 930         },
 931         [MMIO_REGS_FENCE] = {
 932                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 933                 0x2000,
 934                 8
 935         },
 936         [MMIO_REGS_FENCE_NEW] = {
 937                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 938                 0x3000,
 939                 16
 940         }
 941 };
 942
 943 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 944
 945 static int i915_mmio(struct drm_device *dev, void *data,
 946                      struct drm_file *file_priv)
 947 {
 948         uint32_t buf[8];
 949         struct drm_i915_private *dev_priv = dev->dev_private;
 950         drm_i915_mmio_entry_t *e;
 951         drm_i915_mmio_t *mmio = data;
 952         void __iomem *base;
 953         int i;
 954
 955         if (!dev_priv) {
 956                 DRM_ERROR("called with no initialization\n");
 957                 return -EINVAL;
 958         }
 959
 960         if (mmio->reg >= mmio_table_size)
 961                 return -EINVAL;
 962
 963         e = &mmio_table[mmio->reg];
 964         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 965
 966         switch (mmio->read_write) {
 967         case I915_MMIO_READ:
 968                 if (!(e->flag & I915_MMIO_MAY_READ))
 969                         return -EINVAL;
 970                 for (i = 0; i < e->size / 4; i++)
 971                         buf[i] = I915_READ(e->offset + i * 4);
 972                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 973                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 974                         return -EFAULT;
 975                 }
 976                 break;
 977
 978         case I915_MMIO_WRITE:
 979                 if (!(e->flag & I915_MMIO_MAY_WRITE))
 980                         return -EINVAL;
 981                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 982                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 983                         return -EFAULT;
 984                 }
 985                 for (i = 0; i < e->size / 4; i++)
 986                         I915_WRITE(e->offset + i * 4, buf[i]);
 987                 break;
 988         }
 989         return 0;
 990 }
 991
 992 static int i915_set_status_page(struct drm_device *dev, void *data,
 993                                 struct drm_file *file_priv)
 994 {
 995         struct drm_i915_private *dev_priv = dev->dev_private;
 996         drm_i915_hws_addr_t *hws = data;
 997
 998         if (!I915_NEED_GFX_HWS(dev))
 999                 return -EINVAL;
1000
1001         if (!dev_priv) {
1002                 DRM_ERROR("called with no initialization\n");
1003                 return -EINVAL;
1004         }
1005
1006         if (drm_core_check_feature(dev, DRIVER_MODESET))
1007                 return 0;
1008
1009         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1010
1011         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1012
1013         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1014         dev_priv->hws_map.size = 4*1024;
1015         dev_priv->hws_map.type = 0;
1016         dev_priv->hws_map.flags = 0;
1017         dev_priv->hws_map.mtrr = 0;
1018
1019         drm_core_ioremap(&dev_priv->hws_map, dev);
1020         if (dev_priv->hws_map.handle == NULL) {
1021                 i915_dma_cleanup(dev);
1022                 dev_priv->status_gfx_addr = 0;
1023                 DRM_ERROR("can not ioremap virtual address for"
1024                                 " G33 hw status page\n");
1025                 return -ENOMEM;
1026         }
1027         dev_priv->hw_status_page = dev_priv->hws_map.handle;
1028
1029         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1030         I915_WRITE(I915REG_HWS_PGA, dev_priv->status_gfx_addr);
1031         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1032                         dev_priv->status_gfx_addr);
1033         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1034         return 0;
1035 }
1036
1037 struct drm_ioctl_desc i915_ioctls[] = {
1038         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER),
1039         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1040         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1041         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1042         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1043         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1044         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1045         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER),
1046         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1047         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1048         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1049         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1050         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1051         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1052         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1053         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1054         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1055         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1056 #ifdef I915_HAVE_BUFFER
1057         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1058 #endif
1059 };
1060
1061 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1062
1063 /**
1064  * Determine if the device really is AGP or not.
1065  *
1066  * All Intel graphics chipsets are treated as AGP, even if they are really
1067  * PCI-e.
1068  *
1069  * \param dev   The device to be tested.
1070  *
1071  * \returns
1072  * A value of 1 is always retured to indictate every i9x5 is AGP.
1073  */
1074 int i915_driver_device_is_agp(struct drm_device * dev)
1075 {
1076         return 1;
1077 }
1078