shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  44         int i;
  45
  46         for (i = 0; i < 10000; i++) {
  47                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  48                 ring->space = ring->head - (ring->tail + 8);
  49                 if (ring->space < 0)
  50                         ring->space += ring->Size;
  51                 if (ring->space >= n)
  52                         return 0;
  53
  54                 if (ring->head != last_head)
  55                         i = 0;
  56
  57                 last_head = ring->head;
  58                 DRM_UDELAY(1);
  59         }
  60
  61         return -EBUSY;
  62 }
  63
  64 void i915_kernel_lost_context(struct drm_device * dev)
  65 {
  66         drm_i915_private_t *dev_priv = dev->dev_private;
  67         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  68
  69         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  70         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  71         ring->space = ring->head - (ring->tail + 8);
  72         if (ring->space < 0)
  73                 ring->space += ring->Size;
  74 }
  75
  76 static int i915_dma_cleanup(struct drm_device * dev)
  77 {
  78         drm_i915_private_t *dev_priv = dev->dev_private;
  79         /* Make sure interrupts are disabled here because the uninstall ioctl
  80          * may not have been called from userspace and after dev_private
  81          * is freed, it's too late.
  82          */
  83         if (dev->irq)
  84                 drm_irq_uninstall(dev);
  85
  86         if (dev_priv->ring.virtual_start) {
  87                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
  88                 dev_priv->ring.virtual_start = 0;
  89                 dev_priv->ring.map.handle = 0;
  90                 dev_priv->ring.map.size = 0;
  91         }
  92
  93         if (dev_priv->status_page_dmah) {
  94                 drm_pci_free(dev, dev_priv->status_page_dmah);
  95                 dev_priv->status_page_dmah = NULL;
  96                 /* Need to rewrite hardware status page */
  97                 I915_WRITE(0x02080, 0x1ffff000);
  98         }
  99
 100         if (dev_priv->status_gfx_addr) {
 101                 dev_priv->status_gfx_addr = 0;
 102                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 103                 I915_WRITE(0x02080, 0x1ffff000);
 104         }
 105
 106         return 0;
 107 }
 108
 109 #if defined(I915_HAVE_BUFFER)
 110 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 111 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 112 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 113         ((void *) ((unsigned char *) (p) +                      \
 114                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 115
 116 #define DRI2_SAREA_BLOCK_END            0x0000
 117 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 118 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 119
 120 static int
 121 setup_dri2_sarea(struct drm_device * dev,
 122                  struct drm_file *file_priv,
 123                  drm_i915_init_t * init)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         int ret;
 127         unsigned int *p, *end, *next;
 128
 129         mutex_lock(&dev->struct_mutex);
 130         dev_priv->sarea_bo =
 131                 drm_lookup_buffer_object(file_priv,
 132                                          init->sarea_handle, 1);
 133         mutex_unlock(&dev->struct_mutex);
 134
 135         if (!dev_priv->sarea_bo) {
 136                 DRM_ERROR("did not find sarea bo\n");
 137                 return -EINVAL;
 138         }
 139
 140         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 141                           dev_priv->sarea_bo->num_pages,
 142                           &dev_priv->sarea_kmap);
 143         if (ret) {
 144                 DRM_ERROR("could not map sarea bo\n");
 145                 return ret;
 146         }
 147
 148         p = dev_priv->sarea_kmap.virtual;
 149         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 150         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 151                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 152                 case DRI2_SAREA_BLOCK_LOCK:
 153                         dev->lock.hw_lock = (void *) (p + 1);
 154                         dev->sigdata.lock = dev->lock.hw_lock;
 155                         break;
 156                 }
 157                 next = DRI2_SAREA_BLOCK_NEXT(p);
 158                 if (next <= p || end < next) {
 159                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 160                                   next, p, end);
 161                         return -EINVAL;
 162                 }
 163                 p = next;
 164         }
 165
 166         return 0;
 167 }
 168 #endif
 169
 170 static int i915_initialize(struct drm_device * dev,
 171                            struct drm_file *file_priv,
 172                            drm_i915_init_t * init)
 173 {
 174         drm_i915_private_t *dev_priv = dev->dev_private;
 175 #if defined(I915_HAVE_BUFFER)
 176         int ret;
 177 #endif
 178         dev_priv->sarea = drm_getsarea(dev);
 179         if (!dev_priv->sarea) {
 180                 DRM_ERROR("can not find sarea!\n");
 181                 i915_dma_cleanup(dev);
 182                 return -EINVAL;
 183         }
 184
 185         if (init->mmio_offset != 0)
 186                 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 187         if (!dev_priv->mmio_map) {
 188                 i915_dma_cleanup(dev);
 189                 DRM_ERROR("can not find mmio map!\n");
 190                 return -EINVAL;
 191         }
 192
 193 #ifdef I915_HAVE_BUFFER
 194         dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 195 #endif
 196
 197         if (init->sarea_priv_offset)
 198                 dev_priv->sarea_priv = (drm_i915_sarea_t *)
 199                         ((u8 *) dev_priv->sarea->handle +
 200                          init->sarea_priv_offset);
 201         else {
 202                 /* No sarea_priv for you! */
 203                 dev_priv->sarea_priv = NULL;
 204         }
 205
 206         dev_priv->ring.Start = init->ring_start;
 207         dev_priv->ring.End = init->ring_end;
 208         dev_priv->ring.Size = init->ring_size;
 209         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 210
 211         dev_priv->ring.map.offset = init->ring_start;
 212         dev_priv->ring.map.size = init->ring_size;
 213         dev_priv->ring.map.type = 0;
 214         dev_priv->ring.map.flags = 0;
 215         dev_priv->ring.map.mtrr = 0;
 216
 217         drm_core_ioremap(&dev_priv->ring.map, dev);
 218
 219         if (dev_priv->ring.map.handle == NULL) {
 220                 i915_dma_cleanup(dev);
 221                 DRM_ERROR("can not ioremap virtual address for"
 222                           " ring buffer\n");
 223                 return -ENOMEM;
 224         }
 225
 226         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 227
 228         dev_priv->cpp = init->cpp;
 229
 230         if (dev_priv->sarea_priv)
 231                 dev_priv->sarea_priv->pf_current_page = 0;
 232
 233         /* We are using separate values as placeholders for mechanisms for
 234          * private backbuffer/depthbuffer usage.
 235          */
 236         dev_priv->use_mi_batchbuffer_start = 0;
 237         if (IS_I965G(dev)) /* 965 doesn't support older method */
 238                 dev_priv->use_mi_batchbuffer_start = 1;
 239
 240         /* Allow hardware batchbuffers unless told otherwise.
 241          */
 242         dev_priv->allow_batchbuffer = 1;
 243
 244         /* Enable vblank on pipe A for older X servers
 245          */
 246         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 247
 248         /* Program Hardware Status Page */
 249         if (!I915_NEED_GFX_HWS(dev)) {
 250                 dev_priv->status_page_dmah =
 251                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 252
 253                 if (!dev_priv->status_page_dmah) {
 254                         i915_dma_cleanup(dev);
 255                         DRM_ERROR("Can not allocate hardware status page\n");
 256                         return -ENOMEM;
 257                 }
 258                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 259                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 260
 261                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 262
 263                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 264         }
 265         DRM_DEBUG("Enabled hardware status page\n");
 266 #ifdef I915_HAVE_BUFFER
 267         mutex_init(&dev_priv->cmdbuf_mutex);
 268 #endif
 269 #if defined(I915_HAVE_BUFFER)
 270         if (init->func == I915_INIT_DMA2) {
 271                 ret = setup_dri2_sarea(dev, file_priv, init);
 272                 if (ret) {
 273                         i915_dma_cleanup(dev);
 274                         DRM_ERROR("could not set up dri2 sarea\n");
 275                         return ret;
 276                 }
 277         }
 278 #endif
 279
 280         return 0;
 281 }
 282
 283 static int i915_dma_resume(struct drm_device * dev)
 284 {
 285         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 286
 287         DRM_DEBUG("\n");
 288
 289         if (!dev_priv->sarea) {
 290                 DRM_ERROR("can not find sarea!\n");
 291                 return -EINVAL;
 292         }
 293
 294         if (!dev_priv->mmio_map) {
 295                 DRM_ERROR("can not find mmio map!\n");
 296                 return -EINVAL;
 297         }
 298
 299         if (dev_priv->ring.map.handle == NULL) {
 300                 DRM_ERROR("can not ioremap virtual address for"
 301                           " ring buffer\n");
 302                 return -ENOMEM;
 303         }
 304
 305         /* Program Hardware Status Page */
 306         if (!dev_priv->hw_status_page) {
 307                 DRM_ERROR("Can not find hardware status page\n");
 308                 return -EINVAL;
 309         }
 310         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 311
 312         if (dev_priv->status_gfx_addr != 0)
 313                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 314         else
 315                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 316         DRM_DEBUG("Enabled hardware status page\n");
 317
 318         return 0;
 319 }
 320
 321 static int i915_dma_init(struct drm_device *dev, void *data,
 322                          struct drm_file *file_priv)
 323 {
 324         drm_i915_init_t *init = data;
 325         int retcode = 0;
 326
 327         switch (init->func) {
 328         case I915_INIT_DMA:
 329         case I915_INIT_DMA2:
 330                 retcode = i915_initialize(dev, file_priv, init);
 331                 break;
 332         case I915_CLEANUP_DMA:
 333                 retcode = i915_dma_cleanup(dev);
 334                 break;
 335         case I915_RESUME_DMA:
 336                 retcode = i915_dma_resume(dev);
 337                 break;
 338         default:
 339                 retcode = -EINVAL;
 340                 break;
 341         }
 342
 343         return retcode;
 344 }
 345
 346 /* Implement basically the same security restrictions as hardware does
 347  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 348  *
 349  * Most of the calculations below involve calculating the size of a
 350  * particular instruction.  It's important to get the size right as
 351  * that tells us where the next instruction to check is.  Any illegal
 352  * instruction detected will be given a size of zero, which is a
 353  * signal to abort the rest of the buffer.
 354  */
 355 static int do_validate_cmd(int cmd)
 356 {
 357         switch (((cmd >> 29) & 0x7)) {
 358         case 0x0:
 359                 switch ((cmd >> 23) & 0x3f) {
 360                 case 0x0:
 361                         return 1;       /* MI_NOOP */
 362                 case 0x4:
 363                         return 1;       /* MI_FLUSH */
 364                 default:
 365                         return 0;       /* disallow everything else */
 366                 }
 367                 break;
 368         case 0x1:
 369                 return 0;       /* reserved */
 370         case 0x2:
 371                 return (cmd & 0xff) + 2;        /* 2d commands */
 372         case 0x3:
 373                 if (((cmd >> 24) & 0x1f) <= 0x18)
 374                         return 1;
 375
 376                 switch ((cmd >> 24) & 0x1f) {
 377                 case 0x1c:
 378                         return 1;
 379                 case 0x1d:
 380                         switch ((cmd >> 16) & 0xff) {
 381                         case 0x3:
 382                                 return (cmd & 0x1f) + 2;
 383                         case 0x4:
 384                                 return (cmd & 0xf) + 2;
 385                         default:
 386                                 return (cmd & 0xffff) + 2;
 387                         }
 388                 case 0x1e:
 389                         if (cmd & (1 << 23))
 390                                 return (cmd & 0xffff) + 1;
 391                         else
 392                                 return 1;
 393                 case 0x1f:
 394                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 395                                 return (cmd & 0x1ffff) + 2;
 396                         else if (cmd & (1 << 17))       /* indirect random */
 397                                 if ((cmd & 0xffff) == 0)
 398                                         return 0;       /* unknown length, too hard */
 399                                 else
 400                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 401                         else
 402                                 return 2;       /* indirect sequential */
 403                 default:
 404                         return 0;
 405                 }
 406         default:
 407                 return 0;
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int validate_cmd(int cmd)
 414 {
 415         int ret = do_validate_cmd(cmd);
 416
 417 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 418
 419         return ret;
 420 }
 421
 422 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 423                           int dwords)
 424 {
 425         drm_i915_private_t *dev_priv = dev->dev_private;
 426         int i;
 427         RING_LOCALS;
 428
 429         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 430                 return -EINVAL;
 431
 432         BEGIN_LP_RING((dwords+1)&~1);
 433
 434         for (i = 0; i < dwords;) {
 435                 int cmd, sz;
 436
 437                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 438                         return -EINVAL;
 439
 440                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 441                         return -EINVAL;
 442
 443                 OUT_RING(cmd);
 444
 445                 while (++i, --sz) {
 446                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 447                                                          sizeof(cmd))) {
 448                                 return -EINVAL;
 449                         }
 450                         OUT_RING(cmd);
 451                 }
 452         }
 453
 454         if (dwords & 1)
 455                 OUT_RING(0);
 456
 457         ADVANCE_LP_RING();
 458
 459         return 0;
 460 }
 461
 462 static int i915_emit_box(struct drm_device * dev,
 463                          struct drm_clip_rect __user * boxes,
 464                          int i, int DR1, int DR4)
 465 {
 466         drm_i915_private_t *dev_priv = dev->dev_private;
 467         struct drm_clip_rect box;
 468         RING_LOCALS;
 469
 470         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 471                 return -EFAULT;
 472         }
 473
 474         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 475                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 476                           box.x1, box.y1, box.x2, box.y2);
 477                 return -EINVAL;
 478         }
 479
 480         if (IS_I965G(dev)) {
 481                 BEGIN_LP_RING(4);
 482                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 483                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 484                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 485                 OUT_RING(DR4);
 486                 ADVANCE_LP_RING();
 487         } else {
 488                 BEGIN_LP_RING(6);
 489                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 490                 OUT_RING(DR1);
 491                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 492                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 493                 OUT_RING(DR4);
 494                 OUT_RING(0);
 495                 ADVANCE_LP_RING();
 496         }
 497
 498         return 0;
 499 }
 500
 501 /* XXX: Emitting the counter should really be moved to part of the IRQ
 502  * emit. For now, do it in both places:
 503  */
 504
 505 void i915_emit_breadcrumb(struct drm_device *dev)
 506 {
 507         drm_i915_private_t *dev_priv = dev->dev_private;
 508         RING_LOCALS;
 509
 510         if (++dev_priv->counter > BREADCRUMB_MASK) {
 511                  dev_priv->counter = 1;
 512                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 513         }
 514
 515         if (dev_priv->sarea_priv)
 516                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 517
 518         BEGIN_LP_RING(4);
 519         OUT_RING(MI_STORE_DWORD_INDEX);
 520         OUT_RING(20);
 521         OUT_RING(dev_priv->counter);
 522         OUT_RING(0);
 523         ADVANCE_LP_RING();
 524 }
 525
 526
 527 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 528 {
 529         drm_i915_private_t *dev_priv = dev->dev_private;
 530         uint32_t flush_cmd = MI_FLUSH;
 531         RING_LOCALS;
 532
 533         flush_cmd |= flush;
 534
 535         i915_kernel_lost_context(dev);
 536
 537         BEGIN_LP_RING(4);
 538         OUT_RING(flush_cmd);
 539         OUT_RING(0);
 540         OUT_RING(0);
 541         OUT_RING(0);
 542         ADVANCE_LP_RING();
 543
 544         return 0;
 545 }
 546
 547
 548 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 549                                    drm_i915_cmdbuffer_t * cmd)
 550 {
 551 #ifdef I915_HAVE_FENCE
 552         drm_i915_private_t *dev_priv = dev->dev_private;
 553 #endif
 554         int nbox = cmd->num_cliprects;
 555         int i = 0, count, ret;
 556
 557         if (cmd->sz & 0x3) {
 558                 DRM_ERROR("alignment\n");
 559                 return -EINVAL;
 560         }
 561
 562         i915_kernel_lost_context(dev);
 563
 564         count = nbox ? nbox : 1;
 565
 566         for (i = 0; i < count; i++) {
 567                 if (i < nbox) {
 568                         ret = i915_emit_box(dev, cmd->cliprects, i,
 569                                             cmd->DR1, cmd->DR4);
 570                         if (ret)
 571                                 return ret;
 572                 }
 573
 574                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 575                 if (ret)
 576                         return ret;
 577         }
 578
 579         i915_emit_breadcrumb(dev);
 580 #ifdef I915_HAVE_FENCE
 581         if (unlikely((dev_priv->counter & 0xFF) == 0))
 582                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 583 #endif
 584         return 0;
 585 }
 586
 587 int i915_dispatch_batchbuffer(struct drm_device * dev,
 588                               drm_i915_batchbuffer_t * batch)
 589 {
 590         drm_i915_private_t *dev_priv = dev->dev_private;
 591         struct drm_clip_rect __user *boxes = batch->cliprects;
 592         int nbox = batch->num_cliprects;
 593         int i = 0, count;
 594         RING_LOCALS;
 595
 596         if ((batch->start | batch->used) & 0x7) {
 597                 DRM_ERROR("alignment\n");
 598                 return -EINVAL;
 599         }
 600
 601         i915_kernel_lost_context(dev);
 602
 603         count = nbox ? nbox : 1;
 604
 605         for (i = 0; i < count; i++) {
 606                 if (i < nbox) {
 607                         int ret = i915_emit_box(dev, boxes, i,
 608                                                 batch->DR1, batch->DR4);
 609                         if (ret)
 610                                 return ret;
 611                 }
 612
 613                 if (dev_priv->use_mi_batchbuffer_start) {
 614                         BEGIN_LP_RING(2);
 615                         if (IS_I965G(dev)) {
 616                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 617                                 OUT_RING(batch->start);
 618                         } else {
 619                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 620                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 621                         }
 622                         ADVANCE_LP_RING();
 623
 624                 } else {
 625                         BEGIN_LP_RING(4);
 626                         OUT_RING(MI_BATCH_BUFFER);
 627                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 628                         OUT_RING(batch->start + batch->used - 4);
 629                         OUT_RING(0);
 630                         ADVANCE_LP_RING();
 631                 }
 632         }
 633
 634         i915_emit_breadcrumb(dev);
 635 #ifdef I915_HAVE_FENCE
 636         if (unlikely((dev_priv->counter & 0xFF) == 0))
 637                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 638 #endif
 639         return 0;
 640 }
 641
 642 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 643 {
 644         drm_i915_private_t *dev_priv = dev->dev_private;
 645         u32 num_pages, current_page, next_page, dspbase;
 646         int shift = 2 * plane, x, y;
 647         RING_LOCALS;
 648
 649         /* Calculate display base offset */
 650         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 651         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 652         next_page = (current_page + 1) % num_pages;
 653
 654         switch (next_page) {
 655         default:
 656         case 0:
 657                 dspbase = dev_priv->sarea_priv->front_offset;
 658                 break;
 659         case 1:
 660                 dspbase = dev_priv->sarea_priv->back_offset;
 661                 break;
 662         case 2:
 663                 dspbase = dev_priv->sarea_priv->third_offset;
 664                 break;
 665         }
 666
 667         if (plane == 0) {
 668                 x = dev_priv->sarea_priv->planeA_x;
 669                 y = dev_priv->sarea_priv->planeA_y;
 670         } else {
 671                 x = dev_priv->sarea_priv->planeB_x;
 672                 y = dev_priv->sarea_priv->planeB_y;
 673         }
 674
 675         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 676
 677         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 678                   dspbase);
 679
 680         BEGIN_LP_RING(4);
 681         OUT_RING(sync ? 0 :
 682                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 683                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 684         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 685                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 686         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 687         OUT_RING(dspbase);
 688         ADVANCE_LP_RING();
 689
 690         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 691         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 692 }
 693
 694 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 695 {
 696         drm_i915_private_t *dev_priv = dev->dev_private;
 697         int i;
 698
 699         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 700                   planes, dev_priv->sarea_priv->pf_current_page);
 701
 702         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 703
 704         for (i = 0; i < 2; i++)
 705                 if (planes & (1 << i))
 706                         i915_do_dispatch_flip(dev, i, sync);
 707
 708         i915_emit_breadcrumb(dev);
 709 #ifdef I915_HAVE_FENCE
 710         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 711                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 712 #endif
 713 }
 714
 715 int i915_quiescent(struct drm_device *dev)
 716 {
 717         drm_i915_private_t *dev_priv = dev->dev_private;
 718
 719         i915_kernel_lost_context(dev);
 720         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 721 }
 722
 723 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 724                             struct drm_file *file_priv)
 725 {
 726
 727         LOCK_TEST_WITH_RETURN(dev, file_priv);
 728
 729         return i915_quiescent(dev);
 730 }
 731
 732 static int i915_batchbuffer(struct drm_device *dev, void *data,
 733                             struct drm_file *file_priv)
 734 {
 735         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 736         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 737             dev_priv->sarea_priv;
 738         drm_i915_batchbuffer_t *batch = data;
 739         int ret;
 740
 741         if (!dev_priv->allow_batchbuffer) {
 742                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 743                 return -EINVAL;
 744         }
 745
 746         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 747                   batch->start, batch->used, batch->num_cliprects);
 748
 749         LOCK_TEST_WITH_RETURN(dev, file_priv);
 750
 751         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 752                                                         batch->num_cliprects *
 753                                                         sizeof(struct drm_clip_rect)))
 754                 return -EFAULT;
 755
 756         ret = i915_dispatch_batchbuffer(dev, batch);
 757
 758         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 759         return ret;
 760 }
 761
 762 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 763                           struct drm_file *file_priv)
 764 {
 765         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 766         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 767             dev_priv->sarea_priv;
 768         drm_i915_cmdbuffer_t *cmdbuf = data;
 769         int ret;
 770
 771         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 772                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 773
 774         LOCK_TEST_WITH_RETURN(dev, file_priv);
 775
 776         if (cmdbuf->num_cliprects &&
 777             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 778                                 cmdbuf->num_cliprects *
 779                                 sizeof(struct drm_clip_rect))) {
 780                 DRM_ERROR("Fault accessing cliprects\n");
 781                 return -EFAULT;
 782         }
 783
 784         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 785         if (ret) {
 786                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 787                 return ret;
 788         }
 789
 790         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 791         return 0;
 792 }
 793
 794 #if defined(DRM_DEBUG_CODE)
 795 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 796 #else
 797 #define DRM_DEBUG_RELOCATION    0
 798 #endif
 799
 800 static int i915_do_cleanup_pageflip(struct drm_device * dev)
 801 {
 802         drm_i915_private_t *dev_priv = dev->dev_private;
 803         int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 804
 805         DRM_DEBUG("\n");
 806
 807         for (i = 0, planes = 0; i < 2; i++)
 808                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 809                         dev_priv->sarea_priv->pf_current_page =
 810                                 (dev_priv->sarea_priv->pf_current_page &
 811                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 812
 813                         planes |= 1 << i;
 814                 }
 815
 816         if (planes)
 817                 i915_dispatch_flip(dev, planes, 0);
 818
 819         return 0;
 820 }
 821
 822 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 823 {
 824         drm_i915_flip_t *param = data;
 825
 826         DRM_DEBUG("\n");
 827
 828         LOCK_TEST_WITH_RETURN(dev, file_priv);
 829
 830         /* This is really planes */
 831         if (param->pipes & ~0x3) {
 832                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 833                           param->pipes);
 834                 return -EINVAL;
 835         }
 836
 837         i915_dispatch_flip(dev, param->pipes, 0);
 838
 839         return 0;
 840 }
 841
 842
 843 static int i915_getparam(struct drm_device *dev, void *data,
 844                          struct drm_file *file_priv)
 845 {
 846         drm_i915_private_t *dev_priv = dev->dev_private;
 847         drm_i915_getparam_t *param = data;
 848         int value;
 849
 850         if (!dev_priv) {
 851                 DRM_ERROR("called with no initialization\n");
 852                 return -EINVAL;
 853         }
 854
 855         switch (param->param) {
 856         case I915_PARAM_IRQ_ACTIVE:
 857                 value = dev->irq ? 1 : 0;
 858                 break;
 859         case I915_PARAM_ALLOW_BATCHBUFFER:
 860                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 861                 break;
 862         case I915_PARAM_LAST_DISPATCH:
 863                 value = READ_BREADCRUMB(dev_priv);
 864                 break;
 865         case I915_PARAM_CHIPSET_ID:
 866                 value = dev->pci_device;
 867                 break;
 868         default:
 869                 DRM_ERROR("Unknown parameter %d\n", param->param);
 870                 return -EINVAL;
 871         }
 872
 873         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 874                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 875                 return -EFAULT;
 876         }
 877
 878         return 0;
 879 }
 880
 881 static int i915_setparam(struct drm_device *dev, void *data,
 882                          struct drm_file *file_priv)
 883 {
 884         drm_i915_private_t *dev_priv = dev->dev_private;
 885         drm_i915_setparam_t *param = data;
 886
 887         if (!dev_priv) {
 888                 DRM_ERROR("called with no initialization\n");
 889                 return -EINVAL;
 890         }
 891
 892         switch (param->param) {
 893         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 894                 if (!IS_I965G(dev))
 895                         dev_priv->use_mi_batchbuffer_start = param->value;
 896                 break;
 897         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 898                 dev_priv->tex_lru_log_granularity = param->value;
 899                 break;
 900         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 901                 dev_priv->allow_batchbuffer = param->value;
 902                 break;
 903         default:
 904                 DRM_ERROR("unknown parameter %d\n", param->param);
 905                 return -EINVAL;
 906         }
 907
 908         return 0;
 909 }
 910
 911 drm_i915_mmio_entry_t mmio_table[] = {
 912         [MMIO_REGS_PS_DEPTH_COUNT] = {
 913                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 914                 0x2350,
 915                 8
 916         }
 917 };
 918
 919 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 920
 921 static int i915_mmio(struct drm_device *dev, void *data,
 922                      struct drm_file *file_priv)
 923 {
 924         uint32_t buf[8];
 925         drm_i915_private_t *dev_priv = dev->dev_private;
 926         drm_i915_mmio_entry_t *e;
 927         drm_i915_mmio_t *mmio = data;
 928         void __iomem *base;
 929         int i;
 930
 931         if (!dev_priv) {
 932                 DRM_ERROR("called with no initialization\n");
 933                 return -EINVAL;
 934         }
 935
 936         if (mmio->reg >= mmio_table_size)
 937                 return -EINVAL;
 938
 939         e = &mmio_table[mmio->reg];
 940         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 941
 942         switch (mmio->read_write) {
 943         case I915_MMIO_READ:
 944                 if (!(e->flag & I915_MMIO_MAY_READ))
 945                         return -EINVAL;
 946                 for (i = 0; i < e->size / 4; i++)
 947                         buf[i] = I915_READ(e->offset + i * 4);
 948                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 949                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 950                         return -EFAULT;
 951                 }
 952                 break;
 953
 954         case I915_MMIO_WRITE:
 955                 if (!(e->flag & I915_MMIO_MAY_WRITE))
 956                         return -EINVAL;
 957                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 958                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 959                         return -EFAULT;
 960                 }
 961                 for (i = 0; i < e->size / 4; i++)
 962                         I915_WRITE(e->offset + i * 4, buf[i]);
 963                 break;
 964         }
 965         return 0;
 966 }
 967
 968 static int i915_set_status_page(struct drm_device *dev, void *data,
 969                                 struct drm_file *file_priv)
 970 {
 971         drm_i915_private_t *dev_priv = dev->dev_private;
 972         drm_i915_hws_addr_t *hws = data;
 973
 974         if (!I915_NEED_GFX_HWS(dev))
 975                 return -EINVAL;
 976
 977         if (!dev_priv) {
 978                 DRM_ERROR("called with no initialization\n");
 979                 return -EINVAL;
 980         }
 981         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 982
 983         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 984
 985         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 986         dev_priv->hws_map.size = 4*1024;
 987         dev_priv->hws_map.type = 0;
 988         dev_priv->hws_map.flags = 0;
 989         dev_priv->hws_map.mtrr = 0;
 990
 991         drm_core_ioremap(&dev_priv->hws_map, dev);
 992         if (dev_priv->hws_map.handle == NULL) {
 993                 i915_dma_cleanup(dev);
 994                 dev_priv->status_gfx_addr = 0;
 995                 DRM_ERROR("can not ioremap virtual address for"
 996                                 " G33 hw status page\n");
 997                 return -ENOMEM;
 998         }
 999         dev_priv->hw_status_page = dev_priv->hws_map.handle;
1000
1001         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1002         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1003         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1004                         dev_priv->status_gfx_addr);
1005         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1006         return 0;
1007 }
1008
1009 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1010 {
1011         struct drm_i915_private *dev_priv;
1012         unsigned long base, size;
1013         int ret = 0, num_pipes = 2, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1014
1015         /* i915 has 4 more counters */
1016         dev->counters += 4;
1017         dev->types[6] = _DRM_STAT_IRQ;
1018         dev->types[7] = _DRM_STAT_PRIMARY;
1019         dev->types[8] = _DRM_STAT_SECONDARY;
1020         dev->types[9] = _DRM_STAT_DMA;
1021
1022         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1023         if (dev_priv == NULL)
1024                 return -ENOMEM;
1025
1026         memset(dev_priv, 0, sizeof(drm_i915_private_t));
1027
1028         dev->dev_private = (void *)dev_priv;
1029
1030         /* Add register map (needed for suspend/resume) */
1031         base = drm_get_resource_start(dev, mmio_bar);
1032         size = drm_get_resource_len(dev, mmio_bar);
1033
1034         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1035                 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1036
1037 #ifdef __linux__
1038 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1039         intel_init_chipset_flush_compat(dev);
1040 #endif
1041 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
1042         intel_opregion_init(dev);
1043 #endif
1044 #endif
1045
1046         I915_WRITE16(HWSTAM, 0xeffe);
1047         I915_WRITE16(IMR, 0x0);
1048         I915_WRITE16(IER, 0x0);
1049
1050         DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1051         INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
1052         dev_priv->swaps_pending = 0;
1053
1054         DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1055         dev_priv->user_irq_refcount = 0;
1056         dev_priv->irq_enable_reg = 0;
1057
1058         ret = drm_vblank_init(dev, num_pipes);
1059         if (ret)
1060                 return ret;
1061
1062         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1063         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1064
1065         i915_enable_interrupt(dev);
1066         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1067
1068         /*
1069          * Initialize the hardware status page IRQ location.
1070          */
1071
1072         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1073
1074         return ret;
1075 }
1076
1077 int i915_driver_unload(struct drm_device *dev)
1078 {
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         u32 temp;
1081
1082         if (dev_priv) {
1083                 dev_priv->vblank_pipe = 0;
1084
1085                 dev_priv->irq_enabled = 0;
1086                 I915_WRITE(HWSTAM, 0xffffffff);
1087                 I915_WRITE(IMR, 0xffffffff);
1088                 I915_WRITE(IER, 0x0);
1089
1090                 temp = I915_READ(PIPEASTAT);
1091                 I915_WRITE(PIPEASTAT, temp);
1092                 temp = I915_READ(PIPEBSTAT);
1093                 I915_WRITE(PIPEBSTAT, temp);
1094                 temp = I915_READ(IIR);
1095                 I915_WRITE(IIR, temp);
1096         }
1097
1098         if (dev_priv->mmio_map)
1099                 drm_rmmap(dev, dev_priv->mmio_map);
1100
1101 #ifdef __linux__
1102 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25)
1103         intel_opregion_free(dev);
1104 #endif
1105 #endif
1106
1107         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1108                  DRM_MEM_DRIVER);
1109 #ifdef __linux__
1110 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1111         intel_fini_chipset_flush_compat(dev);
1112 #endif
1113 #endif
1114         return 0;
1115 }
1116
1117 void i915_driver_lastclose(struct drm_device * dev)
1118 {
1119         drm_i915_private_t *dev_priv = dev->dev_private;
1120
1121         /* agp off can use this to get called before dev_priv */
1122         if (!dev_priv)
1123                 return;
1124
1125 #ifdef I915_HAVE_BUFFER
1126         if (dev_priv->val_bufs) {
1127                 vfree(dev_priv->val_bufs);
1128                 dev_priv->val_bufs = NULL;
1129         }
1130 #endif
1131
1132         if (drm_getsarea(dev) && dev_priv->sarea_priv)
1133                 i915_do_cleanup_pageflip(dev);
1134         if (dev_priv->agp_heap)
1135                 i915_mem_takedown(&(dev_priv->agp_heap));
1136 #if defined(I915_HAVE_BUFFER)
1137         if (dev_priv->sarea_kmap.virtual) {
1138                 drm_bo_kunmap(&dev_priv->sarea_kmap);
1139                 dev_priv->sarea_kmap.virtual = NULL;
1140                 dev->lock.hw_lock = NULL;
1141                 dev->sigdata.lock = NULL;
1142         }
1143
1144         if (dev_priv->sarea_bo) {
1145                 mutex_lock(&dev->struct_mutex);
1146                 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
1147                 mutex_unlock(&dev->struct_mutex);
1148                 dev_priv->sarea_bo = NULL;
1149         }
1150 #endif
1151         i915_dma_cleanup(dev);
1152 }
1153
1154 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1155 {
1156         drm_i915_private_t *dev_priv = dev->dev_private;
1157         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1158 }
1159
1160 struct drm_ioctl_desc i915_ioctls[] = {
1161         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1162         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1163         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1164         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1165         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1166         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1167         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1168         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1169         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1170         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1171         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1172         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1173         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1174         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1175         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1176         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1177         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1178         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1179 #ifdef I915_HAVE_BUFFER
1180         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1181 #endif
1182 };
1183
1184 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1185
1186 /**
1187  * Determine if the device really is AGP or not.
1188  *
1189  * All Intel graphics chipsets are treated as AGP, even if they are really
1190  * PCI-e.
1191  *
1192  * \param dev   The device to be tested.
1193  *
1194  * \returns
1195  * A value of 1 is always retured to indictate every i9x5 is AGP.
1196  */
1197 int i915_driver_device_is_agp(struct drm_device * dev)
1198 {
1199         return 1;
1200 }
1201
1202 int i915_driver_firstopen(struct drm_device *dev)
1203 {
1204 #ifdef I915_HAVE_BUFFER
1205         drm_bo_driver_init(dev);
1206 #endif
1207         return 0;
1208 }