shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         drm_i915_private_t *dev_priv = dev->dev_private;
  42         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  44         int i;
  45
  46         for (i = 0; i < 10000; i++) {
  47                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  48                 ring->space = ring->head - (ring->tail + 8);
  49                 if (ring->space < 0)
  50                         ring->space += ring->Size;
  51                 if (ring->space >= n)
  52                         return 0;
  53
  54                 if (ring->head != last_head)
  55                         i = 0;
  56
  57                 last_head = ring->head;
  58                 DRM_UDELAY(1);
  59         }
  60
  61         return -EBUSY;
  62 }
  63
  64 void i915_kernel_lost_context(struct drm_device * dev)
  65 {
  66         drm_i915_private_t *dev_priv = dev->dev_private;
  67         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  68
  69         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  70         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  71         ring->space = ring->head - (ring->tail + 8);
  72         if (ring->space < 0)
  73                 ring->space += ring->Size;
  74 }
  75
  76 static int i915_dma_cleanup(struct drm_device * dev)
  77 {
  78         drm_i915_private_t *dev_priv = dev->dev_private;
  79         /* Make sure interrupts are disabled here because the uninstall ioctl
  80          * may not have been called from userspace and after dev_private
  81          * is freed, it's too late.
  82          */
  83         if (dev->irq)
  84                 drm_irq_uninstall(dev);
  85
  86         if (dev_priv->ring.virtual_start) {
  87                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
  88                 dev_priv->ring.virtual_start = 0;
  89                 dev_priv->ring.map.handle = 0;
  90                 dev_priv->ring.map.size = 0;
  91         }
  92
  93         if (dev_priv->status_page_dmah) {
  94                 drm_pci_free(dev, dev_priv->status_page_dmah);
  95                 dev_priv->status_page_dmah = NULL;
  96                 /* Need to rewrite hardware status page */
  97                 I915_WRITE(0x02080, 0x1ffff000);
  98         }
  99
 100         if (dev_priv->status_gfx_addr) {
 101                 dev_priv->status_gfx_addr = 0;
 102                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 103                 I915_WRITE(0x02080, 0x1ffff000);
 104         }
 105
 106         return 0;
 107 }
 108
 109
 110 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 111 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 112 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 113         ((void *) ((unsigned char *) (p) +                      \
 114                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 115
 116 #define DRI2_SAREA_BLOCK_END            0x0000
 117 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 118 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 119
 120 static int
 121 setup_dri2_sarea(struct drm_device * dev,
 122                  struct drm_file *file_priv,
 123                  drm_i915_init_t * init)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         int ret;
 127         unsigned int *p, *end, *next;
 128
 129         mutex_lock(&dev->struct_mutex);
 130         dev_priv->sarea_bo =
 131                 drm_lookup_buffer_object(file_priv,
 132                                          init->sarea_handle, 1);
 133         mutex_unlock(&dev->struct_mutex);
 134
 135         if (!dev_priv->sarea_bo) {
 136                 DRM_ERROR("did not find sarea bo\n");
 137                 return -EINVAL;
 138         }
 139
 140         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 141                           dev_priv->sarea_bo->num_pages,
 142                           &dev_priv->sarea_kmap);
 143         if (ret) {
 144                 DRM_ERROR("could not map sarea bo\n");
 145                 return ret;
 146         }
 147
 148         p = dev_priv->sarea_kmap.virtual;
 149         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 150         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 151                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 152                 case DRI2_SAREA_BLOCK_LOCK:
 153                         dev->lock.hw_lock = (void *) (p + 1);
 154                         dev->sigdata.lock = dev->lock.hw_lock;
 155                         break;
 156                 }
 157                 next = DRI2_SAREA_BLOCK_NEXT(p);
 158                 if (next <= p || end < next) {
 159                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 160                                   next, p, end);
 161                         return -EINVAL;
 162                 }
 163                 p = next;
 164         }
 165
 166         return 0;
 167 }
 168
 169
 170 static int i915_initialize(struct drm_device * dev,
 171                            struct drm_file *file_priv,
 172                            drm_i915_init_t * init)
 173 {
 174         drm_i915_private_t *dev_priv = dev->dev_private;
 175         int ret;
 176
 177         dev_priv->sarea = drm_getsarea(dev);
 178         if (!dev_priv->sarea) {
 179                 DRM_ERROR("can not find sarea!\n");
 180                 i915_dma_cleanup(dev);
 181                 return -EINVAL;
 182         }
 183
 184         if (init->mmio_offset != 0)
 185                 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 186         if (!dev_priv->mmio_map) {
 187                 i915_dma_cleanup(dev);
 188                 DRM_ERROR("can not find mmio map!\n");
 189                 return -EINVAL;
 190         }
 191
 192 #ifdef I915_HAVE_BUFFER
 193         dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 194 #endif
 195
 196         if (init->sarea_priv_offset)
 197                 dev_priv->sarea_priv = (drm_i915_sarea_t *)
 198                         ((u8 *) dev_priv->sarea->handle +
 199                          init->sarea_priv_offset);
 200         else {
 201                 /* No sarea_priv for you! */
 202                 dev_priv->sarea_priv = NULL;
 203         }
 204
 205         dev_priv->ring.Start = init->ring_start;
 206         dev_priv->ring.End = init->ring_end;
 207         dev_priv->ring.Size = init->ring_size;
 208         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 209
 210         dev_priv->ring.map.offset = init->ring_start;
 211         dev_priv->ring.map.size = init->ring_size;
 212         dev_priv->ring.map.type = 0;
 213         dev_priv->ring.map.flags = 0;
 214         dev_priv->ring.map.mtrr = 0;
 215
 216         drm_core_ioremap(&dev_priv->ring.map, dev);
 217
 218         if (dev_priv->ring.map.handle == NULL) {
 219                 i915_dma_cleanup(dev);
 220                 DRM_ERROR("can not ioremap virtual address for"
 221                           " ring buffer\n");
 222                 return -ENOMEM;
 223         }
 224
 225         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 226
 227         dev_priv->cpp = init->cpp;
 228
 229         if (dev_priv->sarea_priv)
 230                 dev_priv->sarea_priv->pf_current_page = 0;
 231
 232         /* We are using separate values as placeholders for mechanisms for
 233          * private backbuffer/depthbuffer usage.
 234          */
 235         dev_priv->use_mi_batchbuffer_start = 0;
 236         if (IS_I965G(dev)) /* 965 doesn't support older method */
 237                 dev_priv->use_mi_batchbuffer_start = 1;
 238
 239         /* Allow hardware batchbuffers unless told otherwise.
 240          */
 241         dev_priv->allow_batchbuffer = 1;
 242
 243         /* Enable vblank on pipe A for older X servers
 244          */
 245         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 246
 247         /* Program Hardware Status Page */
 248         if (!IS_G33(dev)) {
 249                 dev_priv->status_page_dmah =
 250                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 251
 252                 if (!dev_priv->status_page_dmah) {
 253                         i915_dma_cleanup(dev);
 254                         DRM_ERROR("Can not allocate hardware status page\n");
 255                         return -ENOMEM;
 256                 }
 257                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 258                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 259
 260                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 261
 262                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 263         }
 264         DRM_DEBUG("Enabled hardware status page\n");
 265 #ifdef I915_HAVE_BUFFER
 266         mutex_init(&dev_priv->cmdbuf_mutex);
 267 #endif
 268
 269         if (init->func == I915_INIT_DMA2) {
 270                 ret = setup_dri2_sarea(dev, file_priv, init);
 271                 if (ret) {
 272                         i915_dma_cleanup(dev);
 273                         DRM_ERROR("could not set up dri2 sarea\n");
 274                         return ret;
 275                 }
 276         }
 277
 278
 279         return 0;
 280 }
 281
 282 static int i915_dma_resume(struct drm_device * dev)
 283 {
 284         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 285
 286         DRM_DEBUG("\n");
 287
 288         if (!dev_priv->sarea) {
 289                 DRM_ERROR("can not find sarea!\n");
 290                 return -EINVAL;
 291         }
 292
 293         if (!dev_priv->mmio_map) {
 294                 DRM_ERROR("can not find mmio map!\n");
 295                 return -EINVAL;
 296         }
 297
 298         if (dev_priv->ring.map.handle == NULL) {
 299                 DRM_ERROR("can not ioremap virtual address for"
 300                           " ring buffer\n");
 301                 return -ENOMEM;
 302         }
 303
 304         /* Program Hardware Status Page */
 305         if (!dev_priv->hw_status_page) {
 306                 DRM_ERROR("Can not find hardware status page\n");
 307                 return -EINVAL;
 308         }
 309         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 310
 311         if (dev_priv->status_gfx_addr != 0)
 312                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 313         else
 314                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 315         DRM_DEBUG("Enabled hardware status page\n");
 316
 317         return 0;
 318 }
 319
 320 static int i915_dma_init(struct drm_device *dev, void *data,
 321                          struct drm_file *file_priv)
 322 {
 323         drm_i915_init_t *init = data;
 324         int retcode = 0;
 325
 326         switch (init->func) {
 327         case I915_INIT_DMA:
 328         case I915_INIT_DMA2:
 329                 retcode = i915_initialize(dev, file_priv, init);
 330                 break;
 331         case I915_CLEANUP_DMA:
 332                 retcode = i915_dma_cleanup(dev);
 333                 break;
 334         case I915_RESUME_DMA:
 335                 retcode = i915_dma_resume(dev);
 336                 break;
 337         default:
 338                 retcode = -EINVAL;
 339                 break;
 340         }
 341
 342         return retcode;
 343 }
 344
 345 /* Implement basically the same security restrictions as hardware does
 346  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 347  *
 348  * Most of the calculations below involve calculating the size of a
 349  * particular instruction.  It's important to get the size right as
 350  * that tells us where the next instruction to check is.  Any illegal
 351  * instruction detected will be given a size of zero, which is a
 352  * signal to abort the rest of the buffer.
 353  */
 354 static int do_validate_cmd(int cmd)
 355 {
 356         switch (((cmd >> 29) & 0x7)) {
 357         case 0x0:
 358                 switch ((cmd >> 23) & 0x3f) {
 359                 case 0x0:
 360                         return 1;       /* MI_NOOP */
 361                 case 0x4:
 362                         return 1;       /* MI_FLUSH */
 363                 default:
 364                         return 0;       /* disallow everything else */
 365                 }
 366                 break;
 367         case 0x1:
 368                 return 0;       /* reserved */
 369         case 0x2:
 370                 return (cmd & 0xff) + 2;        /* 2d commands */
 371         case 0x3:
 372                 if (((cmd >> 24) & 0x1f) <= 0x18)
 373                         return 1;
 374
 375                 switch ((cmd >> 24) & 0x1f) {
 376                 case 0x1c:
 377                         return 1;
 378                 case 0x1d:
 379                         switch ((cmd >> 16) & 0xff) {
 380                         case 0x3:
 381                                 return (cmd & 0x1f) + 2;
 382                         case 0x4:
 383                                 return (cmd & 0xf) + 2;
 384                         default:
 385                                 return (cmd & 0xffff) + 2;
 386                         }
 387                 case 0x1e:
 388                         if (cmd & (1 << 23))
 389                                 return (cmd & 0xffff) + 1;
 390                         else
 391                                 return 1;
 392                 case 0x1f:
 393                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 394                                 return (cmd & 0x1ffff) + 2;
 395                         else if (cmd & (1 << 17))       /* indirect random */
 396                                 if ((cmd & 0xffff) == 0)
 397                                         return 0;       /* unknown length, too hard */
 398                                 else
 399                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 400                         else
 401                                 return 2;       /* indirect sequential */
 402                 default:
 403                         return 0;
 404                 }
 405         default:
 406                 return 0;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int validate_cmd(int cmd)
 413 {
 414         int ret = do_validate_cmd(cmd);
 415
 416 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 417
 418         return ret;
 419 }
 420
 421 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 422                           int dwords)
 423 {
 424         drm_i915_private_t *dev_priv = dev->dev_private;
 425         int i;
 426         RING_LOCALS;
 427
 428         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 429                 return -EINVAL;
 430
 431         BEGIN_LP_RING((dwords+1)&~1);
 432
 433         for (i = 0; i < dwords;) {
 434                 int cmd, sz;
 435
 436                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 437                         return -EINVAL;
 438
 439                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 440                         return -EINVAL;
 441
 442                 OUT_RING(cmd);
 443
 444                 while (++i, --sz) {
 445                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 446                                                          sizeof(cmd))) {
 447                                 return -EINVAL;
 448                         }
 449                         OUT_RING(cmd);
 450                 }
 451         }
 452
 453         if (dwords & 1)
 454                 OUT_RING(0);
 455
 456         ADVANCE_LP_RING();
 457
 458         return 0;
 459 }
 460
 461 static int i915_emit_box(struct drm_device * dev,
 462                          struct drm_clip_rect __user * boxes,
 463                          int i, int DR1, int DR4)
 464 {
 465         drm_i915_private_t *dev_priv = dev->dev_private;
 466         struct drm_clip_rect box;
 467         RING_LOCALS;
 468
 469         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 470                 return -EFAULT;
 471         }
 472
 473         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 474                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 475                           box.x1, box.y1, box.x2, box.y2);
 476                 return -EINVAL;
 477         }
 478
 479         if (IS_I965G(dev)) {
 480                 BEGIN_LP_RING(4);
 481                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 482                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 483                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 484                 OUT_RING(DR4);
 485                 ADVANCE_LP_RING();
 486         } else {
 487                 BEGIN_LP_RING(6);
 488                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 489                 OUT_RING(DR1);
 490                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 491                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 492                 OUT_RING(DR4);
 493                 OUT_RING(0);
 494                 ADVANCE_LP_RING();
 495         }
 496
 497         return 0;
 498 }
 499
 500 /* XXX: Emitting the counter should really be moved to part of the IRQ
 501  * emit. For now, do it in both places:
 502  */
 503
 504 void i915_emit_breadcrumb(struct drm_device *dev)
 505 {
 506         drm_i915_private_t *dev_priv = dev->dev_private;
 507         RING_LOCALS;
 508
 509         if (++dev_priv->counter > BREADCRUMB_MASK) {
 510                  dev_priv->counter = 1;
 511                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 512         }
 513
 514         if (dev_priv->sarea_priv)
 515                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 516
 517         BEGIN_LP_RING(4);
 518         OUT_RING(CMD_STORE_DWORD_IDX);
 519         OUT_RING(20);
 520         OUT_RING(dev_priv->counter);
 521         OUT_RING(0);
 522         ADVANCE_LP_RING();
 523 }
 524
 525
 526 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 527 {
 528         drm_i915_private_t *dev_priv = dev->dev_private;
 529         uint32_t flush_cmd = CMD_MI_FLUSH;
 530         RING_LOCALS;
 531
 532         flush_cmd |= flush;
 533
 534         i915_kernel_lost_context(dev);
 535
 536         BEGIN_LP_RING(4);
 537         OUT_RING(flush_cmd);
 538         OUT_RING(0);
 539         OUT_RING(0);
 540         OUT_RING(0);
 541         ADVANCE_LP_RING();
 542
 543         return 0;
 544 }
 545
 546
 547 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 548                                    drm_i915_cmdbuffer_t * cmd)
 549 {
 550 #ifdef I915_HAVE_FENCE
 551         drm_i915_private_t *dev_priv = dev->dev_private;
 552 #endif
 553         int nbox = cmd->num_cliprects;
 554         int i = 0, count, ret;
 555
 556         if (cmd->sz & 0x3) {
 557                 DRM_ERROR("alignment\n");
 558                 return -EINVAL;
 559         }
 560
 561         i915_kernel_lost_context(dev);
 562
 563         count = nbox ? nbox : 1;
 564
 565         for (i = 0; i < count; i++) {
 566                 if (i < nbox) {
 567                         ret = i915_emit_box(dev, cmd->cliprects, i,
 568                                             cmd->DR1, cmd->DR4);
 569                         if (ret)
 570                                 return ret;
 571                 }
 572
 573                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 574                 if (ret)
 575                         return ret;
 576         }
 577
 578         i915_emit_breadcrumb(dev);
 579 #ifdef I915_HAVE_FENCE
 580         if (unlikely((dev_priv->counter & 0xFF) == 0))
 581                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 582 #endif
 583         return 0;
 584 }
 585
 586 int i915_dispatch_batchbuffer(struct drm_device * dev,
 587                               drm_i915_batchbuffer_t * batch)
 588 {
 589         drm_i915_private_t *dev_priv = dev->dev_private;
 590         struct drm_clip_rect __user *boxes = batch->cliprects;
 591         int nbox = batch->num_cliprects;
 592         int i = 0, count;
 593         RING_LOCALS;
 594
 595         if ((batch->start | batch->used) & 0x7) {
 596                 DRM_ERROR("alignment\n");
 597                 return -EINVAL;
 598         }
 599
 600         i915_kernel_lost_context(dev);
 601
 602         count = nbox ? nbox : 1;
 603
 604         for (i = 0; i < count; i++) {
 605                 if (i < nbox) {
 606                         int ret = i915_emit_box(dev, boxes, i,
 607                                                 batch->DR1, batch->DR4);
 608                         if (ret)
 609                                 return ret;
 610                 }
 611
 612                 if (dev_priv->use_mi_batchbuffer_start) {
 613                         BEGIN_LP_RING(2);
 614                         if (IS_I965G(dev)) {
 615                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 616                                 OUT_RING(batch->start);
 617                         } else {
 618                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 619                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 620                         }
 621                         ADVANCE_LP_RING();
 622
 623                 } else {
 624                         BEGIN_LP_RING(4);
 625                         OUT_RING(MI_BATCH_BUFFER);
 626                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 627                         OUT_RING(batch->start + batch->used - 4);
 628                         OUT_RING(0);
 629                         ADVANCE_LP_RING();
 630                 }
 631         }
 632
 633         i915_emit_breadcrumb(dev);
 634 #ifdef I915_HAVE_FENCE
 635         if (unlikely((dev_priv->counter & 0xFF) == 0))
 636                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 637 #endif
 638         return 0;
 639 }
 640
 641 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 642 {
 643         drm_i915_private_t *dev_priv = dev->dev_private;
 644         u32 num_pages, current_page, next_page, dspbase;
 645         int shift = 2 * plane, x, y;
 646         RING_LOCALS;
 647
 648         /* Calculate display base offset */
 649         num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 650         current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 651         next_page = (current_page + 1) % num_pages;
 652
 653         switch (next_page) {
 654         default:
 655         case 0:
 656                 dspbase = dev_priv->sarea_priv->front_offset;
 657                 break;
 658         case 1:
 659                 dspbase = dev_priv->sarea_priv->back_offset;
 660                 break;
 661         case 2:
 662                 dspbase = dev_priv->sarea_priv->third_offset;
 663                 break;
 664         }
 665
 666         if (plane == 0) {
 667                 x = dev_priv->sarea_priv->planeA_x;
 668                 y = dev_priv->sarea_priv->planeA_y;
 669         } else {
 670                 x = dev_priv->sarea_priv->planeB_x;
 671                 y = dev_priv->sarea_priv->planeB_y;
 672         }
 673
 674         dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 675
 676         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 677                   dspbase);
 678
 679         BEGIN_LP_RING(4);
 680         OUT_RING(sync ? 0 :
 681                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 682                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 683         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 684                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 685         OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
 686         OUT_RING(dspbase);
 687         ADVANCE_LP_RING();
 688
 689         dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 690         dev_priv->sarea_priv->pf_current_page |= next_page << shift;
 691 }
 692
 693 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 694 {
 695         drm_i915_private_t *dev_priv = dev->dev_private;
 696         int i;
 697
 698         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 699                   planes, dev_priv->sarea_priv->pf_current_page);
 700
 701         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 702
 703         for (i = 0; i < 2; i++)
 704                 if (planes & (1 << i))
 705                         i915_do_dispatch_flip(dev, i, sync);
 706
 707         i915_emit_breadcrumb(dev);
 708 #ifdef I915_HAVE_FENCE
 709         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 710                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 711 #endif
 712 }
 713
 714 int i915_quiescent(struct drm_device *dev)
 715 {
 716         drm_i915_private_t *dev_priv = dev->dev_private;
 717
 718         i915_kernel_lost_context(dev);
 719         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 720 }
 721
 722 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 723                             struct drm_file *file_priv)
 724 {
 725
 726         LOCK_TEST_WITH_RETURN(dev, file_priv);
 727
 728         return i915_quiescent(dev);
 729 }
 730
 731 static int i915_batchbuffer(struct drm_device *dev, void *data,
 732                             struct drm_file *file_priv)
 733 {
 734         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 735         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 736             dev_priv->sarea_priv;
 737         drm_i915_batchbuffer_t *batch = data;
 738         int ret;
 739
 740         if (!dev_priv->allow_batchbuffer) {
 741                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 742                 return -EINVAL;
 743         }
 744
 745         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 746                   batch->start, batch->used, batch->num_cliprects);
 747
 748         LOCK_TEST_WITH_RETURN(dev, file_priv);
 749
 750         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 751                                                         batch->num_cliprects *
 752                                                         sizeof(struct drm_clip_rect)))
 753                 return -EFAULT;
 754
 755         ret = i915_dispatch_batchbuffer(dev, batch);
 756
 757         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 758         return ret;
 759 }
 760
 761 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 762                           struct drm_file *file_priv)
 763 {
 764         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 765         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 766             dev_priv->sarea_priv;
 767         drm_i915_cmdbuffer_t *cmdbuf = data;
 768         int ret;
 769
 770         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 771                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 772
 773         LOCK_TEST_WITH_RETURN(dev, file_priv);
 774
 775         if (cmdbuf->num_cliprects &&
 776             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 777                                 cmdbuf->num_cliprects *
 778                                 sizeof(struct drm_clip_rect))) {
 779                 DRM_ERROR("Fault accessing cliprects\n");
 780                 return -EFAULT;
 781         }
 782
 783         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 784         if (ret) {
 785                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 786                 return ret;
 787         }
 788
 789         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 790         return 0;
 791 }
 792
 793 #if DRM_DEBUG_CODE
 794 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 795 #else
 796 #define DRM_DEBUG_RELOCATION    0
 797 #endif
 798
 799 static int i915_do_cleanup_pageflip(struct drm_device * dev)
 800 {
 801         drm_i915_private_t *dev_priv = dev->dev_private;
 802         int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
 803
 804         DRM_DEBUG("\n");
 805
 806         for (i = 0, planes = 0; i < 2; i++)
 807                 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 808                         dev_priv->sarea_priv->pf_current_page =
 809                                 (dev_priv->sarea_priv->pf_current_page &
 810                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 811
 812                         planes |= 1 << i;
 813                 }
 814
 815         if (planes)
 816                 i915_dispatch_flip(dev, planes, 0);
 817
 818         return 0;
 819 }
 820
 821 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 822 {
 823         drm_i915_flip_t *param = data;
 824
 825         DRM_DEBUG("\n");
 826
 827         LOCK_TEST_WITH_RETURN(dev, file_priv);
 828
 829         /* This is really planes */
 830         if (param->pipes & ~0x3) {
 831                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 832                           param->pipes);
 833                 return -EINVAL;
 834         }
 835
 836         i915_dispatch_flip(dev, param->pipes, 0);
 837
 838         return 0;
 839 }
 840
 841
 842 static int i915_getparam(struct drm_device *dev, void *data,
 843                          struct drm_file *file_priv)
 844 {
 845         drm_i915_private_t *dev_priv = dev->dev_private;
 846         drm_i915_getparam_t *param = data;
 847         int value;
 848
 849         if (!dev_priv) {
 850                 DRM_ERROR("called with no initialization\n");
 851                 return -EINVAL;
 852         }
 853
 854         switch (param->param) {
 855         case I915_PARAM_IRQ_ACTIVE:
 856                 value = dev->irq ? 1 : 0;
 857                 break;
 858         case I915_PARAM_ALLOW_BATCHBUFFER:
 859                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 860                 break;
 861         case I915_PARAM_LAST_DISPATCH:
 862                 value = READ_BREADCRUMB(dev_priv);
 863                 break;
 864         case I915_PARAM_CHIPSET_ID:
 865                 value = dev->pci_device;
 866                 break;
 867         default:
 868                 DRM_ERROR("Unknown parameter %d\n", param->param);
 869                 return -EINVAL;
 870         }
 871
 872         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 873                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 874                 return -EFAULT;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int i915_setparam(struct drm_device *dev, void *data,
 881                          struct drm_file *file_priv)
 882 {
 883         drm_i915_private_t *dev_priv = dev->dev_private;
 884         drm_i915_setparam_t *param = data;
 885
 886         if (!dev_priv) {
 887                 DRM_ERROR("called with no initialization\n");
 888                 return -EINVAL;
 889         }
 890
 891         switch (param->param) {
 892         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 893                 if (!IS_I965G(dev))
 894                         dev_priv->use_mi_batchbuffer_start = param->value;
 895                 break;
 896         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 897                 dev_priv->tex_lru_log_granularity = param->value;
 898                 break;
 899         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 900                 dev_priv->allow_batchbuffer = param->value;
 901                 break;
 902         default:
 903                 DRM_ERROR("unknown parameter %d\n", param->param);
 904                 return -EINVAL;
 905         }
 906
 907         return 0;
 908 }
 909
 910 drm_i915_mmio_entry_t mmio_table[] = {
 911         [MMIO_REGS_PS_DEPTH_COUNT] = {
 912                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 913                 0x2350,
 914                 8
 915         }
 916 };
 917
 918 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 919
 920 static int i915_mmio(struct drm_device *dev, void *data,
 921                      struct drm_file *file_priv)
 922 {
 923         uint32_t buf[8];
 924         drm_i915_private_t *dev_priv = dev->dev_private;
 925         drm_i915_mmio_entry_t *e;
 926         drm_i915_mmio_t *mmio = data;
 927         void __iomem *base;
 928         int i;
 929
 930         if (!dev_priv) {
 931                 DRM_ERROR("called with no initialization\n");
 932                 return -EINVAL;
 933         }
 934
 935         if (mmio->reg >= mmio_table_size)
 936                 return -EINVAL;
 937
 938         e = &mmio_table[mmio->reg];
 939         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 940
 941         switch (mmio->read_write) {
 942         case I915_MMIO_READ:
 943                 if (!(e->flag & I915_MMIO_MAY_READ))
 944                         return -EINVAL;
 945                 for (i = 0; i < e->size / 4; i++)
 946                         buf[i] = I915_READ(e->offset + i * 4);
 947                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 948                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 949                         return -EFAULT;
 950                 }
 951                 break;
 952
 953         case I915_MMIO_WRITE:
 954                 if (!(e->flag & I915_MMIO_MAY_WRITE))
 955                         return -EINVAL;
 956                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 957                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 958                         return -EFAULT;
 959                 }
 960                 for (i = 0; i < e->size / 4; i++)
 961                         I915_WRITE(e->offset + i * 4, buf[i]);
 962                 break;
 963         }
 964         return 0;
 965 }
 966
 967 static int i915_set_status_page(struct drm_device *dev, void *data,
 968                                 struct drm_file *file_priv)
 969 {
 970         drm_i915_private_t *dev_priv = dev->dev_private;
 971         drm_i915_hws_addr_t *hws = data;
 972
 973         if (!dev_priv) {
 974                 DRM_ERROR("called with no initialization\n");
 975                 return -EINVAL;
 976         }
 977         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 978
 979         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
 980
 981         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 982         dev_priv->hws_map.size = 4*1024;
 983         dev_priv->hws_map.type = 0;
 984         dev_priv->hws_map.flags = 0;
 985         dev_priv->hws_map.mtrr = 0;
 986
 987         drm_core_ioremap(&dev_priv->hws_map, dev);
 988         if (dev_priv->hws_map.handle == NULL) {
 989                 i915_dma_cleanup(dev);
 990                 dev_priv->status_gfx_addr = 0;
 991                 DRM_ERROR("can not ioremap virtual address for"
 992                                 " G33 hw status page\n");
 993                 return -ENOMEM;
 994         }
 995         dev_priv->hw_status_page = dev_priv->hws_map.handle;
 996
 997         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 998         I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 999         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1000                         dev_priv->status_gfx_addr);
1001         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1002         return 0;
1003 }
1004
1005 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1006 {
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         unsigned long base, size;
1009         int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1010
1011         /* i915 has 4 more counters */
1012         dev->counters += 4;
1013         dev->types[6] = _DRM_STAT_IRQ;
1014         dev->types[7] = _DRM_STAT_PRIMARY;
1015         dev->types[8] = _DRM_STAT_SECONDARY;
1016         dev->types[9] = _DRM_STAT_DMA;
1017
1018         dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1019         if (dev_priv == NULL)
1020                 return -ENOMEM;
1021
1022         memset(dev_priv, 0, sizeof(drm_i915_private_t));
1023
1024         dev->dev_private = (void *)dev_priv;
1025
1026         /* Add register map (needed for suspend/resume) */
1027         base = drm_get_resource_start(dev, mmio_bar);
1028         size = drm_get_resource_len(dev, mmio_bar);
1029
1030         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1031                 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1032
1033 #ifdef __linux__
1034 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1035         intel_init_chipset_flush_compat(dev);
1036 #endif
1037 #endif
1038
1039         return ret;
1040 }
1041
1042 int i915_driver_unload(struct drm_device *dev)
1043 {
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045
1046         if (dev_priv->mmio_map)
1047                 drm_rmmap(dev, dev_priv->mmio_map);
1048
1049         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1050                  DRM_MEM_DRIVER);
1051 #ifdef __linux__
1052 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1053         intel_fini_chipset_flush_compat(dev);
1054 #endif
1055 #endif
1056         return 0;
1057 }
1058
1059 void i915_driver_lastclose(struct drm_device * dev)
1060 {
1061         drm_i915_private_t *dev_priv = dev->dev_private;
1062
1063         /* agp off can use this to get called before dev_priv */
1064         if (!dev_priv)
1065                 return;
1066
1067 #ifdef I915_HAVE_BUFFER
1068         if (dev_priv->val_bufs) {
1069                 vfree(dev_priv->val_bufs);
1070                 dev_priv->val_bufs = NULL;
1071         }
1072 #endif
1073
1074         if (drm_getsarea(dev) && dev_priv->sarea_priv)
1075                 i915_do_cleanup_pageflip(dev);
1076         if (dev_priv->agp_heap)
1077                 i915_mem_takedown(&(dev_priv->agp_heap));
1078
1079         if (dev_priv->sarea_kmap.virtual) {
1080                 drm_bo_kunmap(&dev_priv->sarea_kmap);
1081                 dev_priv->sarea_kmap.virtual = NULL;
1082                 dev->lock.hw_lock = NULL;
1083                 dev->sigdata.lock = NULL;
1084         }
1085
1086         if (dev_priv->sarea_bo) {
1087                 mutex_lock(&dev->struct_mutex);
1088                 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
1089                 mutex_unlock(&dev->struct_mutex);
1090                 dev_priv->sarea_bo = NULL;
1091         }
1092
1093         i915_dma_cleanup(dev);
1094 }
1095
1096 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1097 {
1098         drm_i915_private_t *dev_priv = dev->dev_private;
1099         i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1100 }
1101
1102 struct drm_ioctl_desc i915_ioctls[] = {
1103         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1104         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1105         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1106         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1107         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1108         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1109         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1110         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1111         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1112         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1113         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1114         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1115         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1116         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1117         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1118         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1119         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1120         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1121 #ifdef I915_HAVE_BUFFER
1122         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1123 #endif
1124 };
1125
1126 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1127
1128 /**
1129  * Determine if the device really is AGP or not.
1130  *
1131  * All Intel graphics chipsets are treated as AGP, even if they are really
1132  * PCI-e.
1133  *
1134  * \param dev   The device to be tested.
1135  *
1136  * \returns
1137  * A value of 1 is always retured to indictate every i9x5 is AGP.
1138  */
1139 int i915_driver_device_is_agp(struct drm_device * dev)
1140 {
1141         return 1;
1142 }
1143
1144 int i915_driver_firstopen(struct drm_device *dev)
1145 {
1146 #ifdef I915_HAVE_BUFFER
1147         drm_bo_driver_init(dev);
1148 #endif
1149         return 0;
1150 }