shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         struct drm_i915_private *dev_priv = dev->dev_private;
  42         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  44         u32 acthd_reg = IS_I965G(dev) ? I965REG_ACTHD : I915REG_ACTHD;
  45         u32 last_acthd = I915_READ(acthd_reg);
  46         u32 acthd;
  47         int i;
  48
  49         for (i = 0; i < 10000; i++) {
  50                 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  51                 acthd = I915_READ(acthd_reg);
  52                 ring->space = ring->head - (ring->tail + 8);
  53                 if (ring->space < 0)
  54                         ring->space += ring->Size;
  55                 if (ring->space >= n)
  56                         return 0;
  57
  58                 if (ring->head != last_head)
  59                         i = 0;
  60
  61                 if (acthd != last_acthd)
  62                         i = 0;
  63
  64                 last_head = ring->head;
  65                 last_acthd = acthd;
  66                 msleep_interruptible (10);
  67         }
  68
  69         return -EBUSY;
  70 }
  71
  72 #if I915_RING_VALIDATE
  73 /**
  74  * Validate the cached ring tail value
  75  *
  76  * If the X server writes to the ring and DRM doesn't
  77  * reload the head and tail pointers, it will end up writing
  78  * data to the wrong place in the ring, causing havoc.
  79  */
  80 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
  81 {
  82         struct drm_i915_private *dev_priv = dev->dev_private;
  83         drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
  84         u32     tail = I915_READ(LP_RING+RING_TAIL) & HEAD_ADDR;
  85         u32     head = I915_READ(LP_RING+RING_HEAD) & HEAD_ADDR;
  86
  87         if (tail != ring->tail) {
  88                 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
  89                           func, line,
  90                           ring->head, head, ring->tail, tail);
  91                 BUG_ON(1);
  92         }
  93 }
  94 #endif
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         struct drm_i915_private *dev_priv = dev->dev_private;
  99         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
 100
 101         /* we should never lose context on the ring with modesetting
 102          * as we don't expose it to userspace */
 103         if (drm_core_check_feature(dev, DRIVER_MODESET))
 104                 return;
 105
 106         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 107         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 108         ring->space = ring->head - (ring->tail + 8);
 109         if (ring->space < 0)
 110                 ring->space += ring->Size;
 111 }
 112
 113 int i915_dma_cleanup(struct drm_device * dev)
 114 {
 115         struct drm_i915_private *dev_priv = dev->dev_private;
 116
 117         if (drm_core_check_feature(dev, DRIVER_MODESET))
 118                 return 0;
 119
 120         /* Make sure interrupts are disabled here because the uninstall ioctl
 121          * may not have been called from userspace and after dev_private
 122          * is freed, it's too late.
 123          */
 124         if (dev->irq_enabled)
 125                 drm_irq_uninstall(dev);
 126
 127         if (dev_priv->ring.virtual_start) {
 128                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 129                 dev_priv->ring.virtual_start = 0;
 130                 dev_priv->ring.map.handle = 0;
 131                 dev_priv->ring.map.size = 0;
 132                 dev_priv->ring.Size = 0;
 133         }
 134
 135         if (dev_priv->status_page_dmah) {
 136                 drm_pci_free(dev, dev_priv->status_page_dmah);
 137                 dev_priv->status_page_dmah = NULL;
 138                 /* Need to rewrite hardware status page */
 139                 I915_WRITE(0x02080, 0x1ffff000);
 140         }
 141
 142         if (dev_priv->hws_agpoffset) {
 143                 dev_priv->hws_agpoffset = 0;
 144                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 145                 I915_WRITE(0x02080, 0x1ffff000);
 146         }
 147
 148         return 0;
 149 }
 150
 151 #if defined(I915_HAVE_BUFFER) && defined(DRI2)
 152 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 153 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 154 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 155         ((void *) ((unsigned char *) (p) +                      \
 156                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 157
 158 #define DRI2_SAREA_BLOCK_END            0x0000
 159 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 160 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 161
 162 static int
 163 setup_dri2_sarea(struct drm_device * dev,
 164                  struct drm_file *file_priv,
 165                  drm_i915_init_t * init)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         int ret;
 169         unsigned int *p, *end, *next;
 170
 171         mutex_lock(&dev->struct_mutex);
 172         dev_priv->sarea_bo =
 173                 drm_lookup_buffer_object(file_priv,
 174                                          init->sarea_handle, 1);
 175         mutex_unlock(&dev->struct_mutex);
 176
 177         if (!dev_priv->sarea_bo) {
 178                 DRM_ERROR("did not find sarea bo\n");
 179                 return -EINVAL;
 180         }
 181
 182         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 183                           dev_priv->sarea_bo->num_pages,
 184                           &dev_priv->sarea_kmap);
 185         if (ret) {
 186                 DRM_ERROR("could not map sarea bo\n");
 187                 return ret;
 188         }
 189
 190         p = dev_priv->sarea_kmap.virtual;
 191         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 192         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 193                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 194                 case DRI2_SAREA_BLOCK_LOCK:
 195                         dev->primary->master->lock.hw_lock = (void *) (p + 1);
 196                         dev->sigdata.lock = dev->primary->master->lock.hw_lock;
 197                         break;
 198                 }
 199                 next = DRI2_SAREA_BLOCK_NEXT(p);
 200                 if (next <= p || end < next) {
 201                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 202                                   next, p, end);
 203                         return -EINVAL;
 204                 }
 205                 p = next;
 206         }
 207
 208         return 0;
 209 }
 210 #endif
 211
 212 static int i915_initialize(struct drm_device * dev,
 213                            struct drm_file *file_priv,
 214                            drm_i915_init_t * init)
 215 {
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 218
 219         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 220                 if (init->mmio_offset != 0)
 221                         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 222                 if (!dev_priv->mmio_map) {
 223                         i915_dma_cleanup(dev);
 224                         DRM_ERROR("can not find mmio map!\n");
 225                         return -EINVAL;
 226                 }
 227         }
 228
 229 #ifdef I915_HAVE_BUFFER
 230         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 231                 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 232         }
 233 #endif
 234
 235         if (init->ring_size != 0) {
 236                 dev_priv->ring.Size = init->ring_size;
 237                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 238                 dev_priv->ring.map.offset = init->ring_start;
 239                 dev_priv->ring.map.size = init->ring_size;
 240                 dev_priv->ring.map.type = 0;
 241                 dev_priv->ring.map.flags = 0;
 242                 dev_priv->ring.map.mtrr = 0;
 243                 drm_core_ioremap(&dev_priv->ring.map, dev);
 244
 245                 if (dev_priv->ring.map.handle == NULL) {
 246                         i915_dma_cleanup(dev);
 247                         DRM_ERROR("can not ioremap virtual address for"
 248                                   " ring buffer\n");
 249                         return -ENOMEM;
 250                 }
 251                 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 252         }
 253
 254         dev_priv->cpp = init->cpp;
 255         master_priv->sarea_priv->pf_current_page = 0;
 256
 257         /* We are using separate values as placeholders for mechanisms for
 258          * private backbuffer/depthbuffer usage.
 259          */
 260
 261         /* Allow hardware batchbuffers unless told otherwise.
 262          */
 263         dev_priv->allow_batchbuffer = 1;
 264
 265         /* Enable vblank on pipe A for older X servers
 266          */
 267         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 268
 269         /* Program Hardware Status Page */
 270         if (!I915_NEED_GFX_HWS(dev)) {
 271                 dev_priv->status_page_dmah =
 272                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 273
 274                 if (!dev_priv->status_page_dmah) {
 275                         i915_dma_cleanup(dev);
 276                         DRM_ERROR("Can not allocate hardware status page\n");
 277                         return -ENOMEM;
 278                 }
 279                 dev_priv->hws_vaddr = dev_priv->status_page_dmah->vaddr;
 280                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 281
 282                 memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
 283
 284                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 285         }
 286         DRM_DEBUG("Enabled hardware status page\n");
 287
 288 #ifdef I915_HAVE_BUFFER
 289         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 290                 mutex_init(&dev_priv->cmdbuf_mutex);
 291         }
 292 #ifdef DRI2
 293         if (init->func == I915_INIT_DMA2) {
 294                 int ret = setup_dri2_sarea(dev, file_priv, init);
 295                 if (ret) {
 296                         i915_dma_cleanup(dev);
 297                         DRM_ERROR("could not set up dri2 sarea\n");
 298                         return ret;
 299                 }
 300         }
 301 #endif /* DRI2 */
 302 #endif /* I915_HAVE_BUFFER */
 303
 304         return 0;
 305 }
 306
 307 static int i915_dma_resume(struct drm_device * dev)
 308 {
 309         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 310
 311         DRM_DEBUG("\n");
 312
 313         if (drm_core_check_feature(dev, DRIVER_MODESET))
 314                 return 0;
 315
 316         if (dev_priv->ring.map.handle == NULL) {
 317                 DRM_ERROR("can not ioremap virtual address for"
 318                           " ring buffer\n");
 319                 return -ENOMEM;
 320         }
 321
 322         /* Program Hardware Status Page */
 323         if (!dev_priv->hws_vaddr) {
 324                 DRM_ERROR("Can not find hardware status page\n");
 325                 return -EINVAL;
 326         }
 327         DRM_DEBUG("hw status page @ %p\n", dev_priv->hws_vaddr);
 328
 329         if (dev_priv->hws_agpoffset != 0)
 330                 I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
 331         else
 332                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 333         DRM_DEBUG("Enabled hardware status page\n");
 334
 335         return 0;
 336 }
 337
 338 static int i915_dma_init(struct drm_device *dev, void *data,
 339                          struct drm_file *file_priv)
 340 {
 341         struct drm_i915_init *init = data;
 342         int retcode = 0;
 343
 344         switch (init->func) {
 345         case I915_INIT_DMA:
 346         case I915_INIT_DMA2:
 347                 retcode = i915_initialize(dev, file_priv, init);
 348                 break;
 349         case I915_CLEANUP_DMA:
 350                 retcode = i915_dma_cleanup(dev);
 351                 break;
 352         case I915_RESUME_DMA:
 353                 retcode = i915_dma_resume(dev);
 354                 break;
 355         default:
 356                 retcode = -EINVAL;
 357                 break;
 358         }
 359
 360         return retcode;
 361 }
 362
 363 /* Implement basically the same security restrictions as hardware does
 364  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 365  *
 366  * Most of the calculations below involve calculating the size of a
 367  * particular instruction.  It's important to get the size right as
 368  * that tells us where the next instruction to check is.  Any illegal
 369  * instruction detected will be given a size of zero, which is a
 370  * signal to abort the rest of the buffer.
 371  */
 372 static int do_validate_cmd(int cmd)
 373 {
 374         switch (((cmd >> 29) & 0x7)) {
 375         case 0x0:
 376                 switch ((cmd >> 23) & 0x3f) {
 377                 case 0x0:
 378                         return 1;       /* MI_NOOP */
 379                 case 0x4:
 380                         return 1;       /* MI_FLUSH */
 381                 default:
 382                         return 0;       /* disallow everything else */
 383                 }
 384                 break;
 385         case 0x1:
 386                 return 0;       /* reserved */
 387         case 0x2:
 388                 return (cmd & 0xff) + 2;        /* 2d commands */
 389         case 0x3:
 390                 if (((cmd >> 24) & 0x1f) <= 0x18)
 391                         return 1;
 392
 393                 switch ((cmd >> 24) & 0x1f) {
 394                 case 0x1c:
 395                         return 1;
 396                 case 0x1d:
 397                         switch ((cmd >> 16) & 0xff) {
 398                         case 0x3:
 399                                 return (cmd & 0x1f) + 2;
 400                         case 0x4:
 401                                 return (cmd & 0xf) + 2;
 402                         default:
 403                                 return (cmd & 0xffff) + 2;
 404                         }
 405                 case 0x1e:
 406                         if (cmd & (1 << 23))
 407                                 return (cmd & 0xffff) + 1;
 408                         else
 409                                 return 1;
 410                 case 0x1f:
 411                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 412                                 return (cmd & 0x1ffff) + 2;
 413                         else if (cmd & (1 << 17))       /* indirect random */
 414                                 if ((cmd & 0xffff) == 0)
 415                                         return 0;       /* unknown length, too hard */
 416                                 else
 417                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 418                         else
 419                                 return 2;       /* indirect sequential */
 420                 default:
 421                         return 0;
 422                 }
 423         default:
 424                 return 0;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int validate_cmd(int cmd)
 431 {
 432         int ret = do_validate_cmd(cmd);
 433
 434 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 435
 436         return ret;
 437 }
 438
 439 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 440                           int dwords)
 441 {
 442         struct drm_i915_private *dev_priv = dev->dev_private;
 443         int i;
 444         RING_LOCALS;
 445
 446         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 447                 return -EINVAL;
 448
 449         BEGIN_LP_RING((dwords+1)&~1);
 450
 451         for (i = 0; i < dwords;) {
 452                 int cmd, sz;
 453
 454                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 455                         return -EINVAL;
 456
 457                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 458                         return -EINVAL;
 459
 460                 OUT_RING(cmd);
 461
 462                 while (++i, --sz) {
 463                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 464                                                          sizeof(cmd))) {
 465                                 return -EINVAL;
 466                         }
 467                         OUT_RING(cmd);
 468                 }
 469         }
 470
 471         if (dwords & 1)
 472                 OUT_RING(0);
 473
 474         ADVANCE_LP_RING();
 475
 476         return 0;
 477 }
 478
 479 int i915_emit_box(struct drm_device * dev,
 480                   struct drm_clip_rect __user * boxes,
 481                   int i, int DR1, int DR4)
 482 {
 483         struct drm_i915_private *dev_priv = dev->dev_private;
 484         struct drm_clip_rect box;
 485         RING_LOCALS;
 486
 487         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 488                 return -EFAULT;
 489         }
 490
 491         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 492                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 493                           box.x1, box.y1, box.x2, box.y2);
 494                 return -EINVAL;
 495         }
 496
 497         if (IS_I965G(dev)) {
 498                 BEGIN_LP_RING(4);
 499                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 500                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 501                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 502                 OUT_RING(DR4);
 503                 ADVANCE_LP_RING();
 504         } else {
 505                 BEGIN_LP_RING(6);
 506                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 507                 OUT_RING(DR1);
 508                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 509                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 510                 OUT_RING(DR4);
 511                 OUT_RING(0);
 512                 ADVANCE_LP_RING();
 513         }
 514
 515         return 0;
 516 }
 517
 518 /* XXX: Emitting the counter should really be moved to part of the IRQ
 519  * emit. For now, do it in both places:
 520  */
 521
 522 void i915_emit_breadcrumb(struct drm_device *dev)
 523 {
 524         struct drm_i915_private *dev_priv = dev->dev_private;
 525         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 526         RING_LOCALS;
 527
 528         if (++dev_priv->counter > BREADCRUMB_MASK) {
 529                  dev_priv->counter = 1;
 530                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 531         }
 532
 533         master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 534
 535         BEGIN_LP_RING(4);
 536         OUT_RING(MI_STORE_DWORD_INDEX);
 537         OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
 538         OUT_RING(dev_priv->counter);
 539         OUT_RING(0);
 540         ADVANCE_LP_RING();
 541 }
 542
 543
 544 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 545 {
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547         uint32_t flush_cmd = MI_FLUSH;
 548         RING_LOCALS;
 549
 550         flush_cmd |= flush;
 551
 552         i915_kernel_lost_context(dev);
 553
 554         BEGIN_LP_RING(4);
 555         OUT_RING(flush_cmd);
 556         OUT_RING(0);
 557         OUT_RING(0);
 558         OUT_RING(0);
 559         ADVANCE_LP_RING();
 560
 561         return 0;
 562 }
 563
 564
 565 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 566                                    struct drm_i915_cmdbuffer * cmd)
 567 {
 568 #ifdef I915_HAVE_FENCE
 569         struct drm_i915_private *dev_priv = dev->dev_private;
 570 #endif
 571         int nbox = cmd->num_cliprects;
 572         int i = 0, count, ret;
 573
 574         if (cmd->sz & 0x3) {
 575                 DRM_ERROR("alignment\n");
 576                 return -EINVAL;
 577         }
 578
 579         i915_kernel_lost_context(dev);
 580
 581         count = nbox ? nbox : 1;
 582
 583         for (i = 0; i < count; i++) {
 584                 if (i < nbox) {
 585                         ret = i915_emit_box(dev, cmd->cliprects, i,
 586                                             cmd->DR1, cmd->DR4);
 587                         if (ret)
 588                                 return ret;
 589                 }
 590
 591                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         i915_emit_breadcrumb(dev);
 597 #ifdef I915_HAVE_FENCE
 598         if (unlikely((dev_priv->counter & 0xFF) == 0))
 599                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 600 #endif
 601         return 0;
 602 }
 603
 604 int i915_dispatch_batchbuffer(struct drm_device * dev,
 605                               drm_i915_batchbuffer_t * batch)
 606 {
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608         struct drm_clip_rect __user *boxes = batch->cliprects;
 609         int nbox = batch->num_cliprects;
 610         int i = 0, count;
 611         RING_LOCALS;
 612
 613         if ((batch->start | batch->used) & 0x7) {
 614                 DRM_ERROR("alignment\n");
 615                 return -EINVAL;
 616         }
 617
 618         i915_kernel_lost_context(dev);
 619
 620         count = nbox ? nbox : 1;
 621
 622         for (i = 0; i < count; i++) {
 623                 if (i < nbox) {
 624                         int ret = i915_emit_box(dev, boxes, i,
 625                                                 batch->DR1, batch->DR4);
 626                         if (ret)
 627                                 return ret;
 628                 }
 629
 630                 if (IS_I830(dev) || IS_845G(dev)) {
 631                         BEGIN_LP_RING(4);
 632                         OUT_RING(MI_BATCH_BUFFER);
 633                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 634                         OUT_RING(batch->start + batch->used - 4);
 635                         OUT_RING(0);
 636                         ADVANCE_LP_RING();
 637                 } else {
 638                         BEGIN_LP_RING(2);
 639                         if (IS_I965G(dev)) {
 640                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 641                                 OUT_RING(batch->start);
 642                         } else {
 643                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 644                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 645                         }
 646                         ADVANCE_LP_RING();
 647                 }
 648         }
 649
 650         i915_emit_breadcrumb(dev);
 651 #ifdef I915_HAVE_FENCE
 652         if (unlikely((dev_priv->counter & 0xFF) == 0))
 653                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 654 #endif
 655         return 0;
 656 }
 657
 658 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 659 {
 660         struct drm_i915_private *dev_priv = dev->dev_private;
 661         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 662         u32 num_pages, current_page, next_page, dspbase;
 663         int shift = 2 * plane, x, y;
 664         RING_LOCALS;
 665
 666         /* Calculate display base offset */
 667         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 668         current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 669         next_page = (current_page + 1) % num_pages;
 670
 671         switch (next_page) {
 672         default:
 673         case 0:
 674                 dspbase = master_priv->sarea_priv->front_offset;
 675                 break;
 676         case 1:
 677                 dspbase = master_priv->sarea_priv->back_offset;
 678                 break;
 679         case 2:
 680                 dspbase = master_priv->sarea_priv->third_offset;
 681                 break;
 682         }
 683
 684         if (plane == 0) {
 685                 x = master_priv->sarea_priv->planeA_x;
 686                 y = master_priv->sarea_priv->planeA_y;
 687         } else {
 688                 x = master_priv->sarea_priv->planeB_x;
 689                 y = master_priv->sarea_priv->planeB_y;
 690         }
 691
 692         dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 693
 694         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 695                   dspbase);
 696
 697         BEGIN_LP_RING(4);
 698         OUT_RING(sync ? 0 :
 699                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 700                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 701         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 702                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 703         OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
 704         OUT_RING(dspbase);
 705         ADVANCE_LP_RING();
 706
 707         master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 708         master_priv->sarea_priv->pf_current_page |= next_page << shift;
 709 }
 710
 711 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 715         int i;
 716
 717         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 718                   planes, master_priv->sarea_priv->pf_current_page);
 719
 720         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 721
 722         for (i = 0; i < 2; i++)
 723                 if (planes & (1 << i))
 724                         i915_do_dispatch_flip(dev, i, sync);
 725
 726         i915_emit_breadcrumb(dev);
 727 #ifdef I915_HAVE_FENCE
 728         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 729                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 730 #endif
 731 }
 732
 733 int i915_quiescent(struct drm_device *dev)
 734 {
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         int ret;
 737
 738         i915_kernel_lost_context(dev);
 739         ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 740         if (ret)
 741         {
 742                 i915_kernel_lost_context (dev);
 743                 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
 744                            dev_priv->ring.head,
 745                            dev_priv->ring.tail,
 746                            dev_priv->ring.space);
 747         }
 748         return ret;
 749 }
 750
 751 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 752                             struct drm_file *file_priv)
 753 {
 754
 755         LOCK_TEST_WITH_RETURN(dev, file_priv);
 756
 757         return i915_quiescent(dev);
 758 }
 759
 760 static int i915_batchbuffer(struct drm_device *dev, void *data,
 761                             struct drm_file *file_priv)
 762 {
 763         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 764         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 765         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 766             master_priv->sarea_priv;
 767         drm_i915_batchbuffer_t *batch = data;
 768         int ret;
 769
 770         if (!dev_priv->allow_batchbuffer) {
 771                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 772                 return -EINVAL;
 773         }
 774
 775         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 776                   batch->start, batch->used, batch->num_cliprects);
 777
 778         LOCK_TEST_WITH_RETURN(dev, file_priv);
 779
 780         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 781                                                         batch->num_cliprects *
 782                                                         sizeof(struct drm_clip_rect)))
 783                 return -EFAULT;
 784
 785         ret = i915_dispatch_batchbuffer(dev, batch);
 786
 787         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 788         return ret;
 789 }
 790
 791 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 792                           struct drm_file *file_priv)
 793 {
 794         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 795         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 796         struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
 797                 master_priv->sarea_priv;
 798         struct drm_i915_cmdbuffer *cmdbuf = data;
 799         int ret;
 800
 801         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 802                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 803
 804         LOCK_TEST_WITH_RETURN(dev, file_priv);
 805
 806         if (cmdbuf->num_cliprects &&
 807             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 808                                 cmdbuf->num_cliprects *
 809                                 sizeof(struct drm_clip_rect))) {
 810                 DRM_ERROR("Fault accessing cliprects\n");
 811                 return -EFAULT;
 812         }
 813
 814         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 815         if (ret) {
 816                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 817                 return ret;
 818         }
 819
 820         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 821         return 0;
 822 }
 823
 824 #if defined(DRM_DEBUG_CODE)
 825 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 826 #else
 827 #define DRM_DEBUG_RELOCATION    0
 828 #endif
 829
 830 int i915_do_cleanup_pageflip(struct drm_device * dev)
 831 {
 832         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 833         int i, planes, num_pages;
 834
 835         DRM_DEBUG("\n");
 836         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 837         for (i = 0, planes = 0; i < 2; i++) {
 838                 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 839                         master_priv->sarea_priv->pf_current_page =
 840                                 (master_priv->sarea_priv->pf_current_page &
 841                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 842
 843                         planes |= 1 << i;
 844                 }
 845         }
 846
 847         if (planes)
 848                 i915_dispatch_flip(dev, planes, 0);
 849
 850         return 0;
 851 }
 852
 853 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 854 {
 855         struct drm_i915_flip *param = data;
 856
 857         DRM_DEBUG("\n");
 858
 859         LOCK_TEST_WITH_RETURN(dev, file_priv);
 860
 861         /* This is really planes */
 862         if (param->pipes & ~0x3) {
 863                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 864                           param->pipes);
 865                 return -EINVAL;
 866         }
 867
 868         i915_dispatch_flip(dev, param->pipes, 0);
 869
 870         return 0;
 871 }
 872
 873
 874 static int i915_getparam(struct drm_device *dev, void *data,
 875                          struct drm_file *file_priv)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878         struct drm_i915_getparam *param = data;
 879         int value;
 880
 881         if (!dev_priv) {
 882                 DRM_ERROR("called with no initialization\n");
 883                 return -EINVAL;
 884         }
 885
 886         switch (param->param) {
 887         case I915_PARAM_IRQ_ACTIVE:
 888                 value = dev->irq_enabled ? 1 : 0;
 889                 break;
 890         case I915_PARAM_ALLOW_BATCHBUFFER:
 891                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 892                 break;
 893         case I915_PARAM_LAST_DISPATCH:
 894                 value = READ_BREADCRUMB(dev_priv);
 895                 break;
 896         case I915_PARAM_CHIPSET_ID:
 897                 value = dev->pci_device;
 898                 break;
 899         default:
 900                 DRM_ERROR("Unknown parameter %d\n", param->param);
 901                 return -EINVAL;
 902         }
 903
 904         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 905                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 906                 return -EFAULT;
 907         }
 908
 909         return 0;
 910 }
 911
 912 static int i915_setparam(struct drm_device *dev, void *data,
 913                          struct drm_file *file_priv)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         drm_i915_setparam_t *param = data;
 917
 918         if (!dev_priv) {
 919                 DRM_ERROR("called with no initialization\n");
 920                 return -EINVAL;
 921         }
 922
 923         switch (param->param) {
 924         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 925                 break;
 926         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 927                 dev_priv->tex_lru_log_granularity = param->value;
 928                 break;
 929         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 930                 dev_priv->allow_batchbuffer = param->value;
 931                 break;
 932         default:
 933                 DRM_ERROR("unknown parameter %d\n", param->param);
 934                 return -EINVAL;
 935         }
 936
 937         return 0;
 938 }
 939
 940 drm_i915_mmio_entry_t mmio_table[] = {
 941         [MMIO_REGS_PS_DEPTH_COUNT] = {
 942                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 943                 0x2350,
 944                 8
 945         },
 946         [MMIO_REGS_DOVSTA] = {
 947                 I915_MMIO_MAY_READ,
 948                 0x30008,
 949                 1
 950         },
 951         [MMIO_REGS_GAMMA] = {
 952                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 953                 0x30010,
 954                 6
 955         },
 956         [MMIO_REGS_FENCE] = {
 957                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 958                 0x2000,
 959                 8
 960         },
 961         [MMIO_REGS_FENCE_NEW] = {
 962                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 963                 0x3000,
 964                 16
 965         }
 966 };
 967
 968 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 969
 970 static int i915_mmio(struct drm_device *dev, void *data,
 971                      struct drm_file *file_priv)
 972 {
 973         uint32_t buf[8];
 974         struct drm_i915_private *dev_priv = dev->dev_private;
 975         drm_i915_mmio_entry_t *e;
 976         drm_i915_mmio_t *mmio = data;
 977         void __iomem *base;
 978         int i;
 979
 980         if (!dev_priv) {
 981                 DRM_ERROR("called with no initialization\n");
 982                 return -EINVAL;
 983         }
 984
 985         if (mmio->reg >= mmio_table_size)
 986                 return -EINVAL;
 987
 988         e = &mmio_table[mmio->reg];
 989         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 990
 991         switch (mmio->read_write) {
 992         case I915_MMIO_READ:
 993                 if (!(e->flag & I915_MMIO_MAY_READ))
 994                         return -EINVAL;
 995                 for (i = 0; i < e->size / 4; i++)
 996                         buf[i] = I915_READ(e->offset + i * 4);
 997                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 998                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 999                         return -EFAULT;
1000                 }
1001                 break;
1002
1003         case I915_MMIO_WRITE:
1004                 if (!(e->flag & I915_MMIO_MAY_WRITE))
1005                         return -EINVAL;
1006                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
1007                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
1008                         return -EFAULT;
1009                 }
1010                 for (i = 0; i < e->size / 4; i++)
1011                         I915_WRITE(e->offset + i * 4, buf[i]);
1012                 break;
1013         }
1014         return 0;
1015 }
1016
1017 static int i915_set_status_page(struct drm_device *dev, void *data,
1018                                 struct drm_file *file_priv)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         drm_i915_hws_addr_t *hws = data;
1022
1023         if (!I915_NEED_GFX_HWS(dev))
1024                 return -EINVAL;
1025
1026         if (!dev_priv) {
1027                 DRM_ERROR("called with no initialization\n");
1028                 return -EINVAL;
1029         }
1030
1031         if (drm_core_check_feature(dev, DRIVER_MODESET))
1032                 return 0;
1033
1034         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1035
1036         dev_priv->hws_agpoffset = hws->addr & (0x1ffff<<12);
1037
1038         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1039         dev_priv->hws_map.size = 4*1024;
1040         dev_priv->hws_map.type = 0;
1041         dev_priv->hws_map.flags = 0;
1042         dev_priv->hws_map.mtrr = 0;
1043
1044         drm_core_ioremap(&dev_priv->hws_map, dev);
1045         if (dev_priv->hws_map.handle == NULL) {
1046                 i915_dma_cleanup(dev);
1047                 dev_priv->hws_agpoffset = 0;
1048                 DRM_ERROR("can not ioremap virtual address for"
1049                                 " G33 hw status page\n");
1050                 return -ENOMEM;
1051         }
1052         dev_priv->hws_vaddr = dev_priv->hws_map.handle;
1053
1054         memset(dev_priv->hws_vaddr, 0, PAGE_SIZE);
1055         I915_WRITE(HWS_PGA, dev_priv->hws_agpoffset);
1056         DRM_DEBUG("load hws at %p\n", dev_priv->hws_vaddr);
1057
1058         return 0;
1059 }
1060
1061 struct drm_ioctl_desc i915_ioctls[] = {
1062         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER),
1063         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1064         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1065         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1066         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1067         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1068         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1069         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER),
1070         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1071         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1072         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1073         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1074         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1075         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1076         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1077         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1078         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1079         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1080 #ifdef I915_HAVE_BUFFER
1081         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1082 #endif
1083         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1084         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1085         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1086         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1087         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1088         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1089         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
1090         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
1091         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1092         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1093         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1094         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1095         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1096         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1097 };
1098
1099 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1100
1101 /**
1102  * Determine if the device really is AGP or not.
1103  *
1104  * All Intel graphics chipsets are treated as AGP, even if they are really
1105  * PCI-e.
1106  *
1107  * \param dev   The device to be tested.
1108  *
1109  * \returns
1110  * A value of 1 is always retured to indictate every i9x5 is AGP.
1111  */
1112 int i915_driver_device_is_agp(struct drm_device * dev)
1113 {
1114         return 1;
1115 }
1116