3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
92 #define XFREE86_VERSION(major,minor,patch,snap) \
93 ((major << 16) | (minor << 8) | patch)
95 #ifndef CONFIG_XFREE86_VERSION
96 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
99 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
100 #define DRM_PROC_DEVICES "/proc/devices"
101 #define DRM_PROC_MISC "/proc/misc"
102 #define DRM_PROC_DRM "/proc/drm"
103 #define DRM_DEV_DRM "/dev/drm"
104 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
105 #define DRM_DEV_UID 0
106 #define DRM_DEV_GID 0
109 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
113 #if defined(__linux__) || defined(__NetBSD__)
114 #define DRM_MAJOR 226
116 #define DRM_MAX_MINOR 15
118 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
119 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
120 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
121 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
123 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
124 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
125 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
126 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
127 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
129 #if defined(__linux__)
130 typedef unsigned int drm_handle_t;
132 #include <sys/types.h>
133 typedef unsigned long drm_handle_t; /**< To mapped regions */
135 typedef unsigned int drm_context_t; /**< GLXContext handle */
136 typedef unsigned int drm_drawable_t;
137 typedef unsigned int drm_magic_t; /**< Magic for authentication */
142 * \warning If you change this structure, make sure you change
143 * XF86DRIClipRectRec in the server as well
145 * \note KW: Actually it's illegal to change either for
146 * backwards-compatibility reasons.
148 struct drm_clip_rect {
156 * Drawable information.
158 struct drm_drawable_info {
159 unsigned int num_rects;
160 struct drm_clip_rect *rects;
166 struct drm_tex_region {
169 unsigned char in_use;
170 unsigned char padding;
177 * The lock structure is a simple cache-line aligned integer. To avoid
178 * processor bus contention on a multiprocessor system, there should not be any
179 * other data stored in the same cache line.
182 __volatile__ unsigned int lock; /**< lock variable */
183 char padding[60]; /**< Pad to cache line */
186 /* This is beyond ugly, and only works on GCC. However, it allows me to use
187 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
188 * fix is to use uint32_t instead of size_t, but that fix will break existing
189 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
190 * eventually happen, though. I chose 'unsigned long' to be the fallback type
191 * because that works on all the platforms I know about. Hopefully, the
192 * real fix will happen before that bites us.
196 # define DRM_SIZE_T __SIZE_TYPE__
198 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
199 # define DRM_SIZE_T unsigned long
203 * DRM_IOCTL_VERSION ioctl argument type.
205 * \sa drmGetVersion().
208 int version_major; /**< Major version */
209 int version_minor; /**< Minor version */
210 int version_patchlevel; /**< Patch level */
211 DRM_SIZE_T name_len; /**< Length of name buffer */
212 char __user *name; /**< Name of driver */
213 DRM_SIZE_T date_len; /**< Length of date buffer */
214 char __user *date; /**< User-space buffer to hold date */
215 DRM_SIZE_T desc_len; /**< Length of desc buffer */
216 char __user *desc; /**< User-space buffer to hold desc */
220 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
222 * \sa drmGetBusid() and drmSetBusId().
225 DRM_SIZE_T unique_len; /**< Length of unique */
226 char __user *unique; /**< Unique name for driver instantiation */
232 int count; /**< Length of user-space structures */
233 struct drm_version __user *version;
241 * DRM_IOCTL_CONTROL ioctl argument type.
243 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
256 * Type of memory to map.
259 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
260 _DRM_REGISTERS = 1, /**< no caching, no core dump */
261 _DRM_SHM = 2, /**< shared, cached */
262 _DRM_AGP = 3, /**< AGP/GART */
263 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
264 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
269 * Memory mapping flags.
272 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
273 _DRM_READ_ONLY = 0x02,
274 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
275 _DRM_KERNEL = 0x08, /**< kernel requires access */
276 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
277 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
278 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
281 struct drm_ctx_priv_map {
282 unsigned int ctx_id; /**< Context requesting private mapping */
283 void *handle; /**< Handle of map */
287 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
293 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
294 unsigned long size; /**< Requested physical size (bytes) */
295 enum drm_map_type type; /**< Type of memory to map */
296 enum drm_map_flags flags; /**< Flags */
297 void *handle; /**< User-space: "Handle" to pass to mmap() */
298 /**< Kernel-space: kernel-virtual address */
299 int mtrr; /**< MTRR slot used */
304 * DRM_IOCTL_GET_CLIENT ioctl argument type.
307 int idx; /**< Which client desired? */
308 int auth; /**< Is client authenticated? */
309 unsigned long pid; /**< Process ID */
310 unsigned long uid; /**< User ID */
311 unsigned long magic; /**< Magic */
312 unsigned long iocs; /**< Ioctl count */
322 _DRM_STAT_VALUE, /**< Generic value */
323 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
324 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
326 _DRM_STAT_IRQ, /**< IRQ */
327 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
328 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
329 _DRM_STAT_DMA, /**< DMA */
330 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
331 _DRM_STAT_MISSED /**< Missed DMA opportunity */
332 /* Add to the *END* of the list */
336 * DRM_IOCTL_GET_STATS ioctl argument type.
342 enum drm_stat_type type;
347 * Hardware locking flags.
349 enum drm_lock_flags {
350 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
351 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
352 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
353 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
354 /* These *HALT* flags aren't supported yet
355 -- they will be used to support the
356 full-screen DGA-like mode. */
357 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
358 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
362 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
364 * \sa drmGetLock() and drmUnlock().
368 enum drm_lock_flags flags;
375 * These values \e must match xf86drm.h.
380 /* Flags for DMA buffer dispatch */
381 _DRM_DMA_BLOCK = 0x01, /**<
382 * Block until buffer dispatched.
384 * \note The buffer may not yet have
385 * been processed by the hardware --
386 * getting a hardware lock with the
387 * hardware quiescent will ensure
388 * that the buffer has been
391 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
392 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
394 /* Flags for DMA buffer request */
395 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
396 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
397 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
401 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
405 struct drm_buf_desc {
406 int count; /**< Number of buffers of this size */
407 int size; /**< Size in bytes */
408 int low_mark; /**< Low water mark */
409 int high_mark; /**< High water mark */
411 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
412 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
413 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
414 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
415 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
417 unsigned long agp_start; /**<
418 * Start address of where the AGP buffers are
419 * in the AGP aperture
424 * DRM_IOCTL_INFO_BUFS ioctl argument type.
426 struct drm_buf_info {
427 int count; /**< Number of buffers described in list */
428 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
432 * DRM_IOCTL_FREE_BUFS ioctl argument type.
434 struct drm_buf_free {
445 int idx; /**< Index into the master buffer list */
446 int total; /**< Buffer size */
447 int used; /**< Amount of buffer in use (for DMA) */
448 void __user *address; /**< Address of buffer */
452 * DRM_IOCTL_MAP_BUFS ioctl argument type.
455 int count; /**< Length of the buffer list */
456 #if defined(__cplusplus)
457 void __user *c_virtual;
459 void __user *virtual; /**< Mmap'd area in user-virtual */
461 struct drm_buf_pub __user *list; /**< Buffer information */
465 * DRM_IOCTL_DMA ioctl argument type.
467 * Indices here refer to the offset into the buffer list in drm_buf_get.
472 int context; /**< Context handle */
473 int send_count; /**< Number of buffers to send */
474 int __user *send_indices; /**< List of handles to buffers */
475 int __user *send_sizes; /**< Lengths of data to send */
476 enum drm_dma_flags flags; /**< Flags */
477 int request_count; /**< Number of buffers requested */
478 int request_size; /**< Desired size for buffers */
479 int __user *request_indices; /**< Buffer information */
480 int __user *request_sizes;
481 int granted_count; /**< Number of buffers granted */
485 _DRM_CONTEXT_PRESERVED = 0x01,
486 _DRM_CONTEXT_2DONLY = 0x02
490 * DRM_IOCTL_ADD_CTX ioctl argument type.
492 * \sa drmCreateContext() and drmDestroyContext().
495 drm_context_t handle;
496 enum drm_ctx_flags flags;
500 * DRM_IOCTL_RES_CTX ioctl argument type.
504 struct drm_ctx __user *contexts;
508 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
511 drm_drawable_t handle;
515 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
518 DRM_DRAWABLE_CLIPRECTS,
519 } drm_drawable_info_type_t;
521 struct drm_update_draw {
522 drm_drawable_t handle;
525 unsigned long long data;
529 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
536 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
538 * \sa drmGetInterruptFromBusID().
540 struct drm_irq_busid {
541 int irq; /**< IRQ number */
542 int busnum; /**< bus number */
543 int devnum; /**< device number */
544 int funcnum; /**< function number */
547 enum drm_vblank_seq_type {
548 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
549 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
550 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
551 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
552 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
553 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
556 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
557 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
558 _DRM_VBLANK_NEXTONMISS)
560 struct drm_wait_vblank_request {
561 enum drm_vblank_seq_type type;
562 unsigned int sequence;
563 unsigned long signal;
566 struct drm_wait_vblank_reply {
567 enum drm_vblank_seq_type type;
568 unsigned int sequence;
574 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
576 * \sa drmWaitVBlank().
578 union drm_wait_vblank {
579 struct drm_wait_vblank_request request;
580 struct drm_wait_vblank_reply reply;
584 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
586 * \sa drmAgpEnable().
588 struct drm_agp_mode {
589 unsigned long mode; /**< AGP mode */
593 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
595 * \sa drmAgpAlloc() and drmAgpFree().
597 struct drm_agp_buffer {
598 unsigned long size; /**< In bytes -- will round to page boundary */
599 unsigned long handle; /**< Used for binding / unbinding */
600 unsigned long type; /**< Type of memory to allocate */
601 unsigned long physical; /**< Physical used by i810 */
605 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
607 * \sa drmAgpBind() and drmAgpUnbind().
609 struct drm_agp_binding {
610 unsigned long handle; /**< From drm_agp_buffer */
611 unsigned long offset; /**< In bytes -- will round to page boundary */
615 * DRM_IOCTL_AGP_INFO ioctl argument type.
617 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
618 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
619 * drmAgpVendorId() and drmAgpDeviceId().
621 struct drm_agp_info {
622 int agp_version_major;
623 int agp_version_minor;
625 unsigned long aperture_base; /**< physical address */
626 unsigned long aperture_size; /**< bytes */
627 unsigned long memory_allowed; /**< bytes */
628 unsigned long memory_used;
630 /** \name PCI information */
632 unsigned short id_vendor;
633 unsigned short id_device;
638 * DRM_IOCTL_SG_ALLOC ioctl argument type.
640 struct drm_scatter_gather {
641 unsigned long size; /**< In bytes -- will round to page boundary */
642 unsigned long handle; /**< Used for mapping / unmapping */
646 * DRM_IOCTL_SET_VERSION ioctl argument type.
648 struct drm_set_version {
656 #define DRM_FENCE_FLAG_EMIT 0x00000001
657 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
658 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
659 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
661 /* Reserved for driver use */
662 #define DRM_FENCE_MASK_DRIVER 0xFF000000
664 #define DRM_FENCE_TYPE_EXE 0x00000001
666 struct drm_fence_arg {
671 unsigned int signaled;
673 uint64_t expand_pad[3]; /*Future expansion */
676 /* Buffer permissions, referring to how the GPU uses the buffers.
677 * these translate to fence types used for the buffers.
678 * Typically a texture buffer is read, A destination buffer is write and
679 * a command (batch-) buffer is exe. Can be or-ed together.
682 #define DRM_BO_FLAG_READ (1ULL << 0)
683 #define DRM_BO_FLAG_WRITE (1ULL << 1)
684 #define DRM_BO_FLAG_EXE (1ULL << 2)
687 * Status flags. Can be read to determine the actual state of a buffer.
688 * Can also be set in the buffer mask before validation.
692 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
693 * available to root and must be manually removed before buffer manager shutdown
697 #define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
700 * Mask: Require that the buffer is placed in mappable memory when validated.
701 * If not set the buffer may or may not be in mappable memory when validated.
702 * Flags: If set, the buffer is in mappable memory.
704 #define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
706 /* Mask: The buffer should be shareable with other processes.
707 * Flags: The buffer is shareable with other processes.
709 #define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
711 /* Mask: If set, place the buffer in cache-coherent memory if available.
712 * If clear, never place the buffer in cache coherent memory if validated.
713 * Flags: The buffer is currently in cache-coherent memory.
715 #define DRM_BO_FLAG_CACHED (1ULL << 7)
717 /* Mask: Make sure that every time this buffer is validated,
718 * it ends up on the same location provided that the memory mask is the same.
719 * The buffer will also not be evicted when claiming space for
720 * other buffers. Basically a pinned buffer but it may be thrown out as
721 * part of buffer manager shutdown or locking.
722 * Flags: Acknowledge.
724 #define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
726 /* Mask: Make sure the buffer is in cached memory when mapped for reading.
727 * Flags: Acknowledge.
729 #define DRM_BO_FLAG_READ_CACHED (1ULL << 19)
731 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
732 * Flags: Acknowledge.
734 #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
737 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
738 * Flags: Acknowledge.
740 #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
743 * Memory type flags that can be or'ed together in the mask, but only
744 * one appears in flags.
748 #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
749 /* Translation table memory */
750 #define DRM_BO_FLAG_MEM_TT (1ULL << 25)
752 #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
753 /* Up to the driver to define. */
754 #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
755 #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
756 #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
757 #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
758 #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
759 /* We can add more of these now with a 64-bit flag type */
761 /* Memory flag mask */
762 #define DRM_BO_MASK_MEM 0x00000000FF000000ULL
763 #define DRM_BO_MASK_MEMTYPE 0x00000000FF0000A0ULL
765 /* Driver-private flags */
766 #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
768 /* Don't block on validate and map */
769 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
770 /* Don't place this buffer on the unfenced list.*/
771 #define DRM_BO_HINT_DONT_FENCE 0x00000004
772 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
773 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
775 #define DRM_BO_INIT_MAGIC 0xfe769812
776 #define DRM_BO_INIT_MAJOR 0
777 #define DRM_BO_INIT_MINOR 1
784 drm_bo_type_kernel, /* for initial kernel allocations */
787 struct drm_bo_info_req {
792 unsigned int fence_class;
796 struct drm_bo_create_req {
799 uint64_t buffer_start;
801 unsigned int page_alignment;
802 enum drm_bo_type type;
806 struct drm_bo_op_req {
812 unsigned int arg_handle;
813 struct drm_bo_info_req bo_req;
820 #define DRM_BO_REP_BUSY 0x00000001
822 struct drm_bo_info_rep {
828 uint64_t buffer_start;
830 unsigned int fence_flags;
831 unsigned int rep_flags;
832 unsigned int page_alignment;
833 unsigned int desired_tile_stride;
834 unsigned int hw_tile_stride;
835 unsigned int tile_info;
837 uint64_t expand_pad[4]; /*Future expansion */
840 struct drm_bo_arg_rep {
841 struct drm_bo_info_rep bo_info;
846 struct drm_bo_create_arg {
848 struct drm_bo_create_req req;
849 struct drm_bo_info_rep rep;
853 struct drm_bo_handle_arg {
857 struct drm_bo_reference_info_arg {
859 struct drm_bo_handle_arg req;
860 struct drm_bo_info_rep rep;
864 struct drm_bo_map_wait_idle_arg {
866 struct drm_bo_info_req req;
867 struct drm_bo_info_rep rep;
871 struct drm_bo_op_arg {
874 struct drm_bo_op_req req;
875 struct drm_bo_arg_rep rep;
881 #define DRM_BO_MEM_LOCAL 0
882 #define DRM_BO_MEM_TT 1
883 #define DRM_BO_MEM_VRAM 2
884 #define DRM_BO_MEM_PRIV0 3
885 #define DRM_BO_MEM_PRIV1 4
886 #define DRM_BO_MEM_PRIV2 5
887 #define DRM_BO_MEM_PRIV3 6
888 #define DRM_BO_MEM_PRIV4 7
890 #define DRM_BO_MEM_TYPES 8 /* For now. */
892 struct drm_mm_type_arg {
893 unsigned int mem_type;
896 struct drm_mm_init_arg {
900 unsigned int mem_type;
906 * \name Ioctls Definitions
910 #define DRM_IOCTL_BASE 'd'
911 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
912 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
913 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
914 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
916 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
917 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
918 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
919 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
920 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
921 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
922 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
923 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
925 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
926 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
927 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
928 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
929 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
930 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
931 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
932 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
933 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
934 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
935 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
937 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
939 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
940 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
942 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
943 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
944 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
945 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
946 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
947 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
948 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
949 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
950 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
951 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
952 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
953 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
954 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
956 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
957 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
958 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
959 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
960 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
961 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
962 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
963 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
965 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
966 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
968 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
970 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
972 #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
973 #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
974 #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
975 #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
977 #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
978 #define DRM_IOCTL_FENCE_DESTROY DRM_IOWR(0xc5, struct drm_fence_arg)
979 #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
980 #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
981 #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
982 #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
983 #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
984 #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
985 #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
987 #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
988 #define DRM_IOCTL_BO_DESTROY DRM_IOWR(0xce, struct drm_bo_handle_arg)
989 #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
990 #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
991 #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
992 #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
993 #define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg)
994 #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
995 #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1001 * Device specific ioctls should only be in their respective headers
1002 * The device specific ioctl range is from 0x40 to 0x99.
1003 * Generic IOCTLS restart at 0xA0.
1005 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1006 * drmCommandReadWrite().
1008 #define DRM_COMMAND_BASE 0x40
1009 #define DRM_COMMAND_END 0xA0
1012 #if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)
1013 typedef struct drm_clip_rect drm_clip_rect_t;
1014 typedef struct drm_drawable_info drm_drawable_info_t;
1015 typedef struct drm_tex_region drm_tex_region_t;
1016 typedef struct drm_hw_lock drm_hw_lock_t;
1017 typedef struct drm_version drm_version_t;
1018 typedef struct drm_unique drm_unique_t;
1019 typedef struct drm_list drm_list_t;
1020 typedef struct drm_block drm_block_t;
1021 typedef struct drm_control drm_control_t;
1022 typedef enum drm_map_type drm_map_type_t;
1023 typedef enum drm_map_flags drm_map_flags_t;
1024 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1025 typedef struct drm_map drm_map_t;
1026 typedef struct drm_client drm_client_t;
1027 typedef enum drm_stat_type drm_stat_type_t;
1028 typedef struct drm_stats drm_stats_t;
1029 typedef enum drm_lock_flags drm_lock_flags_t;
1030 typedef struct drm_lock drm_lock_t;
1031 typedef enum drm_dma_flags drm_dma_flags_t;
1032 typedef struct drm_buf_desc drm_buf_desc_t;
1033 typedef struct drm_buf_info drm_buf_info_t;
1034 typedef struct drm_buf_free drm_buf_free_t;
1035 typedef struct drm_buf_pub drm_buf_pub_t;
1036 typedef struct drm_buf_map drm_buf_map_t;
1037 typedef struct drm_dma drm_dma_t;
1038 typedef union drm_wait_vblank drm_wait_vblank_t;
1039 typedef struct drm_agp_mode drm_agp_mode_t;
1040 typedef enum drm_ctx_flags drm_ctx_flags_t;
1041 typedef struct drm_ctx drm_ctx_t;
1042 typedef struct drm_ctx_res drm_ctx_res_t;
1043 typedef struct drm_draw drm_draw_t;
1044 typedef struct drm_update_draw drm_update_draw_t;
1045 typedef struct drm_auth drm_auth_t;
1046 typedef struct drm_irq_busid drm_irq_busid_t;
1047 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1048 typedef struct drm_agp_buffer drm_agp_buffer_t;
1049 typedef struct drm_agp_binding drm_agp_binding_t;
1050 typedef struct drm_agp_info drm_agp_info_t;
1051 typedef struct drm_scatter_gather drm_scatter_gather_t;
1052 typedef struct drm_set_version drm_set_version_t;
1054 typedef struct drm_fence_arg drm_fence_arg_t;
1055 typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1056 typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1057 typedef enum drm_bo_type drm_bo_type_t;