1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
38 #if defined(__linux__)
39 #include <asm/ioctl.h> /* For _IO* macros */
40 #define DRM_IOCTL_NR(n) _IOC_NR(n)
41 #elif defined(__FreeBSD__)
42 #include <sys/ioccom.h>
43 #define DRM_IOCTL_NR(n) ((n) & 0xff)
46 #define DRM_PROC_DEVICES "/proc/devices"
47 #define DRM_PROC_MISC "/proc/misc"
48 #define DRM_PROC_DRM "/proc/drm"
49 #define DRM_DEV_DRM "/dev/drm"
50 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
55 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
56 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
57 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
58 #define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */
60 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
61 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
62 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
63 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
64 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
66 typedef unsigned long drm_handle_t;
67 typedef unsigned int drm_context_t;
68 typedef unsigned int drm_drawable_t;
69 typedef unsigned int drm_magic_t;
71 /* Warning: If you change this structure, make sure you change
72 * XF86DRIClipRectRec in the server as well */
74 typedef struct drm_clip_rect {
81 /* Seperate include files for the i810/mga/r128 specific structures */
87 typedef struct drm_version {
88 int version_major; /* Major version */
89 int version_minor; /* Minor version */
90 int version_patchlevel;/* Patch level */
91 size_t name_len; /* Length of name buffer */
92 char *name; /* Name of driver */
93 size_t date_len; /* Length of date buffer */
94 char *date; /* User-space buffer to hold date */
95 size_t desc_len; /* Length of desc buffer */
96 char *desc; /* User-space buffer to hold desc */
99 typedef struct drm_unique {
100 size_t unique_len; /* Length of unique */
101 char *unique; /* Unique name for driver instantiation */
104 typedef struct drm_list {
105 int count; /* Length of user-space structures */
106 drm_version_t *version;
109 typedef struct drm_block {
113 typedef struct drm_control {
123 typedef enum drm_map_type {
124 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
125 _DRM_REGISTERS = 1, /* no caching, no core dump */
126 _DRM_SHM = 2, /* shared, cached */
127 _DRM_AGP = 3 /* AGP/GART */
130 typedef enum drm_map_flags {
131 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
132 _DRM_READ_ONLY = 0x02,
133 _DRM_LOCKED = 0x04, /* shared, cached, locked */
134 _DRM_KERNEL = 0x08, /* kernel requires access */
135 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
136 _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */
139 typedef struct drm_map {
140 unsigned long offset; /* Requested physical address (0 for SAREA)*/
141 unsigned long size; /* Requested physical size (bytes) */
142 drm_map_type_t type; /* Type of memory to map */
143 drm_map_flags_t flags; /* Flags */
144 void *handle; /* User-space: "Handle" to pass to mmap */
145 /* Kernel-space: kernel-virtual address */
146 int mtrr; /* MTRR slot used */
150 typedef enum drm_lock_flags {
151 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
152 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
153 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
154 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
155 /* These *HALT* flags aren't supported yet
156 -- they will be used to support the
157 full-screen DGA-like mode. */
158 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
159 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
162 typedef struct drm_lock {
164 drm_lock_flags_t flags;
167 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
168 /* Flags for DMA buffer dispatch */
169 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
170 Note, the buffer may not yet have
171 been processed by the hardware --
172 getting a hardware lock with the
173 hardware quiescent will ensure
174 that the buffer has been
176 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
177 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
179 /* Flags for DMA buffer request */
180 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
181 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
182 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
185 typedef struct drm_buf_desc {
186 int count; /* Number of buffers of this size */
187 int size; /* Size in bytes */
188 int low_mark; /* Low water mark */
189 int high_mark; /* High water mark */
191 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
192 _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */
194 unsigned long agp_start; /* Start address of where the agp buffers
195 * are in the agp aperture */
198 typedef struct drm_buf_info {
199 int count; /* Entries in list */
200 drm_buf_desc_t *list;
203 typedef struct drm_buf_free {
208 typedef struct drm_buf_pub {
209 int idx; /* Index into master buflist */
210 int total; /* Buffer size */
211 int used; /* Amount of buffer in use (for DMA) */
212 void *address; /* Address of buffer */
215 typedef struct drm_buf_map {
216 int count; /* Length of buflist */
217 void *virtual; /* Mmaped area in user-virtual */
218 drm_buf_pub_t *list; /* Buffer information */
221 typedef struct drm_dma {
222 /* Indices here refer to the offset into
223 buflist in drm_buf_get_t. */
224 int context; /* Context handle */
225 int send_count; /* Number of buffers to send */
226 int *send_indices; /* List of handles to buffers */
227 int *send_sizes; /* Lengths of data to send */
228 drm_dma_flags_t flags; /* Flags */
229 int request_count; /* Number of buffers requested */
230 int request_size; /* Desired size for buffers */
231 int *request_indices; /* Buffer information */
233 int granted_count; /* Number of buffers granted */
237 _DRM_CONTEXT_PRESERVED = 0x01,
238 _DRM_CONTEXT_2DONLY = 0x02
241 typedef struct drm_ctx {
242 drm_context_t handle;
243 drm_ctx_flags_t flags;
246 typedef struct drm_ctx_res {
251 typedef struct drm_draw {
252 drm_drawable_t handle;
255 typedef struct drm_auth {
259 typedef struct drm_irq_busid {
266 typedef struct drm_agp_mode {
270 /* For drm_agp_alloc -- allocated a buffer */
271 typedef struct drm_agp_buffer {
272 unsigned long size; /* In bytes -- will round to page boundary */
273 unsigned long handle; /* Used for BIND/UNBIND ioctls */
274 unsigned long type; /* Type of memory to allocate */
275 unsigned long physical; /* Physical used by i810 */
278 /* For drm_agp_bind */
279 typedef struct drm_agp_binding {
280 unsigned long handle; /* From drm_agp_buffer */
281 unsigned long offset; /* In bytes -- will round to page boundary */
284 typedef struct drm_agp_info {
285 int agp_version_major;
286 int agp_version_minor;
288 unsigned long aperture_base; /* physical address */
289 unsigned long aperture_size; /* bytes */
290 unsigned long memory_allowed; /* bytes */
291 unsigned long memory_used;
293 /* PCI information */
294 unsigned short id_vendor;
295 unsigned short id_device;
298 #define DRM_IOCTL_BASE 'd'
299 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
300 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
301 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
302 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
305 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
306 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
307 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
308 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
310 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
311 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
312 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
313 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
314 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
315 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
316 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
317 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
318 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
319 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
320 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
322 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
323 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
324 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
325 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
326 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
327 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
328 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
329 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
330 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
331 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
332 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
333 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
334 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
336 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
337 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
338 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
339 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
340 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
341 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
342 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
343 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
345 /* Mga specific ioctls */
346 #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
347 #define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
348 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
349 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
350 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
351 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
352 #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
354 /* I810 specific ioctls */
355 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
356 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
357 #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
358 #define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
359 #define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)
360 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
361 #define DRM_IOCTL_I810_SWAP DRM_IO ( 0x46)
362 #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
363 #define DRM_IOCTL_I810_DOCOPY DRM_IO ( 0x48)
365 /* Rage 128 specific ioctls */
366 #define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
367 #define DRM_IOCTL_R128_RESET DRM_IO( 0x41)
368 #define DRM_IOCTL_R128_FLUSH DRM_IO( 0x42)
369 #define DRM_IOCTL_R128_IDLE DRM_IO( 0x43)
370 #define DRM_IOCTL_R128_PACKET DRM_IOW( 0x44, drm_r128_packet_t)
371 #define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x45, drm_r128_vertex_t)
373 /* SiS specific ioctls */
374 #define SIS_IOCTL_FB_ALLOC DRM_IOWR( 0x44, drm_sis_mem_t)
375 #define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
376 #define SIS_IOCTL_AGP_INIT DRM_IOWR( 0x53, drm_sis_agp_t)
377 #define SIS_IOCTL_AGP_ALLOC DRM_IOWR( 0x54, drm_sis_mem_t)
378 #define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
379 #define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
380 #define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
381 #define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)