1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
38 #include <linux/config.h>
39 #if defined(__linux__)
40 #include <asm/ioctl.h> /* For _IO* macros */
41 #define DRM_IOCTL_NR(n) _IOC_NR(n)
42 #elif defined(__FreeBSD__)
43 #include <sys/ioccom.h>
44 #define DRM_IOCTL_NR(n) ((n) & 0xff)
48 #define DRM_MAX_MINOR 15
49 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
50 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
51 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
52 #define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */
54 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
55 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
56 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
57 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
58 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
60 typedef unsigned long drm_handle_t;
61 typedef unsigned int drm_context_t;
62 typedef unsigned int drm_drawable_t;
63 typedef unsigned int drm_magic_t;
65 /* Warning: If you change this structure, make sure you change
66 * XF86DRIClipRectRec in the server as well */
68 typedef struct drm_clip_rect {
75 typedef struct drm_tex_region {
79 unsigned char padding;
83 /* Seperate include files for the i810/mga/r128 specific structures */
87 #include "radeon_drm.h"
92 typedef struct drm_version {
93 int version_major; /* Major version */
94 int version_minor; /* Minor version */
95 int version_patchlevel;/* Patch level */
96 size_t name_len; /* Length of name buffer */
97 char *name; /* Name of driver */
98 size_t date_len; /* Length of date buffer */
99 char *date; /* User-space buffer to hold date */
100 size_t desc_len; /* Length of desc buffer */
101 char *desc; /* User-space buffer to hold desc */
104 typedef struct drm_unique {
105 size_t unique_len; /* Length of unique */
106 char *unique; /* Unique name for driver instantiation */
109 typedef struct drm_list {
110 int count; /* Length of user-space structures */
111 drm_version_t *version;
114 typedef struct drm_block {
118 typedef struct drm_control {
128 typedef enum drm_map_type {
129 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
130 _DRM_REGISTERS = 1, /* no caching, no core dump */
131 _DRM_SHM = 2, /* shared, cached */
132 _DRM_AGP = 3 /* AGP/GART */
135 typedef enum drm_map_flags {
136 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
137 _DRM_READ_ONLY = 0x02,
138 _DRM_LOCKED = 0x04, /* shared, cached, locked */
139 _DRM_KERNEL = 0x08, /* kernel requires access */
140 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
141 _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */
144 typedef struct drm_map {
145 unsigned long offset; /* Requested physical address (0 for SAREA)*/
146 unsigned long size; /* Requested physical size (bytes) */
147 drm_map_type_t type; /* Type of memory to map */
148 drm_map_flags_t flags; /* Flags */
149 void *handle; /* User-space: "Handle" to pass to mmap */
150 /* Kernel-space: kernel-virtual address */
151 int mtrr; /* MTRR slot used */
155 typedef struct drm_client {
156 int idx; /* Which client desired? */
157 int auth; /* Is client authenticated? */
158 unsigned long pid; /* Process id */
159 unsigned long uid; /* User id */
160 unsigned long magic; /* Magic */
161 unsigned long iocs; /* Ioctl count */
171 _DRM_STAT_VALUE, /* Generic value */
172 _DRM_STAT_BYTE, /* Generic byte counter (1024bytes/K) */
173 _DRM_STAT_COUNT, /* Generic non-byte counter (1000/k) */
175 _DRM_STAT_IRQ, /* IRQ */
176 _DRM_STAT_PRIMARY, /* Primary DMA bytes */
177 _DRM_STAT_SECONDARY, /* Secondary DMA bytes */
178 _DRM_STAT_DMA, /* DMA */
179 _DRM_STAT_SPECIAL, /* Special DMA (e.g., priority or polled) */
180 _DRM_STAT_MISSED /* Missed DMA opportunity */
182 /* Add to the *END* of the list */
185 typedef struct drm_stats {
189 drm_stat_type_t type;
193 typedef enum drm_lock_flags {
194 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
195 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
196 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
197 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
198 /* These *HALT* flags aren't supported yet
199 -- they will be used to support the
200 full-screen DGA-like mode. */
201 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
202 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
205 typedef struct drm_lock {
207 drm_lock_flags_t flags;
210 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
211 /* Flags for DMA buffer dispatch */
212 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
213 Note, the buffer may not yet have
214 been processed by the hardware --
215 getting a hardware lock with the
216 hardware quiescent will ensure
217 that the buffer has been
219 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
220 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
222 /* Flags for DMA buffer request */
223 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
224 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
225 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
228 typedef struct drm_buf_desc {
229 int count; /* Number of buffers of this size */
230 int size; /* Size in bytes */
231 int low_mark; /* Low water mark */
232 int high_mark; /* High water mark */
234 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
235 _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */
237 unsigned long agp_start; /* Start address of where the agp buffers
238 * are in the agp aperture */
241 typedef struct drm_buf_info {
242 int count; /* Entries in list */
243 drm_buf_desc_t *list;
246 typedef struct drm_buf_free {
251 typedef struct drm_buf_pub {
252 int idx; /* Index into master buflist */
253 int total; /* Buffer size */
254 int used; /* Amount of buffer in use (for DMA) */
255 void *address; /* Address of buffer */
258 typedef struct drm_buf_map {
259 int count; /* Length of buflist */
260 void *virtual; /* Mmaped area in user-virtual */
261 drm_buf_pub_t *list; /* Buffer information */
264 typedef struct drm_dma {
265 /* Indices here refer to the offset into
266 buflist in drm_buf_get_t. */
267 int context; /* Context handle */
268 int send_count; /* Number of buffers to send */
269 int *send_indices; /* List of handles to buffers */
270 int *send_sizes; /* Lengths of data to send */
271 drm_dma_flags_t flags; /* Flags */
272 int request_count; /* Number of buffers requested */
273 int request_size; /* Desired size for buffers */
274 int *request_indices; /* Buffer information */
276 int granted_count; /* Number of buffers granted */
280 _DRM_CONTEXT_PRESERVED = 0x01,
281 _DRM_CONTEXT_2DONLY = 0x02
284 typedef struct drm_ctx {
285 drm_context_t handle;
286 drm_ctx_flags_t flags;
289 typedef struct drm_ctx_res {
294 typedef struct drm_draw {
295 drm_drawable_t handle;
298 typedef struct drm_auth {
302 typedef struct drm_irq_busid {
309 typedef struct drm_agp_mode {
313 /* For drm_agp_alloc -- allocated a buffer */
314 typedef struct drm_agp_buffer {
315 unsigned long size; /* In bytes -- will round to page boundary */
316 unsigned long handle; /* Used for BIND/UNBIND ioctls */
317 unsigned long type; /* Type of memory to allocate */
318 unsigned long physical; /* Physical used by i810 */
321 /* For drm_agp_bind */
322 typedef struct drm_agp_binding {
323 unsigned long handle; /* From drm_agp_buffer */
324 unsigned long offset; /* In bytes -- will round to page boundary */
327 typedef struct drm_agp_info {
328 int agp_version_major;
329 int agp_version_minor;
331 unsigned long aperture_base; /* physical address */
332 unsigned long aperture_size; /* bytes */
333 unsigned long memory_allowed; /* bytes */
334 unsigned long memory_used;
336 /* PCI information */
337 unsigned short id_vendor;
338 unsigned short id_device;
341 #define DRM_IOCTL_BASE 'd'
342 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
343 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
344 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
345 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
348 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
349 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
350 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
351 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
352 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
353 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
354 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
356 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
357 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
358 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
359 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
360 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
361 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
362 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
363 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
364 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
365 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
366 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
368 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
369 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
370 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
371 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
372 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
373 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
374 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
375 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
376 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
377 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
378 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
379 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
380 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
382 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
383 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
384 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
385 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
386 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
387 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
388 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
389 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
391 /* MGA specific ioctls */
392 #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
393 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t)
394 #define DRM_IOCTL_MGA_RESET DRM_IO( 0x42)
395 #define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43)
396 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t)
397 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t)
398 #define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t)
399 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t)
400 #define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t)
402 /* i810 specific ioctls */
403 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
404 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
405 #define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t)
406 #define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43)
407 #define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44)
408 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t)
409 #define DRM_IOCTL_I810_SWAP DRM_IO( 0x46)
410 #define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t)
411 #define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48)
413 /* Rage 128 specific ioctls */
414 #define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t)
415 #define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41)
416 #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t)
417 #define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
418 #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
419 #define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
420 #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x47, drm_r128_fullscreen_t)
421 #define DRM_IOCTL_R128_SWAP DRM_IO( 0x48)
422 #define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x49, drm_r128_clear_t)
423 #define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x4a, drm_r128_vertex_t)
424 #define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4b, drm_r128_indices_t)
425 #define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4c, drm_r128_blit_t)
426 #define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4d, drm_r128_depth_t)
427 #define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4e, drm_r128_stipple_t)
428 #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
430 /* Radeon specific ioctls */
431 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
432 #define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
433 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
434 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
435 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
436 #define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
437 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
438 #define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
439 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
440 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
441 #define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
442 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4b, drm_radeon_texture_t)
443 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
444 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
446 #ifdef CONFIG_DRM_SIS
447 /* SiS specific ioctls */
448 #define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t)
449 #define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t)
450 #define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t)
451 #define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t)
452 #define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t)
453 #define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
454 #define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49)
455 #define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50)