3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
65 #if defined(__linux__)
66 #include <linux/config.h>
67 #include <asm/ioctl.h> /* For _IO* macros */
68 #define DRM_IOCTL_NR(n) _IOC_NR(n)
69 #define DRM_IOC_VOID _IOC_NONE
70 #define DRM_IOC_READ _IOC_READ
71 #define DRM_IOC_WRITE _IOC_WRITE
72 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
73 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
74 #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
75 #if defined(__FreeBSD__) && defined(IN_MODULE)
76 /* Prevent name collision when including sys/ioccom.h */
78 #include <sys/ioccom.h>
79 #define ioctl(a,b,c) xf86ioctl(a,b,c)
81 #include <sys/ioccom.h>
82 #endif /* __FreeBSD__ && xf86ioctl */
83 #define DRM_IOCTL_NR(n) ((n) & 0xff)
84 #define DRM_IOC_VOID IOC_VOID
85 #define DRM_IOC_READ IOC_OUT
86 #define DRM_IOC_WRITE IOC_IN
87 #define DRM_IOC_READWRITE IOC_INOUT
88 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
91 #define XFREE86_VERSION(major,minor,patch,snap) \
92 ((major << 16) | (minor << 8) | patch)
94 #ifndef CONFIG_XFREE86_VERSION
95 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
98 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
99 #define DRM_PROC_DEVICES "/proc/devices"
100 #define DRM_PROC_MISC "/proc/misc"
101 #define DRM_PROC_DRM "/proc/drm"
102 #define DRM_DEV_DRM "/dev/drm"
103 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
104 #define DRM_DEV_UID 0
105 #define DRM_DEV_GID 0
108 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
112 #if defined(__linux__) || defined(__NetBSD__)
113 #define DRM_MAJOR 226
115 #define DRM_MAX_MINOR 255
117 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
118 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
119 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
120 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
122 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
123 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
124 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
125 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
126 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
128 typedef unsigned long drm_handle_t; /**< To mapped regions */
129 typedef unsigned int drm_context_t; /**< GLXContext handle */
130 typedef unsigned int drm_drawable_t;
131 typedef unsigned int drm_magic_t; /**< Magic for authentication */
136 * \warning If you change this structure, make sure you change
137 * XF86DRIClipRectRec in the server as well
139 * \note KW: Actually it's illegal to change either for
140 * backwards-compatibility reasons.
142 typedef struct drm_clip_rect {
152 typedef struct drm_tex_region {
155 unsigned char in_use;
156 unsigned char padding;
163 * The lock structure is a simple cache-line aligned integer. To avoid
164 * processor bus contention on a multiprocessor system, there should not be any
165 * other data stored in the same cache line.
167 typedef struct drm_hw_lock {
168 __volatile__ unsigned int lock; /**< lock variable */
169 char padding[60]; /**< Pad to cache line */
172 /* This is beyond ugly, and only works on GCC. However, it allows me to use
173 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
174 * fix is to use uint32_t instead of size_t, but that fix will break existing
175 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
176 * eventually happen, though. I chose 'unsigned long' to be the fallback type
177 * because that works on all the platforms I know about. Hopefully, the
178 * real fix will happen before that bites us.
182 # define DRM_SIZE_T __SIZE_TYPE__
184 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
185 # define DRM_SIZE_T unsigned long
189 * DRM_IOCTL_VERSION ioctl argument type.
191 * \sa drmGetVersion().
193 typedef struct drm_version {
194 int version_major; /**< Major version */
195 int version_minor; /**< Minor version */
196 int version_patchlevel; /**< Patch level */
197 DRM_SIZE_T name_len; /**< Length of name buffer */
198 char __user *name; /**< Name of driver */
199 DRM_SIZE_T date_len; /**< Length of date buffer */
200 char __user *date; /**< User-space buffer to hold date */
201 DRM_SIZE_T desc_len; /**< Length of desc buffer */
202 char __user *desc; /**< User-space buffer to hold desc */
206 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
208 * \sa drmGetBusid() and drmSetBusId().
210 typedef struct drm_unique {
211 DRM_SIZE_T unique_len; /**< Length of unique */
212 char __user *unique; /**< Unique name for driver instantiation */
217 typedef struct drm_list {
218 int count; /**< Length of user-space structures */
219 drm_version_t __user *version;
222 typedef struct drm_block {
227 * DRM_IOCTL_CONTROL ioctl argument type.
229 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
231 typedef struct drm_control {
242 * Type of memory to map.
244 typedef enum drm_map_type {
245 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
246 _DRM_REGISTERS = 1, /**< no caching, no core dump */
247 _DRM_SHM = 2, /**< shared, cached */
248 _DRM_AGP = 3, /**< AGP/GART */
249 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
250 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
254 * Memory mapping flags.
256 typedef enum drm_map_flags {
257 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
258 _DRM_READ_ONLY = 0x02,
259 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
260 _DRM_KERNEL = 0x08, /**< kernel requires access */
261 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
262 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
263 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
266 typedef struct drm_ctx_priv_map {
267 unsigned int ctx_id; /**< Context requesting private mapping */
268 void *handle; /**< Handle of map */
269 } drm_ctx_priv_map_t;
272 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
277 typedef struct drm_map {
278 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
279 unsigned long size; /**< Requested physical size (bytes) */
280 drm_map_type_t type; /**< Type of memory to map */
281 drm_map_flags_t flags; /**< Flags */
282 void *handle; /**< User-space: "Handle" to pass to mmap() */
283 /**< Kernel-space: kernel-virtual address */
284 int mtrr; /**< MTRR slot used */
289 * DRM_IOCTL_GET_CLIENT ioctl argument type.
291 typedef struct drm_client {
292 int idx; /**< Which client desired? */
293 int auth; /**< Is client authenticated? */
294 unsigned long pid; /**< Process ID */
295 unsigned long uid; /**< User ID */
296 unsigned long magic; /**< Magic */
297 unsigned long iocs; /**< Ioctl count */
307 _DRM_STAT_VALUE, /**< Generic value */
308 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
309 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
311 _DRM_STAT_IRQ, /**< IRQ */
312 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
313 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
314 _DRM_STAT_DMA, /**< DMA */
315 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
316 _DRM_STAT_MISSED /**< Missed DMA opportunity */
317 /* Add to the *END* of the list */
321 * DRM_IOCTL_GET_STATS ioctl argument type.
323 typedef struct drm_stats {
327 drm_stat_type_t type;
332 * Hardware locking flags.
334 typedef enum drm_lock_flags {
335 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
336 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
337 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
338 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
339 /* These *HALT* flags aren't supported yet
340 -- they will be used to support the
341 full-screen DGA-like mode. */
342 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
343 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
347 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
349 * \sa drmGetLock() and drmUnlock().
351 typedef struct drm_lock {
353 drm_lock_flags_t flags;
360 * These values \e must match xf86drm.h.
364 typedef enum drm_dma_flags {
365 /* Flags for DMA buffer dispatch */
366 _DRM_DMA_BLOCK = 0x01, /**<
367 * Block until buffer dispatched.
369 * \note The buffer may not yet have
370 * been processed by the hardware --
371 * getting a hardware lock with the
372 * hardware quiescent will ensure
373 * that the buffer has been
376 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
377 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
379 /* Flags for DMA buffer request */
380 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
381 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
382 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
386 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
390 typedef struct drm_buf_desc {
391 int count; /**< Number of buffers of this size */
392 int size; /**< Size in bytes */
393 int low_mark; /**< Low water mark */
394 int high_mark; /**< High water mark */
396 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
397 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
398 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
399 _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */
401 unsigned long agp_start; /**<
402 * Start address of where the AGP buffers are
403 * in the AGP aperture
408 * DRM_IOCTL_INFO_BUFS ioctl argument type.
410 typedef struct drm_buf_info {
411 int count; /**< Number of buffers described in list */
412 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
416 * DRM_IOCTL_FREE_BUFS ioctl argument type.
418 typedef struct drm_buf_free {
428 typedef struct drm_buf_pub {
429 int idx; /**< Index into the master buffer list */
430 int total; /**< Buffer size */
431 int used; /**< Amount of buffer in use (for DMA) */
432 void __user *address; /**< Address of buffer */
436 * DRM_IOCTL_MAP_BUFS ioctl argument type.
438 typedef struct drm_buf_map {
439 int count; /**< Length of the buffer list */
440 void __user *virtual; /**< Mmap'd area in user-virtual */
441 drm_buf_pub_t __user *list; /**< Buffer information */
445 * DRM_IOCTL_DMA ioctl argument type.
447 * Indices here refer to the offset into the buffer list in drm_buf_get.
451 typedef struct drm_dma {
452 int context; /**< Context handle */
453 int send_count; /**< Number of buffers to send */
454 int __user *send_indices; /**< List of handles to buffers */
455 int __user *send_sizes; /**< Lengths of data to send */
456 drm_dma_flags_t flags; /**< Flags */
457 int request_count; /**< Number of buffers requested */
458 int request_size; /**< Desired size for buffers */
459 int __user *request_indices; /**< Buffer information */
460 int __user *request_sizes;
461 int granted_count; /**< Number of buffers granted */
465 _DRM_CONTEXT_PRESERVED = 0x01,
466 _DRM_CONTEXT_2DONLY = 0x02
470 * DRM_IOCTL_ADD_CTX ioctl argument type.
472 * \sa drmCreateContext() and drmDestroyContext().
474 typedef struct drm_ctx {
475 drm_context_t handle;
476 drm_ctx_flags_t flags;
480 * DRM_IOCTL_RES_CTX ioctl argument type.
482 typedef struct drm_ctx_res {
484 drm_ctx_t __user *contexts;
488 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
490 typedef struct drm_draw {
491 drm_drawable_t handle;
495 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
497 typedef struct drm_auth {
502 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
504 * \sa drmGetInterruptFromBusID().
506 typedef struct drm_irq_busid {
507 int irq; /**< IRQ number */
508 int busnum; /**< bus number */
509 int devnum; /**< device number */
510 int funcnum; /**< function number */
514 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
515 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
516 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
517 } drm_vblank_seq_type_t;
519 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
521 struct drm_wait_vblank_request {
522 drm_vblank_seq_type_t type;
523 unsigned int sequence;
524 unsigned long signal;
527 struct drm_wait_vblank_reply {
528 drm_vblank_seq_type_t type;
529 unsigned int sequence;
535 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
537 * \sa drmWaitVBlank().
539 typedef union drm_wait_vblank {
540 struct drm_wait_vblank_request request;
541 struct drm_wait_vblank_reply reply;
545 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
547 * \sa drmAgpEnable().
549 typedef struct drm_agp_mode {
550 unsigned long mode; /**< AGP mode */
554 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
556 * \sa drmAgpAlloc() and drmAgpFree().
558 typedef struct drm_agp_buffer {
559 unsigned long size; /**< In bytes -- will round to page boundary */
560 unsigned long handle; /**< Used for binding / unbinding */
561 unsigned long type; /**< Type of memory to allocate */
562 unsigned long physical; /**< Physical used by i810 */
566 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
568 * \sa drmAgpBind() and drmAgpUnbind().
570 typedef struct drm_agp_binding {
571 unsigned long handle; /**< From drm_agp_buffer */
572 unsigned long offset; /**< In bytes -- will round to page boundary */
576 * DRM_IOCTL_AGP_INFO ioctl argument type.
578 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
579 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
580 * drmAgpVendorId() and drmAgpDeviceId().
582 typedef struct drm_agp_info {
583 int agp_version_major;
584 int agp_version_minor;
586 unsigned long aperture_base; /**< physical address */
587 unsigned long aperture_size; /**< bytes */
588 unsigned long memory_allowed; /**< bytes */
589 unsigned long memory_used;
591 /** \name PCI information */
593 unsigned short id_vendor;
594 unsigned short id_device;
599 * DRM_IOCTL_SG_ALLOC ioctl argument type.
601 typedef struct drm_scatter_gather {
602 unsigned long size; /**< In bytes -- will round to page boundary */
603 unsigned long handle; /**< Used for mapping / unmapping */
604 } drm_scatter_gather_t;
607 * DRM_IOCTL_SET_VERSION ioctl argument type.
609 typedef struct drm_set_version {
617 * \name Ioctls Definitions
621 #define DRM_IOCTL_BASE 'd'
622 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
623 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
624 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
625 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
627 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
628 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
629 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
630 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
631 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
632 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
633 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
634 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
636 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
637 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
638 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
639 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
640 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
641 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
642 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
643 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
644 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
645 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
646 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
648 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
650 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
651 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
653 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
654 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
655 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
656 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
657 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
658 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
659 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
660 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
661 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
662 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
663 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
664 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
665 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
667 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
668 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
669 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
670 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
671 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
672 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
673 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
674 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
676 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
677 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
679 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
684 * Device specific ioctls should only be in their respective headers
685 * The device specific ioctl range is from 0x40 to 0x79.
687 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
688 * drmCommandReadWrite().
690 #define DRM_COMMAND_BASE 0x40