3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
66 # define DEPRECATED __attribute__ ((deprecated))
71 #if defined(__linux__)
72 #include <asm/ioctl.h> /* For _IO* macros */
73 #define DRM_IOCTL_NR(n) _IOC_NR(n)
74 #define DRM_IOC_VOID _IOC_NONE
75 #define DRM_IOC_READ _IOC_READ
76 #define DRM_IOC_WRITE _IOC_WRITE
77 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
78 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
79 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
80 #if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
81 /* Prevent name collision when including sys/ioccom.h */
83 #include <sys/ioccom.h>
84 #define ioctl(a,b,c) xf86ioctl(a,b,c)
86 #include <sys/ioccom.h>
87 #endif /* __FreeBSD__ && xf86ioctl */
88 #define DRM_IOCTL_NR(n) ((n) & 0xff)
89 #define DRM_IOC_VOID IOC_VOID
90 #define DRM_IOC_READ IOC_OUT
91 #define DRM_IOC_WRITE IOC_IN
92 #define DRM_IOC_READWRITE IOC_INOUT
93 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
96 #define XFREE86_VERSION(major,minor,patch,snap) \
97 ((major << 16) | (minor << 8) | patch)
99 #ifndef CONFIG_XFREE86_VERSION
100 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
103 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
104 #define DRM_PROC_DEVICES "/proc/devices"
105 #define DRM_PROC_MISC "/proc/misc"
106 #define DRM_PROC_DRM "/proc/drm"
107 #define DRM_DEV_DRM "/dev/drm"
108 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
109 #define DRM_DEV_UID 0
110 #define DRM_DEV_GID 0
113 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
117 #if defined(__linux__) || defined(__NetBSD__)
118 #define DRM_MAJOR 226
120 #define DRM_MAX_MINOR 15
122 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
123 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
124 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
125 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
127 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
128 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
129 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
130 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
131 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
133 #if defined(__linux__)
134 #if defined(__KERNEL__)
135 typedef __u64 drm_u64_t;
137 typedef unsigned long long drm_u64_t;
140 typedef unsigned int drm_handle_t;
142 #include <sys/types.h>
143 typedef u_int64_t drm_u64_t;
144 typedef unsigned long drm_handle_t; /**< To mapped regions */
146 typedef unsigned int drm_context_t; /**< GLXContext handle */
147 typedef unsigned int drm_drawable_t;
148 typedef unsigned int drm_magic_t; /**< Magic for authentication */
153 * \warning If you change this structure, make sure you change
154 * XF86DRIClipRectRec in the server as well
156 * \note KW: Actually it's illegal to change either for
157 * backwards-compatibility reasons.
159 typedef struct drm_clip_rect {
167 * Drawable information.
169 typedef struct drm_drawable_info {
170 unsigned int num_rects;
171 drm_clip_rect_t *rects;
172 } drm_drawable_info_t;
177 typedef struct drm_tex_region {
180 unsigned char in_use;
181 unsigned char padding;
188 * The lock structure is a simple cache-line aligned integer. To avoid
189 * processor bus contention on a multiprocessor system, there should not be any
190 * other data stored in the same cache line.
192 typedef struct drm_hw_lock {
193 __volatile__ unsigned int lock; /**< lock variable */
194 char padding[60]; /**< Pad to cache line */
197 /* This is beyond ugly, and only works on GCC. However, it allows me to use
198 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
199 * fix is to use uint32_t instead of size_t, but that fix will break existing
200 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
201 * eventually happen, though. I chose 'unsigned long' to be the fallback type
202 * because that works on all the platforms I know about. Hopefully, the
203 * real fix will happen before that bites us.
207 # define DRM_SIZE_T __SIZE_TYPE__
209 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
210 # define DRM_SIZE_T unsigned long
214 * DRM_IOCTL_VERSION ioctl argument type.
216 * \sa drmGetVersion().
218 typedef struct drm_version {
219 int version_major; /**< Major version */
220 int version_minor; /**< Minor version */
221 int version_patchlevel; /**< Patch level */
222 DRM_SIZE_T name_len; /**< Length of name buffer */
223 char __user *name; /**< Name of driver */
224 DRM_SIZE_T date_len; /**< Length of date buffer */
225 char __user *date; /**< User-space buffer to hold date */
226 DRM_SIZE_T desc_len; /**< Length of desc buffer */
227 char __user *desc; /**< User-space buffer to hold desc */
231 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
233 * \sa drmGetBusid() and drmSetBusId().
235 typedef struct drm_unique {
236 DRM_SIZE_T unique_len; /**< Length of unique */
237 char __user *unique; /**< Unique name for driver instantiation */
242 typedef struct drm_list {
243 int count; /**< Length of user-space structures */
244 drm_version_t __user *version;
247 typedef struct drm_block {
252 * DRM_IOCTL_CONTROL ioctl argument type.
254 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
256 typedef struct drm_control {
267 * Type of memory to map.
269 typedef enum drm_map_type {
270 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
271 _DRM_REGISTERS = 1, /**< no caching, no core dump */
272 _DRM_SHM = 2, /**< shared, cached */
273 _DRM_AGP = 3, /**< AGP/GART */
274 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
275 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
280 * Memory mapping flags.
282 typedef enum drm_map_flags {
283 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
284 _DRM_READ_ONLY = 0x02,
285 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
286 _DRM_KERNEL = 0x08, /**< kernel requires access */
287 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
288 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
289 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
292 typedef struct drm_ctx_priv_map {
293 unsigned int ctx_id; /**< Context requesting private mapping */
294 void *handle; /**< Handle of map */
295 } drm_ctx_priv_map_t;
298 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
303 typedef struct drm_map {
304 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
305 unsigned long size; /**< Requested physical size (bytes) */
306 drm_map_type_t type; /**< Type of memory to map */
307 drm_map_flags_t flags; /**< Flags */
308 void *handle; /**< User-space: "Handle" to pass to mmap() */
309 /**< Kernel-space: kernel-virtual address */
310 int mtrr; /**< MTRR slot used */
315 * DRM_IOCTL_GET_CLIENT ioctl argument type.
317 typedef struct drm_client {
318 int idx; /**< Which client desired? */
319 int auth; /**< Is client authenticated? */
320 unsigned long pid; /**< Process ID */
321 unsigned long uid; /**< User ID */
322 unsigned long magic; /**< Magic */
323 unsigned long iocs; /**< Ioctl count */
333 _DRM_STAT_VALUE, /**< Generic value */
334 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
335 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
337 _DRM_STAT_IRQ, /**< IRQ */
338 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
339 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
340 _DRM_STAT_DMA, /**< DMA */
341 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
342 _DRM_STAT_MISSED /**< Missed DMA opportunity */
343 /* Add to the *END* of the list */
347 * DRM_IOCTL_GET_STATS ioctl argument type.
349 typedef struct drm_stats {
353 drm_stat_type_t type;
358 * Hardware locking flags.
360 typedef enum drm_lock_flags {
361 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
362 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
363 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
364 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
365 /* These *HALT* flags aren't supported yet
366 -- they will be used to support the
367 full-screen DGA-like mode. */
368 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
369 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
373 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
375 * \sa drmGetLock() and drmUnlock().
377 typedef struct drm_lock {
379 drm_lock_flags_t flags;
386 * These values \e must match xf86drm.h.
390 typedef enum drm_dma_flags {
391 /* Flags for DMA buffer dispatch */
392 _DRM_DMA_BLOCK = 0x01, /**<
393 * Block until buffer dispatched.
395 * \note The buffer may not yet have
396 * been processed by the hardware --
397 * getting a hardware lock with the
398 * hardware quiescent will ensure
399 * that the buffer has been
402 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
403 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
405 /* Flags for DMA buffer request */
406 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
407 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
408 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
412 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
416 typedef struct drm_buf_desc {
417 int count; /**< Number of buffers of this size */
418 int size; /**< Size in bytes */
419 int low_mark; /**< Low water mark */
420 int high_mark; /**< High water mark */
422 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
423 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
424 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
425 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
426 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
428 unsigned long agp_start; /**<
429 * Start address of where the AGP buffers are
430 * in the AGP aperture
435 * DRM_IOCTL_INFO_BUFS ioctl argument type.
437 typedef struct drm_buf_info {
438 int count; /**< Number of buffers described in list */
439 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
443 * DRM_IOCTL_FREE_BUFS ioctl argument type.
445 typedef struct drm_buf_free {
455 typedef struct drm_buf_pub {
456 int idx; /**< Index into the master buffer list */
457 int total; /**< Buffer size */
458 int used; /**< Amount of buffer in use (for DMA) */
459 void __user *address; /**< Address of buffer */
463 * DRM_IOCTL_MAP_BUFS ioctl argument type.
465 typedef struct drm_buf_map {
466 int count; /**< Length of the buffer list */
467 #if defined(__cplusplus)
468 void __user *c_virtual;
470 void __user *virtual; /**< Mmap'd area in user-virtual */
472 drm_buf_pub_t __user *list; /**< Buffer information */
476 * DRM_IOCTL_DMA ioctl argument type.
478 * Indices here refer to the offset into the buffer list in drm_buf_get.
482 typedef struct drm_dma {
483 int context; /**< Context handle */
484 int send_count; /**< Number of buffers to send */
485 int __user *send_indices; /**< List of handles to buffers */
486 int __user *send_sizes; /**< Lengths of data to send */
487 drm_dma_flags_t flags; /**< Flags */
488 int request_count; /**< Number of buffers requested */
489 int request_size; /**< Desired size for buffers */
490 int __user *request_indices; /**< Buffer information */
491 int __user *request_sizes;
492 int granted_count; /**< Number of buffers granted */
496 _DRM_CONTEXT_PRESERVED = 0x01,
497 _DRM_CONTEXT_2DONLY = 0x02
501 * DRM_IOCTL_ADD_CTX ioctl argument type.
503 * \sa drmCreateContext() and drmDestroyContext().
505 typedef struct drm_ctx {
506 drm_context_t handle;
507 drm_ctx_flags_t flags;
511 * DRM_IOCTL_RES_CTX ioctl argument type.
513 typedef struct drm_ctx_res {
515 drm_ctx_t __user *contexts;
519 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
521 typedef struct drm_draw {
522 drm_drawable_t handle;
526 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
529 DRM_DRAWABLE_CLIPRECTS,
530 } drm_drawable_info_type_t;
532 typedef struct drm_update_draw {
533 drm_drawable_t handle;
536 unsigned long long data;
540 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
542 typedef struct drm_auth {
547 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
549 * \sa drmGetInterruptFromBusID().
551 typedef struct drm_irq_busid {
552 int irq; /**< IRQ number */
553 int busnum; /**< bus number */
554 int devnum; /**< device number */
555 int funcnum; /**< function number */
559 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
560 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
561 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
562 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
563 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
564 } drm_vblank_seq_type_t;
566 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
567 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
568 _DRM_VBLANK_NEXTONMISS)
570 struct drm_wait_vblank_request {
571 drm_vblank_seq_type_t type;
572 unsigned int sequence;
573 unsigned long signal;
576 struct drm_wait_vblank_reply {
577 drm_vblank_seq_type_t type;
578 unsigned int sequence;
584 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
586 * \sa drmWaitVBlank().
588 typedef union drm_wait_vblank {
589 struct drm_wait_vblank_request request;
590 struct drm_wait_vblank_reply reply;
594 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
596 * \sa drmAgpEnable().
598 typedef struct drm_agp_mode {
599 unsigned long mode; /**< AGP mode */
603 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
605 * \sa drmAgpAlloc() and drmAgpFree().
607 typedef struct drm_agp_buffer {
608 unsigned long size; /**< In bytes -- will round to page boundary */
609 unsigned long handle; /**< Used for binding / unbinding */
610 unsigned long type; /**< Type of memory to allocate */
611 unsigned long physical; /**< Physical used by i810 */
615 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
617 * \sa drmAgpBind() and drmAgpUnbind().
619 typedef struct drm_agp_binding {
620 unsigned long handle; /**< From drm_agp_buffer */
621 unsigned long offset; /**< In bytes -- will round to page boundary */
625 * DRM_IOCTL_AGP_INFO ioctl argument type.
627 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
628 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
629 * drmAgpVendorId() and drmAgpDeviceId().
631 typedef struct drm_agp_info {
632 int agp_version_major;
633 int agp_version_minor;
635 unsigned long aperture_base; /**< physical address */
636 unsigned long aperture_size; /**< bytes */
637 unsigned long memory_allowed; /**< bytes */
638 unsigned long memory_used;
640 /** \name PCI information */
642 unsigned short id_vendor;
643 unsigned short id_device;
648 * DRM_IOCTL_SG_ALLOC ioctl argument type.
650 typedef struct drm_scatter_gather {
651 unsigned long size; /**< In bytes -- will round to page boundary */
652 unsigned long handle; /**< Used for mapping / unmapping */
653 } drm_scatter_gather_t;
656 * DRM_IOCTL_SET_VERSION ioctl argument type.
658 typedef struct drm_set_version {
666 #define DRM_FENCE_FLAG_EMIT 0x00000001
667 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
668 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
669 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
671 /* Reserved for driver use */
672 #define DRM_FENCE_MASK_DRIVER 0xFF000000
674 #define DRM_FENCE_TYPE_EXE 0x00000001
676 typedef struct drm_fence_arg {
682 unsigned expand_pad[4]; /*Future expansion */
687 drm_fence_unreference,
696 /* Buffer permissions, referring to how the GPU uses the buffers.
697 these translate to fence types used for the buffers.
698 Typically a texture buffer is read, A destination buffer is write and
699 a command (batch-) buffer is exe. Can be or-ed together. */
701 #define DRM_BO_FLAG_READ 0x00000001
702 #define DRM_BO_FLAG_WRITE 0x00000002
703 #define DRM_BO_FLAG_EXE 0x00000004
706 * Status flags. Can be read to determine the actual state of a buffer.
710 * Cannot evict this buffer. Not even with force. This type of buffer should
711 * only be available for root, and must be manually removed before buffer
712 * manager shutdown or swapout.
714 #define DRM_BO_FLAG_NO_EVICT 0x00000010
715 /* Always keep a system memory shadow to a vram buffer */
716 #define DRM_BO_FLAG_SHADOW_VRAM 0x00000020
717 /* The buffer is shareable with other processes */
718 #define DRM_BO_FLAG_SHAREABLE 0x00000040
719 /* The buffer is currently cached */
720 #define DRM_BO_FLAG_CACHED 0x00000080
721 /* Make sure that every time this buffer is validated, it ends up on the same
722 * location. The buffer will also not be evicted when claiming space for
723 * other buffers. Basically a pinned buffer but it may be thrown out as
724 * part of buffer manager shutdown or swapout. Not supported yet.*/
725 #define DRM_BO_FLAG_NO_MOVE 0x00000100
727 /* Make sure the buffer is in cached memory when mapped for reading */
728 #define DRM_BO_FLAG_READ_CACHED 0x00080000
729 /* When there is a choice between VRAM and TT, prefer VRAM.
730 The default behaviour is to prefer TT. */
731 #define DRM_BO_FLAG_PREFER_VRAM 0x00040000
732 /* Bind this buffer cached if the hardware supports it. */
733 #define DRM_BO_FLAG_BIND_CACHED 0x0002000
736 #define DRM_BO_FLAG_MEM_LOCAL 0x01000000
737 /* Translation table memory */
738 #define DRM_BO_FLAG_MEM_TT 0x02000000
740 #define DRM_BO_FLAG_MEM_VRAM 0x04000000
741 /* Unmappable Vram memory */
742 #define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000
743 /* Memory flag mask */
744 #define DRM_BO_MASK_MEM 0xFF000000
746 /* When creating a buffer, Avoid system storage even if allowed */
747 #define DRM_BO_HINT_AVOID_LOCAL 0x00000001
748 /* Don't block on validate and map */
749 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
750 /* Don't place this buffer on the unfenced list.*/
751 #define DRM_BO_HINT_DONT_FENCE 0x00000004
752 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
753 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
756 /* Driver specific flags. Could be for example rendering engine */
757 #define DRM_BO_MASK_DRIVER 0x00F00000
766 typedef struct drm_bo_arg_request {
767 unsigned handle; /* User space handle */
773 drm_u64_t buffer_start;
774 unsigned page_alignment;
775 unsigned expand_pad[4]; /*Future expansion */
789 } drm_bo_arg_request_t;
796 #define DRM_BO_REP_BUSY 0x00000001
798 typedef struct drm_bo_arg_reply {
804 drm_u64_t arg_handle;
806 drm_u64_t buffer_start;
807 unsigned fence_flags;
809 unsigned page_alignment;
810 unsigned expand_pad[4]; /*Future expansion */
814 typedef struct drm_bo_arg{
818 drm_bo_arg_request_t req;
819 drm_bo_arg_reply_t rep;
823 #define DRM_BO_MEM_LOCAL 0
824 #define DRM_BO_MEM_TT 1
825 #define DRM_BO_MEM_VRAM 2
826 #define DRM_BO_MEM_VRAM_NM 3
827 #define DRM_BO_MEM_TYPES 2 /* For now. */
829 typedef union drm_mm_init_arg{
841 unsigned expand_pad[8]; /*Future expansion */
844 drm_handle_t mm_sarea;
845 unsigned expand_pad[8]; /*Future expansion */
850 * \name Ioctls Definitions
854 #define DRM_IOCTL_BASE 'd'
855 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
856 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
857 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
858 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
860 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
861 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
862 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
863 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
864 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
865 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
866 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
867 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
869 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
870 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
871 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
872 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
873 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
874 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
875 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
876 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
877 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
878 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
879 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
881 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
883 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
884 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
886 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
887 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
888 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
889 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
890 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
891 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
892 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
893 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
894 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
895 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
896 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
897 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
898 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
900 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
901 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
902 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
903 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
904 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
905 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
906 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
907 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
909 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
910 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
912 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
914 #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
915 #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
916 #define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
918 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
923 * Device specific ioctls should only be in their respective headers
924 * The device specific ioctl range is from 0x40 to 0x99.
925 * Generic IOCTLS restart at 0xA0.
927 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
928 * drmCommandReadWrite().
930 #define DRM_COMMAND_BASE 0x40
931 #define DRM_COMMAND_END 0xA0