3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
95 #if defined(__linux__) || defined(__NetBSD__)
98 #define DRM_MAX_MINOR 15
100 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
101 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
102 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
103 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
105 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
106 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
107 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
108 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
109 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
111 #if defined(__linux__)
112 typedef unsigned int drm_handle_t;
114 #include <sys/types.h>
115 typedef unsigned long drm_handle_t; /**< To mapped regions */
117 typedef unsigned int drm_context_t; /**< GLXContext handle */
118 typedef unsigned int drm_drawable_t;
119 typedef unsigned int drm_magic_t; /**< Magic for authentication */
124 * \warning If you change this structure, make sure you change
125 * XF86DRIClipRectRec in the server as well
127 * \note KW: Actually it's illegal to change either for
128 * backwards-compatibility reasons.
130 struct drm_clip_rect {
138 * Drawable information.
140 struct drm_drawable_info {
141 unsigned int num_rects;
142 struct drm_clip_rect *rects;
148 struct drm_tex_region {
151 unsigned char in_use;
152 unsigned char padding;
159 * The lock structure is a simple cache-line aligned integer. To avoid
160 * processor bus contention on a multiprocessor system, there should not be any
161 * other data stored in the same cache line.
164 __volatile__ unsigned int lock; /**< lock variable */
165 char padding[60]; /**< Pad to cache line */
168 /* This is beyond ugly, and only works on GCC. However, it allows me to use
169 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
170 * fix is to use uint32_t instead of size_t, but that fix will break existing
171 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
172 * eventually happen, though. I chose 'unsigned long' to be the fallback type
173 * because that works on all the platforms I know about. Hopefully, the
174 * real fix will happen before that bites us.
178 # define DRM_SIZE_T __SIZE_TYPE__
180 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
181 # define DRM_SIZE_T unsigned long
185 * DRM_IOCTL_VERSION ioctl argument type.
187 * \sa drmGetVersion().
190 int version_major; /**< Major version */
191 int version_minor; /**< Minor version */
192 int version_patchlevel; /**< Patch level */
193 DRM_SIZE_T name_len; /**< Length of name buffer */
194 char __user *name; /**< Name of driver */
195 DRM_SIZE_T date_len; /**< Length of date buffer */
196 char __user *date; /**< User-space buffer to hold date */
197 DRM_SIZE_T desc_len; /**< Length of desc buffer */
198 char __user *desc; /**< User-space buffer to hold desc */
202 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
204 * \sa drmGetBusid() and drmSetBusId().
207 DRM_SIZE_T unique_len; /**< Length of unique */
208 char __user *unique; /**< Unique name for driver instantiation */
214 int count; /**< Length of user-space structures */
215 struct drm_version __user *version;
223 * DRM_IOCTL_CONTROL ioctl argument type.
225 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
238 * Type of memory to map.
241 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
242 _DRM_REGISTERS = 1, /**< no caching, no core dump */
243 _DRM_SHM = 2, /**< shared, cached */
244 _DRM_AGP = 3, /**< AGP/GART */
245 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
246 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
251 * Memory mapping flags.
254 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
255 _DRM_READ_ONLY = 0x02,
256 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
257 _DRM_KERNEL = 0x08, /**< kernel requires access */
258 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
259 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
260 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
261 _DRM_DRIVER = 0x80 /**< Driver will take care of it */
264 struct drm_ctx_priv_map {
265 unsigned int ctx_id; /**< Context requesting private mapping */
266 void *handle; /**< Handle of map */
270 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
276 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
277 unsigned long size; /**< Requested physical size (bytes) */
278 enum drm_map_type type; /**< Type of memory to map */
279 enum drm_map_flags flags; /**< Flags */
280 void *handle; /**< User-space: "Handle" to pass to mmap() */
281 /**< Kernel-space: kernel-virtual address */
282 int mtrr; /**< MTRR slot used */
287 * DRM_IOCTL_GET_CLIENT ioctl argument type.
290 int idx; /**< Which client desired? */
291 int auth; /**< Is client authenticated? */
292 unsigned long pid; /**< Process ID */
293 unsigned long uid; /**< User ID */
294 unsigned long magic; /**< Magic */
295 unsigned long iocs; /**< Ioctl count */
305 _DRM_STAT_VALUE, /**< Generic value */
306 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
307 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
309 _DRM_STAT_IRQ, /**< IRQ */
310 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
311 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
312 _DRM_STAT_DMA, /**< DMA */
313 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
314 _DRM_STAT_MISSED /**< Missed DMA opportunity */
315 /* Add to the *END* of the list */
319 * DRM_IOCTL_GET_STATS ioctl argument type.
325 enum drm_stat_type type;
330 * Hardware locking flags.
332 enum drm_lock_flags {
333 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
334 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
335 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
336 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
337 /* These *HALT* flags aren't supported yet
338 -- they will be used to support the
339 full-screen DGA-like mode. */
340 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
341 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
345 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
347 * \sa drmGetLock() and drmUnlock().
351 enum drm_lock_flags flags;
358 * These values \e must match xf86drm.h.
363 /* Flags for DMA buffer dispatch */
364 _DRM_DMA_BLOCK = 0x01, /**<
365 * Block until buffer dispatched.
367 * \note The buffer may not yet have
368 * been processed by the hardware --
369 * getting a hardware lock with the
370 * hardware quiescent will ensure
371 * that the buffer has been
374 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
375 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
377 /* Flags for DMA buffer request */
378 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
379 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
380 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
384 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
388 struct drm_buf_desc {
389 int count; /**< Number of buffers of this size */
390 int size; /**< Size in bytes */
391 int low_mark; /**< Low water mark */
392 int high_mark; /**< High water mark */
394 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
395 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
396 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
397 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
398 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
400 unsigned long agp_start; /**<
401 * Start address of where the AGP buffers are
402 * in the AGP aperture
407 * DRM_IOCTL_INFO_BUFS ioctl argument type.
409 struct drm_buf_info {
410 int count; /**< Number of buffers described in list */
411 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
415 * DRM_IOCTL_FREE_BUFS ioctl argument type.
417 struct drm_buf_free {
428 int idx; /**< Index into the master buffer list */
429 int total; /**< Buffer size */
430 int used; /**< Amount of buffer in use (for DMA) */
431 void __user *address; /**< Address of buffer */
435 * DRM_IOCTL_MAP_BUFS ioctl argument type.
438 int count; /**< Length of the buffer list */
439 #if defined(__cplusplus)
440 void __user *c_virtual;
442 void __user *virtual; /**< Mmap'd area in user-virtual */
444 struct drm_buf_pub __user *list; /**< Buffer information */
448 * DRM_IOCTL_DMA ioctl argument type.
450 * Indices here refer to the offset into the buffer list in drm_buf_get.
455 int context; /**< Context handle */
456 int send_count; /**< Number of buffers to send */
457 int __user *send_indices; /**< List of handles to buffers */
458 int __user *send_sizes; /**< Lengths of data to send */
459 enum drm_dma_flags flags; /**< Flags */
460 int request_count; /**< Number of buffers requested */
461 int request_size; /**< Desired size for buffers */
462 int __user *request_indices; /**< Buffer information */
463 int __user *request_sizes;
464 int granted_count; /**< Number of buffers granted */
468 _DRM_CONTEXT_PRESERVED = 0x01,
469 _DRM_CONTEXT_2DONLY = 0x02
473 * DRM_IOCTL_ADD_CTX ioctl argument type.
475 * \sa drmCreateContext() and drmDestroyContext().
478 drm_context_t handle;
479 enum drm_ctx_flags flags;
483 * DRM_IOCTL_RES_CTX ioctl argument type.
487 struct drm_ctx __user *contexts;
491 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
494 drm_drawable_t handle;
498 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
501 DRM_DRAWABLE_CLIPRECTS,
502 } drm_drawable_info_type_t;
504 struct drm_update_draw {
505 drm_drawable_t handle;
508 unsigned long long data;
512 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
519 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
521 * \sa drmGetInterruptFromBusID().
523 struct drm_irq_busid {
524 int irq; /**< IRQ number */
525 int busnum; /**< bus number */
526 int devnum; /**< device number */
527 int funcnum; /**< function number */
530 enum drm_vblank_seq_type {
531 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
532 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
533 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
534 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
535 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
536 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
539 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
540 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
541 _DRM_VBLANK_NEXTONMISS)
543 struct drm_wait_vblank_request {
544 enum drm_vblank_seq_type type;
545 unsigned int sequence;
546 unsigned long signal;
549 struct drm_wait_vblank_reply {
550 enum drm_vblank_seq_type type;
551 unsigned int sequence;
557 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
559 * \sa drmWaitVBlank().
561 union drm_wait_vblank {
562 struct drm_wait_vblank_request request;
563 struct drm_wait_vblank_reply reply;
567 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
569 * \sa drmAgpEnable().
571 struct drm_agp_mode {
572 unsigned long mode; /**< AGP mode */
576 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
578 * \sa drmAgpAlloc() and drmAgpFree().
580 struct drm_agp_buffer {
581 unsigned long size; /**< In bytes -- will round to page boundary */
582 unsigned long handle; /**< Used for binding / unbinding */
583 unsigned long type; /**< Type of memory to allocate */
584 unsigned long physical; /**< Physical used by i810 */
588 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
590 * \sa drmAgpBind() and drmAgpUnbind().
592 struct drm_agp_binding {
593 unsigned long handle; /**< From drm_agp_buffer */
594 unsigned long offset; /**< In bytes -- will round to page boundary */
598 * DRM_IOCTL_AGP_INFO ioctl argument type.
600 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
601 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
602 * drmAgpVendorId() and drmAgpDeviceId().
604 struct drm_agp_info {
605 int agp_version_major;
606 int agp_version_minor;
608 unsigned long aperture_base; /**< physical address */
609 unsigned long aperture_size; /**< bytes */
610 unsigned long memory_allowed; /**< bytes */
611 unsigned long memory_used;
613 /** \name PCI information */
615 unsigned short id_vendor;
616 unsigned short id_device;
621 * DRM_IOCTL_SG_ALLOC ioctl argument type.
623 struct drm_scatter_gather {
624 unsigned long size; /**< In bytes -- will round to page boundary */
625 unsigned long handle; /**< Used for mapping / unmapping */
629 * DRM_IOCTL_SET_VERSION ioctl argument type.
631 struct drm_set_version {
639 #define DRM_FENCE_FLAG_EMIT 0x00000001
640 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
641 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
642 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
643 #define DRM_FENCE_FLAG_NO_USER 0x00000010
645 /* Reserved for driver use */
646 #define DRM_FENCE_MASK_DRIVER 0xFF000000
648 #define DRM_FENCE_TYPE_EXE 0x00000001
650 struct drm_fence_arg {
652 unsigned int fence_class;
655 unsigned int signaled;
657 unsigned int sequence;
659 uint64_t expand_pad[2]; /*Future expansion */
662 /* Buffer permissions, referring to how the GPU uses the buffers.
663 * these translate to fence types used for the buffers.
664 * Typically a texture buffer is read, A destination buffer is write and
665 * a command (batch-) buffer is exe. Can be or-ed together.
668 #define DRM_BO_FLAG_READ (1ULL << 0)
669 #define DRM_BO_FLAG_WRITE (1ULL << 1)
670 #define DRM_BO_FLAG_EXE (1ULL << 2)
673 * Status flags. Can be read to determine the actual state of a buffer.
674 * Can also be set in the buffer mask before validation.
678 * Mask: Require that the buffer is placed in mappable memory when validated.
679 * If not set the buffer may or may not be in mappable memory when validated.
680 * Flags: If set, the buffer is in mappable memory.
682 #define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
684 /* Mask: The buffer should be shareable with other processes.
685 * Flags: The buffer is shareable with other processes.
687 #define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
689 /* Mask: If set, place the buffer in cache-coherent memory if available.
690 * If clear, never place the buffer in cache coherent memory if validated.
691 * Flags: The buffer is currently in cache-coherent memory.
693 #define DRM_BO_FLAG_CACHED (1ULL << 7)
695 /* Mask: Make sure that every time this buffer is validated,
696 * it ends up on the same location provided that the memory mask is the same.
697 * The buffer will also not be evicted when claiming space for
698 * other buffers. Basically a pinned buffer but it may be thrown out as
699 * part of buffer manager shutdown or locking.
700 * Flags: Acknowledge.
702 #define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
704 /* Mask: Make sure the buffer is in cached memory when mapped for reading.
705 * Flags: Acknowledge.
707 #define DRM_BO_FLAG_READ_CACHED (1ULL << 19)
709 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
710 * Flags: Acknowledge.
712 #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
715 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
716 * Flags: Acknowledge.
718 #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
721 * Memory type flags that can be or'ed together in the mask, but only
722 * one appears in flags.
726 #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
727 /* Translation table memory */
728 #define DRM_BO_FLAG_MEM_TT (1ULL << 25)
730 #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
731 /* Up to the driver to define. */
732 #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
733 #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
734 #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
735 #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
736 #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
737 /* We can add more of these now with a 64-bit flag type */
739 /* Memory flag mask */
740 #define DRM_BO_MASK_MEM 0x00000000FF000000ULL
741 #define DRM_BO_MASK_MEMTYPE 0x00000000FF0000A0ULL
743 /* Driver-private flags */
744 #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
746 /* Don't block on validate and map */
747 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
748 /* Don't place this buffer on the unfenced list.*/
749 #define DRM_BO_HINT_DONT_FENCE 0x00000004
750 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
751 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
753 #define DRM_BO_INIT_MAGIC 0xfe769812
754 #define DRM_BO_INIT_MAJOR 0
755 #define DRM_BO_INIT_MINOR 1
758 struct drm_bo_info_req {
763 unsigned int fence_class;
767 struct drm_bo_create_req {
770 uint64_t buffer_start;
772 unsigned int page_alignment;
775 struct drm_bo_op_req {
781 unsigned int arg_handle;
782 struct drm_bo_info_req bo_req;
785 struct drm_bo_set_pin_req {
786 /** Buffer object ID */
789 * - 0: Unpin the given buffer object.
790 * - 1: Pin the given buffer object, requiring that its offset and
791 * memory area stay constant until unpin. The intended use is for
801 #define DRM_BO_REP_BUSY 0x00000001
803 struct drm_bo_info_rep {
809 uint64_t buffer_start;
811 unsigned int fence_flags;
812 unsigned int rep_flags;
813 unsigned int page_alignment;
814 unsigned int desired_tile_stride;
815 unsigned int hw_tile_stride;
816 unsigned int tile_info;
818 uint64_t expand_pad[4]; /*Future expansion */
821 struct drm_bo_arg_rep {
822 struct drm_bo_info_rep bo_info;
827 struct drm_bo_create_arg {
829 struct drm_bo_create_req req;
830 struct drm_bo_info_rep rep;
834 struct drm_bo_handle_arg {
838 struct drm_bo_reference_info_arg {
840 struct drm_bo_handle_arg req;
841 struct drm_bo_info_rep rep;
845 struct drm_bo_map_wait_idle_arg {
847 struct drm_bo_info_req req;
848 struct drm_bo_info_rep rep;
852 struct drm_bo_op_arg {
855 struct drm_bo_op_req req;
856 struct drm_bo_arg_rep rep;
862 struct drm_bo_set_pin_arg {
864 struct drm_bo_set_pin_req req;
865 struct drm_bo_info_rep rep;
869 #define DRM_BO_MEM_LOCAL 0
870 #define DRM_BO_MEM_TT 1
871 #define DRM_BO_MEM_VRAM 2
872 #define DRM_BO_MEM_PRIV0 3
873 #define DRM_BO_MEM_PRIV1 4
874 #define DRM_BO_MEM_PRIV2 5
875 #define DRM_BO_MEM_PRIV3 6
876 #define DRM_BO_MEM_PRIV4 7
878 #define DRM_BO_MEM_TYPES 8 /* For now. */
880 struct drm_mm_type_arg {
881 unsigned int mem_type;
884 struct drm_mm_init_arg {
888 unsigned int mem_type;
896 #define DRM_DISPLAY_INFO_LEN 32
897 #define DRM_OUTPUT_NAME_LEN 32
898 #define DRM_DISPLAY_MODE_LEN 32
900 struct drm_mode_modeinfo {
905 unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
906 unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
908 unsigned int vrefresh; /* vertical refresh * 1000 */
912 char name[DRM_DISPLAY_MODE_LEN];
915 struct drm_mode_card_res {
918 unsigned int __user *fb_id;
921 unsigned int __user *crtc_id;
924 unsigned int __user *output_id;
927 struct drm_mode_modeinfo __user *modes;
931 struct drm_mode_crtc {
932 unsigned int crtc_id; /**< Id */
933 unsigned int fb_id; /**< Id of framebuffer */
935 int x, y; /**< Position on the frameuffer */
937 unsigned int mode; /**< Current mode used */
940 unsigned int outputs; /**< Outputs that are connected */
943 unsigned int possibles; /**< Outputs that can be connected */
945 unsigned int __user *set_outputs; /**< Outputs to be connected */
951 struct drm_mode_get_output {
953 unsigned int output; /**< Id */
954 unsigned int crtc; /**< Id of crtc */
955 unsigned char name[DRM_OUTPUT_NAME_LEN];
957 unsigned int connection;
958 unsigned int mm_width, mm_height; /**< HxW in millimeters */
959 unsigned int subpixel;
962 unsigned int crtcs; /**< possible crtc to connect to */
965 unsigned int clones; /**< list of clones */
968 unsigned int __user *modes; /**< list of modes it supports */
972 struct drm_mode_fb_cmd {
973 unsigned int buffer_id;
974 unsigned int width, height;
981 struct drm_mode_mode_cmd {
982 unsigned int output_id;
983 unsigned int mode_id;
987 * \name Ioctls Definitions
991 #define DRM_IOCTL_BASE 'd'
992 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
993 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
994 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
995 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
997 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
998 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
999 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
1000 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
1001 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
1002 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
1003 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
1004 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
1006 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
1007 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
1008 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
1009 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
1010 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
1011 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
1012 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
1013 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
1014 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
1015 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
1016 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
1018 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
1020 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
1021 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
1023 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
1024 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
1025 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
1026 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
1027 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
1028 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
1029 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
1030 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
1031 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
1032 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
1033 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
1034 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
1035 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
1037 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
1038 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
1039 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
1040 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
1041 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
1042 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
1043 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
1044 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
1046 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
1047 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
1049 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
1051 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1053 #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
1054 #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
1055 #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
1056 #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
1058 #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
1059 #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
1060 #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
1061 #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
1062 #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
1063 #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
1064 #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
1065 #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
1067 #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
1068 #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
1069 #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
1070 #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
1071 #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
1072 #define DRM_IOCTL_BO_OP DRM_IOWR(0xd3, struct drm_bo_op_arg)
1073 #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
1074 #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1075 #define DRM_IOCTL_BO_SET_PIN DRM_IOWR(0xd6, struct drm_bo_set_pin_arg)
1077 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1078 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
1079 #define DRM_IOCTL_MODE_GETOUTPUT DRM_IOWR(0xA2, struct drm_mode_get_output)
1080 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
1081 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
1082 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
1083 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
1085 #define DRM_IOCTL_MODE_ADDMODE DRM_IOWR(0xA7, struct drm_mode_modeinfo)
1086 #define DRM_IOCTL_MODE_RMMODE DRM_IOWR(0xA8, unsigned int)
1087 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
1088 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
1092 * Device specific ioctls should only be in their respective headers
1093 * The device specific ioctl range is from 0x40 to 0x99.
1094 * Generic IOCTLS restart at 0xA0.
1096 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1097 * drmCommandReadWrite().
1099 #define DRM_COMMAND_BASE 0x40
1100 #define DRM_COMMAND_END 0xA0
1103 #if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)
1104 typedef struct drm_clip_rect drm_clip_rect_t;
1105 typedef struct drm_drawable_info drm_drawable_info_t;
1106 typedef struct drm_tex_region drm_tex_region_t;
1107 typedef struct drm_hw_lock drm_hw_lock_t;
1108 typedef struct drm_version drm_version_t;
1109 typedef struct drm_unique drm_unique_t;
1110 typedef struct drm_list drm_list_t;
1111 typedef struct drm_block drm_block_t;
1112 typedef struct drm_control drm_control_t;
1113 typedef enum drm_map_type drm_map_type_t;
1114 typedef enum drm_map_flags drm_map_flags_t;
1115 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1116 typedef struct drm_map drm_map_t;
1117 typedef struct drm_client drm_client_t;
1118 typedef enum drm_stat_type drm_stat_type_t;
1119 typedef struct drm_stats drm_stats_t;
1120 typedef enum drm_lock_flags drm_lock_flags_t;
1121 typedef struct drm_lock drm_lock_t;
1122 typedef enum drm_dma_flags drm_dma_flags_t;
1123 typedef struct drm_buf_desc drm_buf_desc_t;
1124 typedef struct drm_buf_info drm_buf_info_t;
1125 typedef struct drm_buf_free drm_buf_free_t;
1126 typedef struct drm_buf_pub drm_buf_pub_t;
1127 typedef struct drm_buf_map drm_buf_map_t;
1128 typedef struct drm_dma drm_dma_t;
1129 typedef union drm_wait_vblank drm_wait_vblank_t;
1130 typedef struct drm_agp_mode drm_agp_mode_t;
1131 typedef enum drm_ctx_flags drm_ctx_flags_t;
1132 typedef struct drm_ctx drm_ctx_t;
1133 typedef struct drm_ctx_res drm_ctx_res_t;
1134 typedef struct drm_draw drm_draw_t;
1135 typedef struct drm_update_draw drm_update_draw_t;
1136 typedef struct drm_auth drm_auth_t;
1137 typedef struct drm_irq_busid drm_irq_busid_t;
1138 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1139 typedef struct drm_agp_buffer drm_agp_buffer_t;
1140 typedef struct drm_agp_binding drm_agp_binding_t;
1141 typedef struct drm_agp_info drm_agp_info_t;
1142 typedef struct drm_scatter_gather drm_scatter_gather_t;
1143 typedef struct drm_set_version drm_set_version_t;
1145 typedef struct drm_fence_arg drm_fence_arg_t;
1146 typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1147 typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1148 typedef enum drm_bo_type drm_bo_type_t;