3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
66 # define DEPRECATED __attribute__ ((deprecated))
71 #if defined(__linux__)
72 #if defined(__KERNEL__)
73 #include <linux/config.h>
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
84 /* Prevent name collision when including sys/ioccom.h */
86 #include <sys/ioccom.h>
87 #define ioctl(a,b,c) xf86ioctl(a,b,c)
89 #include <sys/ioccom.h>
90 #endif /* __FreeBSD__ && xf86ioctl */
91 #define DRM_IOCTL_NR(n) ((n) & 0xff)
92 #define DRM_IOC_VOID IOC_VOID
93 #define DRM_IOC_READ IOC_OUT
94 #define DRM_IOC_WRITE IOC_IN
95 #define DRM_IOC_READWRITE IOC_INOUT
96 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
99 #define XFREE86_VERSION(major,minor,patch,snap) \
100 ((major << 16) | (minor << 8) | patch)
102 #ifndef CONFIG_XFREE86_VERSION
103 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
106 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
107 #define DRM_PROC_DEVICES "/proc/devices"
108 #define DRM_PROC_MISC "/proc/misc"
109 #define DRM_PROC_DRM "/proc/drm"
110 #define DRM_DEV_DRM "/dev/drm"
111 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
112 #define DRM_DEV_UID 0
113 #define DRM_DEV_GID 0
116 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
120 #if defined(__linux__) || defined(__NetBSD__)
121 #define DRM_MAJOR 226
123 #define DRM_MAX_MINOR 15
125 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
126 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
127 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
128 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
130 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
131 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
132 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
133 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
134 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
136 #if defined(__linux__)
137 #if defined(__KERNEL__)
138 typedef __u64 drm_u64_t;
140 typedef unsigned long long drm_u64_t;
143 typedef unsigned int drm_handle_t;
145 typedef unsigned long drm_handle_t; /**< To mapped regions */
147 typedef unsigned int drm_context_t; /**< GLXContext handle */
148 typedef unsigned int drm_drawable_t;
149 typedef unsigned int drm_magic_t; /**< Magic for authentication */
154 * \warning If you change this structure, make sure you change
155 * XF86DRIClipRectRec in the server as well
157 * \note KW: Actually it's illegal to change either for
158 * backwards-compatibility reasons.
160 typedef struct drm_clip_rect {
170 typedef struct drm_tex_region {
173 unsigned char in_use;
174 unsigned char padding;
181 * The lock structure is a simple cache-line aligned integer. To avoid
182 * processor bus contention on a multiprocessor system, there should not be any
183 * other data stored in the same cache line.
185 typedef struct drm_hw_lock {
186 __volatile__ unsigned int lock; /**< lock variable */
187 char padding[60]; /**< Pad to cache line */
190 /* This is beyond ugly, and only works on GCC. However, it allows me to use
191 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
192 * fix is to use uint32_t instead of size_t, but that fix will break existing
193 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
194 * eventually happen, though. I chose 'unsigned long' to be the fallback type
195 * because that works on all the platforms I know about. Hopefully, the
196 * real fix will happen before that bites us.
200 # define DRM_SIZE_T __SIZE_TYPE__
202 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
203 # define DRM_SIZE_T unsigned long
207 * DRM_IOCTL_VERSION ioctl argument type.
209 * \sa drmGetVersion().
211 typedef struct drm_version {
212 int version_major; /**< Major version */
213 int version_minor; /**< Minor version */
214 int version_patchlevel; /**< Patch level */
215 DRM_SIZE_T name_len; /**< Length of name buffer */
216 char __user *name; /**< Name of driver */
217 DRM_SIZE_T date_len; /**< Length of date buffer */
218 char __user *date; /**< User-space buffer to hold date */
219 DRM_SIZE_T desc_len; /**< Length of desc buffer */
220 char __user *desc; /**< User-space buffer to hold desc */
224 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
226 * \sa drmGetBusid() and drmSetBusId().
228 typedef struct drm_unique {
229 DRM_SIZE_T unique_len; /**< Length of unique */
230 char __user *unique; /**< Unique name for driver instantiation */
235 typedef struct drm_list {
236 int count; /**< Length of user-space structures */
237 drm_version_t __user *version;
240 typedef struct drm_block {
245 * DRM_IOCTL_CONTROL ioctl argument type.
247 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
249 typedef struct drm_control {
260 * Type of memory to map.
262 typedef enum drm_map_type {
263 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
264 _DRM_REGISTERS = 1, /**< no caching, no core dump */
265 _DRM_SHM = 2, /**< shared, cached */
266 _DRM_AGP = 3, /**< AGP/GART */
267 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
268 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
273 * Memory mapping flags.
275 typedef enum drm_map_flags {
276 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
277 _DRM_READ_ONLY = 0x02,
278 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
279 _DRM_KERNEL = 0x08, /**< kernel requires access */
280 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
281 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
282 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
285 typedef struct drm_ctx_priv_map {
286 unsigned int ctx_id; /**< Context requesting private mapping */
287 void *handle; /**< Handle of map */
288 } drm_ctx_priv_map_t;
291 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
296 typedef struct drm_map {
297 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
298 unsigned long size; /**< Requested physical size (bytes) */
299 drm_map_type_t type; /**< Type of memory to map */
300 drm_map_flags_t flags; /**< Flags */
301 void *handle; /**< User-space: "Handle" to pass to mmap() */
302 /**< Kernel-space: kernel-virtual address */
303 int mtrr; /**< MTRR slot used */
308 * DRM_IOCTL_GET_CLIENT ioctl argument type.
310 typedef struct drm_client {
311 int idx; /**< Which client desired? */
312 int auth; /**< Is client authenticated? */
313 unsigned long pid; /**< Process ID */
314 unsigned long uid; /**< User ID */
315 unsigned long magic; /**< Magic */
316 unsigned long iocs; /**< Ioctl count */
326 _DRM_STAT_VALUE, /**< Generic value */
327 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
328 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
330 _DRM_STAT_IRQ, /**< IRQ */
331 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
332 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
333 _DRM_STAT_DMA, /**< DMA */
334 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
335 _DRM_STAT_MISSED /**< Missed DMA opportunity */
336 /* Add to the *END* of the list */
340 * DRM_IOCTL_GET_STATS ioctl argument type.
342 typedef struct drm_stats {
346 drm_stat_type_t type;
351 * Hardware locking flags.
353 typedef enum drm_lock_flags {
354 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
355 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
356 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
357 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
358 /* These *HALT* flags aren't supported yet
359 -- they will be used to support the
360 full-screen DGA-like mode. */
361 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
362 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
366 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
368 * \sa drmGetLock() and drmUnlock().
370 typedef struct drm_lock {
372 drm_lock_flags_t flags;
379 * These values \e must match xf86drm.h.
383 typedef enum drm_dma_flags {
384 /* Flags for DMA buffer dispatch */
385 _DRM_DMA_BLOCK = 0x01, /**<
386 * Block until buffer dispatched.
388 * \note The buffer may not yet have
389 * been processed by the hardware --
390 * getting a hardware lock with the
391 * hardware quiescent will ensure
392 * that the buffer has been
395 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
396 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
398 /* Flags for DMA buffer request */
399 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
400 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
401 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
405 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
409 typedef struct drm_buf_desc {
410 int count; /**< Number of buffers of this size */
411 int size; /**< Size in bytes */
412 int low_mark; /**< Low water mark */
413 int high_mark; /**< High water mark */
415 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
416 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
417 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
418 _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */
420 unsigned long agp_start; /**<
421 * Start address of where the AGP buffers are
422 * in the AGP aperture
427 * DRM_IOCTL_INFO_BUFS ioctl argument type.
429 typedef struct drm_buf_info {
430 int count; /**< Number of buffers described in list */
431 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
435 * DRM_IOCTL_FREE_BUFS ioctl argument type.
437 typedef struct drm_buf_free {
447 typedef struct drm_buf_pub {
448 int idx; /**< Index into the master buffer list */
449 int total; /**< Buffer size */
450 int used; /**< Amount of buffer in use (for DMA) */
451 void __user *address; /**< Address of buffer */
455 * DRM_IOCTL_MAP_BUFS ioctl argument type.
457 typedef struct drm_buf_map {
458 int count; /**< Length of the buffer list */
459 #if defined(__cplusplus)
460 void __user *c_virtual;
462 void __user *virtual; /**< Mmap'd area in user-virtual */
464 drm_buf_pub_t __user *list; /**< Buffer information */
468 * DRM_IOCTL_DMA ioctl argument type.
470 * Indices here refer to the offset into the buffer list in drm_buf_get.
474 typedef struct drm_dma {
475 int context; /**< Context handle */
476 int send_count; /**< Number of buffers to send */
477 int __user *send_indices; /**< List of handles to buffers */
478 int __user *send_sizes; /**< Lengths of data to send */
479 drm_dma_flags_t flags; /**< Flags */
480 int request_count; /**< Number of buffers requested */
481 int request_size; /**< Desired size for buffers */
482 int __user *request_indices; /**< Buffer information */
483 int __user *request_sizes;
484 int granted_count; /**< Number of buffers granted */
488 _DRM_CONTEXT_PRESERVED = 0x01,
489 _DRM_CONTEXT_2DONLY = 0x02
493 * DRM_IOCTL_ADD_CTX ioctl argument type.
495 * \sa drmCreateContext() and drmDestroyContext().
497 typedef struct drm_ctx {
498 drm_context_t handle;
499 drm_ctx_flags_t flags;
503 * DRM_IOCTL_RES_CTX ioctl argument type.
505 typedef struct drm_ctx_res {
507 drm_ctx_t __user *contexts;
511 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
513 typedef struct drm_draw {
514 drm_drawable_t handle;
518 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
520 typedef struct drm_auth {
525 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
527 * \sa drmGetInterruptFromBusID().
529 typedef struct drm_irq_busid {
530 int irq; /**< IRQ number */
531 int busnum; /**< bus number */
532 int devnum; /**< device number */
533 int funcnum; /**< function number */
537 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
538 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
539 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
540 } drm_vblank_seq_type_t;
542 #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL
544 struct drm_wait_vblank_request {
545 drm_vblank_seq_type_t type;
546 unsigned int sequence;
547 unsigned long signal;
550 struct drm_wait_vblank_reply {
551 drm_vblank_seq_type_t type;
552 unsigned int sequence;
558 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
560 * \sa drmWaitVBlank().
562 typedef union drm_wait_vblank {
563 struct drm_wait_vblank_request request;
564 struct drm_wait_vblank_reply reply;
568 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
570 * \sa drmAgpEnable().
572 typedef struct drm_agp_mode {
573 unsigned long mode; /**< AGP mode */
577 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
579 * \sa drmAgpAlloc() and drmAgpFree().
581 typedef struct drm_agp_buffer {
582 unsigned long size; /**< In bytes -- will round to page boundary */
583 unsigned long handle; /**< Used for binding / unbinding */
584 unsigned long type; /**< Type of memory to allocate */
585 unsigned long physical; /**< Physical used by i810 */
589 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
591 * \sa drmAgpBind() and drmAgpUnbind().
593 typedef struct drm_agp_binding {
594 unsigned long handle; /**< From drm_agp_buffer */
595 unsigned long offset; /**< In bytes -- will round to page boundary */
599 * DRM_IOCTL_AGP_INFO ioctl argument type.
601 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
602 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
603 * drmAgpVendorId() and drmAgpDeviceId().
605 typedef struct drm_agp_info {
606 int agp_version_major;
607 int agp_version_minor;
609 unsigned long aperture_base; /**< physical address */
610 unsigned long aperture_size; /**< bytes */
611 unsigned long memory_allowed; /**< bytes */
612 unsigned long memory_used;
614 /** \name PCI information */
616 unsigned short id_vendor;
617 unsigned short id_device;
622 * DRM_IOCTL_SG_ALLOC ioctl argument type.
624 typedef struct drm_scatter_gather {
625 unsigned long size; /**< In bytes -- will round to page boundary */
626 unsigned long handle; /**< Used for mapping / unmapping */
627 } drm_scatter_gather_t;
630 * DRM_IOCTL_SET_VERSION ioctl argument type.
632 typedef struct drm_set_version {
641 #define DRM_FENCE_FLAG_EMIT 0x00000001
642 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
643 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
644 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
646 #define DRM_FENCE_EXE 0x00000001
648 typedef struct drm_fence_arg {
658 drm_fence_unreference,
667 #define DRM_TTM_FLAG_SHAREABLE 0x00000001
669 typedef struct drm_ttm_arg {
683 /* Buffer permissions, referring to how the GPU uses the buffers.
684 these translate to fence types used for the buffers.
685 Typically a texture buffer is read, A destination buffer is write and
686 a command (batch-) buffer is exe. Can be or-ed together. */
688 #define DRM_BO_FLAG_READ 0x00000001
689 #define DRM_BO_FLAG_WRITE 0x00000002
690 #define DRM_BO_FLAG_EXE 0x00000004
693 * Status flags. Can be read to determine the actual state of a buffer.
697 #define DRM_BO_FLAG_NO_EVICT 0x00000010
698 /* Always keep a system memory shadow to a vram buffer */
699 #define DRM_BO_FLAG_SHADOW_VRAM 0x00000020
700 /* When mapped for reading, make sure the buffer is cached even
701 if it means moving the buffer to system memory */
702 #define DRM_BO_FLAG_SHAREABLE 0x00000040
703 /* When there is a choice between VRAM and TT, prefer VRAM.
704 The default behaviour is to prefer TT. */
705 #define DRM_BO_FLAG_CACHED 0x00000080
706 /* The buffer is shareable with other processes */
709 #define DRM_BO_FLAG_READ_CACHED 0x00080000
710 /* The buffer is currently cached */
711 #define DRM_BO_FLAG_PREFER_VRAM 0x00040000
712 /* Bind this buffer cached if the hardware supports it. */
713 #define DRM_BO_FLAG_BIND_CACHED 0x0002000
715 /* Translation table aperture */
716 #define DRM_BO_FLAG_MEM_TT 0x01000000
718 #define DRM_BO_FLAG_MEM_VRAM 0x02000000
720 #define DRM_BO_FLAG_MEM_LOCAL 0x04000000
721 /* Memory flag mask */
722 #define DRM_BO_MASK_MEM 0xFF000000
724 /* When creating a buffer, Avoid system storage even if allowed */
725 #define DRM_BO_HINT_AVOID_LOCAL 0x00000001
726 /* Don't block on validate and map */
727 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
728 /* Don't place this buffer on the unfenced list.*/
729 #define DRM_BO_HINT_DONT_FENCE 0x00000004
730 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
731 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
734 /* Driver specific flags. Could be for example rendering engine */
735 #define DRM_BO_MASK_DRIVER 0x00F00000
745 typedef struct drm_bo_arg_request {
746 unsigned handle; /* User space handle */
752 drm_u64_t buffer_start;
767 } drm_bo_arg_request_t;
774 #define DRM_BO_REP_BUSY 0x00000001
776 typedef struct drm_bo_arg_reply {
784 drm_u64_t buffer_start;
785 unsigned fence_flags;
790 typedef struct drm_bo_arg{
793 drm_bo_arg_request_t req;
794 drm_bo_arg_reply_t rep;
798 typedef union drm_mm_init_arg{
807 drm_u64_t vr_p_offset;
809 drm_u64_t tt_p_offset;
811 drm_u64_t max_locked_pages;
814 drm_handle_t mm_sarea;
821 * \name Ioctls Definitions
825 #define DRM_IOCTL_BASE 'd'
826 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
827 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
828 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
829 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
831 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
832 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
833 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
834 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
835 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
836 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
837 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
838 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
840 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
841 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
842 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
843 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
844 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
845 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
846 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
847 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
848 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
849 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
850 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
852 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
854 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
855 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
857 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
858 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
859 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
860 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
861 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
862 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
863 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
864 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
865 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
866 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
867 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
868 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
869 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
871 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
872 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
873 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
874 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
875 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
876 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
877 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
878 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
880 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
881 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
883 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
886 #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
887 #define DRM_IOCTL_TTM DRM_IOWR(0x3c, drm_ttm_arg_t)
888 #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
889 #define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
895 * Device specific ioctls should only be in their respective headers
896 * The device specific ioctl range is from 0x40 to 0x99.
897 * Generic IOCTLS restart at 0xA0.
899 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
900 * drmCommandReadWrite().
902 #define DRM_COMMAND_BASE 0x40
903 #define DRM_COMMAND_END 0xA0