1 /* drm.h -- Header for Direct Rendering Manager -*- linux-c -*-
2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com
3 * Revised: Mon Feb 14 00:15:23 2000 by kevin@precisioninsight.com
5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/kernel/drm.h,v 1.5 2000/02/23 04:47:26 martin Exp $
30 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
37 #include <asm/ioctl.h> /* For _IO* macros */
39 #define DRM_PROC_DEVICES "/proc/devices"
40 #define DRM_PROC_MISC "/proc/misc"
41 #define DRM_PROC_DRM "/proc/drm"
42 #define DRM_DEV_DRM "/dev/drm"
43 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
48 #define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
49 #define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
50 #define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
51 #define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */
53 #define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */
54 #define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */
55 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
56 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
57 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
59 typedef unsigned long drm_handle_t;
60 typedef unsigned int drm_context_t;
61 typedef unsigned int drm_drawable_t;
62 typedef unsigned int drm_magic_t;
64 /* Warning: If you change this structure, make sure you change
65 * XF86DRIClipRectRec in the server as well */
67 typedef struct drm_clip_rect {
74 /* Seperate include files for the i810/mga specific structures */
78 typedef struct drm_version {
79 int version_major; /* Major version */
80 int version_minor; /* Minor version */
81 int version_patchlevel;/* Patch level */
82 size_t name_len; /* Length of name buffer */
83 char *name; /* Name of driver */
84 size_t date_len; /* Length of date buffer */
85 char *date; /* User-space buffer to hold date */
86 size_t desc_len; /* Length of desc buffer */
87 char *desc; /* User-space buffer to hold desc */
90 typedef struct drm_unique {
91 size_t unique_len; /* Length of unique */
92 char *unique; /* Unique name for driver instantiation */
95 typedef struct drm_list {
96 int count; /* Length of user-space structures */
97 drm_version_t *version;
100 typedef struct drm_block {
104 typedef struct drm_control {
114 typedef enum drm_map_type {
115 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */
116 _DRM_REGISTERS = 1, /* no caching, no core dump */
117 _DRM_SHM = 2, /* shared, cached */
118 _DRM_AGP = 3 /* AGP/GART */
121 typedef enum drm_map_flags {
122 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */
123 _DRM_READ_ONLY = 0x02,
124 _DRM_LOCKED = 0x04, /* shared, cached, locked */
125 _DRM_KERNEL = 0x08, /* kernel requires access */
126 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */
127 _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */
130 typedef struct drm_map {
131 unsigned long offset; /* Requested physical address (0 for SAREA)*/
132 unsigned long size; /* Requested physical size (bytes) */
133 drm_map_type_t type; /* Type of memory to map */
134 drm_map_flags_t flags; /* Flags */
135 void *handle; /* User-space: "Handle" to pass to mmap */
136 /* Kernel-space: kernel-virtual address */
137 int mtrr; /* MTRR slot used */
141 typedef enum drm_lock_flags {
142 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */
143 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */
144 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */
145 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */
146 /* These *HALT* flags aren't supported yet
147 -- they will be used to support the
148 full-screen DGA-like mode. */
149 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */
150 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */
153 typedef struct drm_lock {
155 drm_lock_flags_t flags;
158 typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */
159 /* Flags for DMA buffer dispatch */
160 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched.
161 Note, the buffer may not yet have
162 been processed by the hardware --
163 getting a hardware lock with the
164 hardware quiescent will ensure
165 that the buffer has been
167 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */
168 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */
170 /* Flags for DMA buffer request */
171 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */
172 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */
173 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */
176 typedef struct drm_buf_desc {
177 int count; /* Number of buffers of this size */
178 int size; /* Size in bytes */
179 int low_mark; /* Low water mark */
180 int high_mark; /* High water mark */
182 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */
183 _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */
185 unsigned long agp_start; /* Start address of where the agp buffers
186 * are in the agp aperture */
189 typedef struct drm_buf_info {
190 int count; /* Entries in list */
191 drm_buf_desc_t *list;
194 typedef struct drm_buf_free {
199 typedef struct drm_buf_pub {
200 int idx; /* Index into master buflist */
201 int total; /* Buffer size */
202 int used; /* Amount of buffer in use (for DMA) */
203 void *address; /* Address of buffer */
206 typedef struct drm_buf_map {
207 int count; /* Length of buflist */
208 void *virtual; /* Mmaped area in user-virtual */
209 drm_buf_pub_t *list; /* Buffer information */
212 typedef struct drm_dma {
213 /* Indices here refer to the offset into
214 buflist in drm_buf_get_t. */
215 int context; /* Context handle */
216 int send_count; /* Number of buffers to send */
217 int *send_indices; /* List of handles to buffers */
218 int *send_sizes; /* Lengths of data to send */
219 drm_dma_flags_t flags; /* Flags */
220 int request_count; /* Number of buffers requested */
221 int request_size; /* Desired size for buffers */
222 int *request_indices; /* Buffer information */
224 int granted_count; /* Number of buffers granted */
228 _DRM_CONTEXT_PRESERVED = 0x01,
229 _DRM_CONTEXT_2DONLY = 0x02
232 typedef struct drm_ctx {
233 drm_context_t handle;
234 drm_ctx_flags_t flags;
237 typedef struct drm_ctx_res {
242 typedef struct drm_draw {
243 drm_drawable_t handle;
246 typedef struct drm_auth {
250 typedef struct drm_irq_busid {
257 typedef struct drm_agp_mode {
261 /* For drm_agp_alloc -- allocated a buffer */
262 typedef struct drm_agp_buffer {
263 unsigned long size; /* In bytes -- will round to page boundary */
264 unsigned long handle; /* Used for BIND/UNBIND ioctls */
265 unsigned long type; /* Type of memory to allocate */
266 unsigned long physical; /* Physical used by i810 */
269 /* For drm_agp_bind */
270 typedef struct drm_agp_binding {
271 unsigned long handle; /* From drm_agp_buffer */
272 unsigned long offset; /* In bytes -- will round to page boundary */
275 typedef struct drm_agp_info {
276 int agp_version_major;
277 int agp_version_minor;
279 unsigned long aperture_base; /* physical address */
280 unsigned long aperture_size; /* bytes */
281 unsigned long memory_allowed; /* bytes */
282 unsigned long memory_used;
284 /* PCI information */
285 unsigned short id_vendor;
286 unsigned short id_device;
289 #define DRM_IOCTL_BASE 'd'
290 #define DRM_IOCTL_NR(n) _IOC_NR(n)
291 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
292 #define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size)
293 #define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size)
294 #define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size)
297 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
298 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
299 #define DRM_IOCTL_GET_MAGIC DRM_IOW( 0x02, drm_auth_t)
300 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
302 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
303 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
304 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
305 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
306 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
307 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
308 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
309 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
310 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
311 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
312 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
314 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
315 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
316 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
317 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
318 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
319 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
320 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
321 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
322 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
323 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
324 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
325 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
326 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
328 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
329 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
330 #define DRM_IOCTL_AGP_ENABLE DRM_IOR( 0x32, drm_agp_mode_t)
331 #define DRM_IOCTL_AGP_INFO DRM_IOW( 0x33, drm_agp_info_t)
332 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
333 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
334 #define DRM_IOCTL_AGP_BIND DRM_IOWR(0x36, drm_agp_binding_t)
335 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
337 /* Mga specific ioctls */
338 #define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t)
339 #define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t)
340 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t)
341 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t)
342 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t)
343 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t )
345 /* I810 specific ioctls */
346 #define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t)
347 #define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t)
348 #define DRM_IOCTL_I810_DMA DRM_IOW( 0x42, drm_i810_general_t)
349 #define DRM_IOCTL_I810_FLUSH DRM_IO ( 0x43)
350 #define DRM_IOCTL_I810_GETAGE DRM_IO ( 0x44)