3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
95 #if defined(__linux__) || defined(__NetBSD__)
98 #define DRM_MAX_MINOR 15
100 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
101 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
102 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
103 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
105 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
106 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
107 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
108 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
109 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
111 #if defined(__linux__)
112 typedef unsigned int drm_handle_t;
114 #include <sys/types.h>
115 typedef unsigned long drm_handle_t; /**< To mapped regions */
117 typedef unsigned int drm_context_t; /**< GLXContext handle */
118 typedef unsigned int drm_drawable_t;
119 typedef unsigned int drm_magic_t; /**< Magic for authentication */
124 * \warning If you change this structure, make sure you change
125 * XF86DRIClipRectRec in the server as well
127 * \note KW: Actually it's illegal to change either for
128 * backwards-compatibility reasons.
130 struct drm_clip_rect {
140 struct drm_tex_region {
143 unsigned char in_use;
144 unsigned char padding;
151 * The lock structure is a simple cache-line aligned integer. To avoid
152 * processor bus contention on a multiprocessor system, there should not be any
153 * other data stored in the same cache line.
156 __volatile__ unsigned int lock; /**< lock variable */
157 char padding[60]; /**< Pad to cache line */
160 /* This is beyond ugly, and only works on GCC. However, it allows me to use
161 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
162 * fix is to use uint32_t instead of size_t, but that fix will break existing
163 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
164 * eventually happen, though. I chose 'unsigned long' to be the fallback type
165 * because that works on all the platforms I know about. Hopefully, the
166 * real fix will happen before that bites us.
170 # define DRM_SIZE_T __SIZE_TYPE__
172 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
173 # define DRM_SIZE_T unsigned long
177 * DRM_IOCTL_VERSION ioctl argument type.
179 * \sa drmGetVersion().
182 int version_major; /**< Major version */
183 int version_minor; /**< Minor version */
184 int version_patchlevel; /**< Patch level */
185 DRM_SIZE_T name_len; /**< Length of name buffer */
186 char __user *name; /**< Name of driver */
187 DRM_SIZE_T date_len; /**< Length of date buffer */
188 char __user *date; /**< User-space buffer to hold date */
189 DRM_SIZE_T desc_len; /**< Length of desc buffer */
190 char __user *desc; /**< User-space buffer to hold desc */
194 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
196 * \sa drmGetBusid() and drmSetBusId().
199 DRM_SIZE_T unique_len; /**< Length of unique */
200 char __user *unique; /**< Unique name for driver instantiation */
206 int count; /**< Length of user-space structures */
207 struct drm_version __user *version;
215 * DRM_IOCTL_CONTROL ioctl argument type.
217 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
230 * Type of memory to map.
233 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
234 _DRM_REGISTERS = 1, /**< no caching, no core dump */
235 _DRM_SHM = 2, /**< shared, cached */
236 _DRM_AGP = 3, /**< AGP/GART */
237 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
238 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
243 * Memory mapping flags.
246 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
247 _DRM_READ_ONLY = 0x02,
248 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
249 _DRM_KERNEL = 0x08, /**< kernel requires access */
250 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
251 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
252 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
253 _DRM_DRIVER = 0x80 /**< Managed by driver */
256 struct drm_ctx_priv_map {
257 unsigned int ctx_id; /**< Context requesting private mapping */
258 void *handle; /**< Handle of map */
262 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
268 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
269 unsigned long size; /**< Requested physical size (bytes) */
270 enum drm_map_type type; /**< Type of memory to map */
271 enum drm_map_flags flags; /**< Flags */
272 void *handle; /**< User-space: "Handle" to pass to mmap() */
273 /**< Kernel-space: kernel-virtual address */
274 int mtrr; /**< MTRR slot used */
279 * DRM_IOCTL_GET_CLIENT ioctl argument type.
282 int idx; /**< Which client desired? */
283 int auth; /**< Is client authenticated? */
284 unsigned long pid; /**< Process ID */
285 unsigned long uid; /**< User ID */
286 unsigned long magic; /**< Magic */
287 unsigned long iocs; /**< Ioctl count */
297 _DRM_STAT_VALUE, /**< Generic value */
298 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
299 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
301 _DRM_STAT_IRQ, /**< IRQ */
302 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
303 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
304 _DRM_STAT_DMA, /**< DMA */
305 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
306 _DRM_STAT_MISSED /**< Missed DMA opportunity */
307 /* Add to the *END* of the list */
311 * DRM_IOCTL_GET_STATS ioctl argument type.
317 enum drm_stat_type type;
322 * Hardware locking flags.
324 enum drm_lock_flags {
325 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
326 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
327 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
328 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
329 /* These *HALT* flags aren't supported yet
330 -- they will be used to support the
331 full-screen DGA-like mode. */
332 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
333 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
337 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
339 * \sa drmGetLock() and drmUnlock().
343 enum drm_lock_flags flags;
350 * These values \e must match xf86drm.h.
355 /* Flags for DMA buffer dispatch */
356 _DRM_DMA_BLOCK = 0x01, /**<
357 * Block until buffer dispatched.
359 * \note The buffer may not yet have
360 * been processed by the hardware --
361 * getting a hardware lock with the
362 * hardware quiescent will ensure
363 * that the buffer has been
366 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
367 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
369 /* Flags for DMA buffer request */
370 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
371 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
372 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
376 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
380 struct drm_buf_desc {
381 int count; /**< Number of buffers of this size */
382 int size; /**< Size in bytes */
383 int low_mark; /**< Low water mark */
384 int high_mark; /**< High water mark */
386 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
387 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
388 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
389 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
390 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
392 unsigned long agp_start; /**<
393 * Start address of where the AGP buffers are
394 * in the AGP aperture
399 * DRM_IOCTL_INFO_BUFS ioctl argument type.
401 struct drm_buf_info {
402 int count; /**< Number of buffers described in list */
403 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
407 * DRM_IOCTL_FREE_BUFS ioctl argument type.
409 struct drm_buf_free {
420 int idx; /**< Index into the master buffer list */
421 int total; /**< Buffer size */
422 int used; /**< Amount of buffer in use (for DMA) */
423 void __user *address; /**< Address of buffer */
427 * DRM_IOCTL_MAP_BUFS ioctl argument type.
430 int count; /**< Length of the buffer list */
431 #if defined(__cplusplus)
432 void __user *c_virtual;
434 void __user *virtual; /**< Mmap'd area in user-virtual */
436 struct drm_buf_pub __user *list; /**< Buffer information */
440 * DRM_IOCTL_DMA ioctl argument type.
442 * Indices here refer to the offset into the buffer list in drm_buf_get.
447 int context; /**< Context handle */
448 int send_count; /**< Number of buffers to send */
449 int __user *send_indices; /**< List of handles to buffers */
450 int __user *send_sizes; /**< Lengths of data to send */
451 enum drm_dma_flags flags; /**< Flags */
452 int request_count; /**< Number of buffers requested */
453 int request_size; /**< Desired size for buffers */
454 int __user *request_indices; /**< Buffer information */
455 int __user *request_sizes;
456 int granted_count; /**< Number of buffers granted */
460 _DRM_CONTEXT_PRESERVED = 0x01,
461 _DRM_CONTEXT_2DONLY = 0x02
465 * DRM_IOCTL_ADD_CTX ioctl argument type.
467 * \sa drmCreateContext() and drmDestroyContext().
470 drm_context_t handle;
471 enum drm_ctx_flags flags;
475 * DRM_IOCTL_RES_CTX ioctl argument type.
479 struct drm_ctx __user *contexts;
483 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
486 drm_drawable_t handle;
490 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
493 DRM_DRAWABLE_CLIPRECTS,
494 } drm_drawable_info_type_t;
496 struct drm_update_draw {
497 drm_drawable_t handle;
500 unsigned long long data;
504 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
511 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
513 * \sa drmGetInterruptFromBusID().
515 struct drm_irq_busid {
516 int irq; /**< IRQ number */
517 int busnum; /**< bus number */
518 int devnum; /**< device number */
519 int funcnum; /**< function number */
522 enum drm_vblank_seq_type {
523 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
524 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
525 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
526 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
527 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
528 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
531 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
532 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
533 _DRM_VBLANK_NEXTONMISS)
535 struct drm_wait_vblank_request {
536 enum drm_vblank_seq_type type;
537 unsigned int sequence;
538 unsigned long signal;
541 struct drm_wait_vblank_reply {
542 enum drm_vblank_seq_type type;
543 unsigned int sequence;
549 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
551 * \sa drmWaitVBlank().
553 union drm_wait_vblank {
554 struct drm_wait_vblank_request request;
555 struct drm_wait_vblank_reply reply;
558 /* Handle monitor hotplug.
560 * May want to extend this later to pass reply information which
561 * details the connectors which generated the hotplug event.
562 * Some chipsets can't determine that though, and we'd need to leave
563 * it to the higher levels to determine exactly what changed.
565 enum drm_hotplug_seq_type {
566 _DRM_HOTPLUG_SIGNAL = 0x00000001, /**< Send signal instead of blocking */
568 struct drm_wait_hotplug_request {
569 enum drm_hotplug_seq_type type;
570 unsigned long signal;
573 struct drm_wait_hotplug_reply {
574 enum drm_hotplug_seq_type type;
575 unsigned int counter;
581 * DRM_IOCTL_WAIT_HOTPLUG ioctl argument type.
583 * \sa drmWaitHotplug().
585 union drm_wait_hotplug {
586 struct drm_wait_hotplug_request request;
587 struct drm_wait_hotplug_reply reply;
590 enum drm_modeset_ctl_cmd {
591 _DRM_PRE_MODESET = 1,
592 _DRM_POST_MODESET = 2,
597 * DRM_IOCTL_MODESET_CTL ioctl argument type
599 * \sa drmModesetCtl().
601 struct drm_modeset_ctl {
607 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
609 * \sa drmAgpEnable().
611 struct drm_agp_mode {
612 unsigned long mode; /**< AGP mode */
616 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
618 * \sa drmAgpAlloc() and drmAgpFree().
620 struct drm_agp_buffer {
621 unsigned long size; /**< In bytes -- will round to page boundary */
622 unsigned long handle; /**< Used for binding / unbinding */
623 unsigned long type; /**< Type of memory to allocate */
624 unsigned long physical; /**< Physical used by i810 */
628 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
630 * \sa drmAgpBind() and drmAgpUnbind().
632 struct drm_agp_binding {
633 unsigned long handle; /**< From drm_agp_buffer */
634 unsigned long offset; /**< In bytes -- will round to page boundary */
638 * DRM_IOCTL_AGP_INFO ioctl argument type.
640 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
641 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
642 * drmAgpVendorId() and drmAgpDeviceId().
644 struct drm_agp_info {
645 int agp_version_major;
646 int agp_version_minor;
648 unsigned long aperture_base; /**< physical address */
649 unsigned long aperture_size; /**< bytes */
650 unsigned long memory_allowed; /**< bytes */
651 unsigned long memory_used;
653 /** \name PCI information */
655 unsigned short id_vendor;
656 unsigned short id_device;
661 * DRM_IOCTL_SG_ALLOC ioctl argument type.
663 struct drm_scatter_gather {
664 unsigned long size; /**< In bytes -- will round to page boundary */
665 unsigned long handle; /**< Used for mapping / unmapping */
669 * DRM_IOCTL_SET_VERSION ioctl argument type.
671 struct drm_set_version {
679 #define DRM_FENCE_FLAG_EMIT 0x00000001
680 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
682 * On hardware with no interrupt events for operation completion,
683 * indicates that the kernel should sleep while waiting for any blocking
684 * operation to complete rather than spinning.
686 * Has no effect otherwise.
688 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
689 #define DRM_FENCE_FLAG_NO_USER 0x00000010
691 /* Reserved for driver use */
692 #define DRM_FENCE_MASK_DRIVER 0xFF000000
694 #define DRM_FENCE_TYPE_EXE 0x00000001
696 struct drm_fence_arg {
698 unsigned int fence_class;
701 unsigned int signaled;
703 unsigned int sequence;
705 uint64_t expand_pad[2]; /*Future expansion */
708 /* Buffer permissions, referring to how the GPU uses the buffers.
709 * these translate to fence types used for the buffers.
710 * Typically a texture buffer is read, A destination buffer is write and
711 * a command (batch-) buffer is exe. Can be or-ed together.
714 #define DRM_BO_FLAG_READ (1ULL << 0)
715 #define DRM_BO_FLAG_WRITE (1ULL << 1)
716 #define DRM_BO_FLAG_EXE (1ULL << 2)
719 * All of the bits related to access mode
721 #define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE)
723 * Status flags. Can be read to determine the actual state of a buffer.
724 * Can also be set in the buffer mask before validation.
728 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
729 * available to root and must be manually removed before buffer manager shutdown
733 #define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
736 * Mask: Require that the buffer is placed in mappable memory when validated.
737 * If not set the buffer may or may not be in mappable memory when validated.
738 * Flags: If set, the buffer is in mappable memory.
740 #define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
742 /* Mask: The buffer should be shareable with other processes.
743 * Flags: The buffer is shareable with other processes.
745 #define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
747 /* Mask: If set, place the buffer in cache-coherent memory if available.
748 * If clear, never place the buffer in cache coherent memory if validated.
749 * Flags: The buffer is currently in cache-coherent memory.
751 #define DRM_BO_FLAG_CACHED (1ULL << 7)
753 /* Mask: Make sure that every time this buffer is validated,
754 * it ends up on the same location provided that the memory mask is the same.
755 * The buffer will also not be evicted when claiming space for
756 * other buffers. Basically a pinned buffer but it may be thrown out as
757 * part of buffer manager shutdown or locking.
758 * Flags: Acknowledge.
760 #define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
762 /* Mask: Make sure the buffer is in cached memory when mapped. In conjunction
763 * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART
764 * with unsnooped PTEs instead of snooped, by using chipset-specific cache
765 * flushing at bind time. A better name might be DRM_BO_FLAG_TT_UNSNOOPED,
766 * as the eviction to local memory (TTM unbind) on map is just a side effect
767 * to prevent aggressive cache prefetch from the GPU disturbing the cache
768 * management that the DRM is doing.
770 * Flags: Acknowledge.
771 * Buffers allocated with this flag should not be used for suballocators
772 * This type may have issues on CPUs with over-aggressive caching
773 * http://marc.info/?l=linux-kernel&m=102376926732464&w=2
775 #define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
778 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
779 * Flags: Acknowledge.
781 #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
784 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
785 * Flags: Acknowledge.
787 #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
788 #define DRM_BO_FLAG_TILE (1ULL << 15)
791 * Memory type flags that can be or'ed together in the mask, but only
792 * one appears in flags.
796 #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
797 /* Translation table memory */
798 #define DRM_BO_FLAG_MEM_TT (1ULL << 25)
800 #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
801 /* Up to the driver to define. */
802 #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
803 #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
804 #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
805 #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
806 #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
807 /* We can add more of these now with a 64-bit flag type */
810 * This is a mask covering all of the memory type flags; easier to just
811 * use a single constant than a bunch of | values. It covers
812 * DRM_BO_FLAG_MEM_LOCAL through DRM_BO_FLAG_MEM_PRIV4
814 #define DRM_BO_MASK_MEM 0x00000000FF000000ULL
816 * This adds all of the CPU-mapping options in with the memory
817 * type to label all bits which change how the page gets mapped
819 #define DRM_BO_MASK_MEMTYPE (DRM_BO_MASK_MEM | \
820 DRM_BO_FLAG_CACHED_MAPPED | \
821 DRM_BO_FLAG_CACHED | \
822 DRM_BO_FLAG_MAPPABLE)
824 /* Driver-private flags */
825 #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
828 * Don't block on validate and map. Instead, return EBUSY.
830 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
832 * Don't place this buffer on the unfenced list. This means
833 * that the buffer will not end up having a fence associated
834 * with it as a result of this operation
836 #define DRM_BO_HINT_DONT_FENCE 0x00000004
838 * On hardware with no interrupt events for operation completion,
839 * indicates that the kernel should sleep while waiting for any blocking
840 * operation to complete rather than spinning.
842 * Has no effect otherwise.
844 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
846 * The client has compute relocations refering to this buffer using the
847 * offset in the presumed_offset field. If that offset ends up matching
848 * where this buffer lands, the kernel is free to skip executing those
851 #define DRM_BO_HINT_PRESUMED_OFFSET 0x00000010
853 #define DRM_BO_INIT_MAGIC 0xfe769812
854 #define DRM_BO_INIT_MAJOR 1
855 #define DRM_BO_INIT_MINOR 0
856 #define DRM_BO_INIT_PATCH 0
859 struct drm_bo_info_req {
864 unsigned int fence_class;
865 unsigned int desired_tile_stride;
866 unsigned int tile_info;
868 uint64_t presumed_offset;
871 struct drm_bo_create_req {
874 uint64_t buffer_start;
876 unsigned int page_alignment;
884 #define DRM_BO_REP_BUSY 0x00000001
886 struct drm_bo_info_rep {
888 uint64_t proposed_flags;
892 uint64_t buffer_start;
894 unsigned int fence_flags;
895 unsigned int rep_flags;
896 unsigned int page_alignment;
897 unsigned int desired_tile_stride;
898 unsigned int hw_tile_stride;
899 unsigned int tile_info;
901 uint64_t expand_pad[4]; /*Future expansion */
904 struct drm_bo_arg_rep {
905 struct drm_bo_info_rep bo_info;
910 struct drm_bo_create_arg {
912 struct drm_bo_create_req req;
913 struct drm_bo_info_rep rep;
917 struct drm_bo_handle_arg {
921 struct drm_bo_reference_info_arg {
923 struct drm_bo_handle_arg req;
924 struct drm_bo_info_rep rep;
928 struct drm_bo_map_wait_idle_arg {
930 struct drm_bo_info_req req;
931 struct drm_bo_info_rep rep;
935 struct drm_bo_op_req {
941 unsigned int arg_handle;
942 struct drm_bo_info_req bo_req;
946 struct drm_bo_op_arg {
949 struct drm_bo_op_req req;
950 struct drm_bo_arg_rep rep;
957 #define DRM_BO_MEM_LOCAL 0
958 #define DRM_BO_MEM_TT 1
959 #define DRM_BO_MEM_VRAM 2
960 #define DRM_BO_MEM_PRIV0 3
961 #define DRM_BO_MEM_PRIV1 4
962 #define DRM_BO_MEM_PRIV2 5
963 #define DRM_BO_MEM_PRIV3 6
964 #define DRM_BO_MEM_PRIV4 7
966 #define DRM_BO_MEM_TYPES 8 /* For now. */
968 #define DRM_BO_LOCK_UNLOCK_BM (1 << 0)
969 #define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1)
971 struct drm_bo_version_arg {
977 struct drm_mm_type_arg {
978 unsigned int mem_type;
979 unsigned int lock_flags;
982 struct drm_mm_init_arg {
986 unsigned int mem_type;
991 struct drm_mm_info_arg {
992 unsigned int mem_type;
1000 #define DRM_DISPLAY_INFO_LEN 32
1001 #define DRM_CONNECTOR_NAME_LEN 32
1002 #define DRM_DISPLAY_MODE_LEN 32
1003 #define DRM_PROP_NAME_LEN 32
1005 #define DRM_MODE_TYPE_BUILTIN (1<<0)
1006 #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
1007 #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
1008 #define DRM_MODE_TYPE_PREFERRED (1<<3)
1009 #define DRM_MODE_TYPE_DEFAULT (1<<4)
1010 #define DRM_MODE_TYPE_USERDEF (1<<5)
1011 #define DRM_MODE_TYPE_DRIVER (1<<6)
1013 struct drm_mode_modeinfo {
1015 unsigned short hdisplay, hsync_start, hsync_end, htotal, hskew;
1016 unsigned short vdisplay, vsync_start, vsync_end, vtotal, vscan;
1018 unsigned int vrefresh; /* vertical refresh * 1000 */
1022 char name[DRM_DISPLAY_MODE_LEN];
1025 struct drm_mode_card_res {
1027 uint64_t crtc_id_ptr;
1028 uint64_t connector_id_ptr;
1029 uint64_t encoder_id_ptr;
1032 int count_connectors;
1034 int min_width, max_width;
1035 int min_height, max_height;
1038 struct drm_mode_crtc {
1039 uint64_t set_connectors_ptr;
1041 unsigned int crtc_id; /**< Id */
1042 unsigned int fb_id; /**< Id of framebuffer */
1044 int x, y; /**< Position on the frameuffer */
1046 int count_connectors;
1047 unsigned int connectors; /**< Connectors that are connected */
1049 int count_possibles;
1050 unsigned int possibles; /**< Connectors that can be connected */
1051 uint32_t gamma_size;
1053 struct drm_mode_modeinfo mode;
1056 struct drm_mode_get_encoder {
1058 uint32_t encoder_type;
1059 uint32_t encoder_id;
1061 unsigned int crtc; /**< Id of crtc */
1066 #define DRM_MODE_ENCODER_NONE 0
1067 #define DRM_MODE_ENCODER_DAC 1
1068 #define DRM_MODE_ENCODER_TMDS 2
1069 #define DRM_MODE_ENCODER_LVDS 3
1070 #define DRM_MODE_ENCODER_TVDAC 4
1072 struct drm_mode_get_connector {
1074 uint64_t encoders_ptr;
1077 uint64_t prop_values_ptr;
1083 unsigned int encoder; /**< Current Encoder */
1084 unsigned int connector; /**< Id */
1085 unsigned int connector_type;
1086 unsigned int connector_type_id;
1088 unsigned int connection;
1089 unsigned int mm_width, mm_height; /**< HxW in millimeters */
1090 unsigned int subpixel;
1093 #define DRM_MODE_PROP_PENDING (1<<0)
1094 #define DRM_MODE_PROP_RANGE (1<<1)
1095 #define DRM_MODE_PROP_IMMUTABLE (1<<2)
1096 #define DRM_MODE_PROP_ENUM (1<<3) // enumerated type with text strings
1097 #define DRM_MODE_PROP_BLOB (1<<4)
1099 struct drm_mode_property_enum {
1101 unsigned char name[DRM_PROP_NAME_LEN];
1104 struct drm_mode_get_property {
1105 uint64_t values_ptr; /* values and blob lengths */
1106 uint64_t enum_blob_ptr; /* enum and blob id ptrs */
1108 unsigned int prop_id;
1110 unsigned char name[DRM_PROP_NAME_LEN];
1113 int count_enum_blobs;
1116 struct drm_mode_connector_set_property {
1118 unsigned int prop_id;
1119 unsigned int connector_id;
1122 struct drm_mode_get_blob {
1128 struct drm_mode_fb_cmd {
1129 unsigned int buffer_id;
1130 unsigned int width, height;
1133 unsigned int handle;
1137 struct drm_mode_mode_cmd {
1138 unsigned int connector_id;
1139 struct drm_mode_modeinfo mode;
1142 #define DRM_MODE_CURSOR_BO 0x01
1143 #define DRM_MODE_CURSOR_MOVE 0x02
1146 * depending on the value in flags diffrent members are used.
1152 * handle - if 0 turns the cursor of
1159 struct drm_mode_cursor {
1166 unsigned int handle;
1170 * oh so ugly hotplug
1172 struct drm_mode_hotplug {
1176 struct drm_mode_crtc_lut {
1179 uint32_t gamma_size;
1187 * \name Ioctls Definitions
1191 #define DRM_IOCTL_BASE 'd'
1192 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
1193 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
1194 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
1195 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
1197 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
1198 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
1199 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
1200 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
1201 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
1202 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
1203 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
1204 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
1205 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
1207 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
1208 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
1209 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
1210 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
1211 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
1212 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
1213 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
1214 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
1215 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
1216 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
1217 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
1219 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
1221 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
1222 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
1224 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
1225 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
1227 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
1228 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
1229 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
1230 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
1231 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
1232 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
1233 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
1234 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
1235 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
1236 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
1237 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
1238 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
1239 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
1241 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
1242 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
1243 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
1244 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
1245 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
1246 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
1247 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
1248 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
1250 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
1251 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
1253 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
1255 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
1257 #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
1258 #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
1259 #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
1260 #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
1262 #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
1263 #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
1264 #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
1265 #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
1266 #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
1267 #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
1268 #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
1269 #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
1271 #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
1272 #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
1273 #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
1274 #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
1275 #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
1276 #define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
1277 #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
1278 #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
1279 #define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg)
1280 #define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg)
1282 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1283 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
1284 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA2, struct drm_mode_get_connector)
1285 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA3, struct drm_mode_crtc)
1286 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xA4, struct drm_mode_fb_cmd)
1287 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xA5, unsigned int)
1288 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xA6, struct drm_mode_fb_cmd)
1290 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xA7, struct drm_mode_connector_set_property)
1291 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xA8, struct drm_mode_get_blob)
1292 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
1293 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xAA, struct drm_mode_mode_cmd)
1295 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAB, struct drm_mode_get_property)
1296 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xAC, struct drm_mode_cursor)
1297 #define DRM_IOCTL_MODE_HOTPLUG DRM_IOWR(0xAD, struct drm_mode_hotplug)
1298 #define DRM_IOCTL_WAIT_HOTPLUG DRM_IOWR(0xAE, union drm_wait_hotplug)
1300 #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xAF, struct drm_mode_fb_cmd)
1301 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xB0, struct drm_mode_get_encoder)
1302 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xB1, struct drm_mode_crtc_lut)
1303 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xB2, struct drm_mode_crtc_lut)
1308 * Device specific ioctls should only be in their respective headers
1309 * The device specific ioctl range is from 0x40 to 0x99.
1310 * Generic IOCTLS restart at 0xA0.
1312 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1313 * drmCommandReadWrite().
1315 #define DRM_COMMAND_BASE 0x40
1316 #define DRM_COMMAND_END 0xA0
1319 #if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)
1320 typedef struct drm_clip_rect drm_clip_rect_t;
1321 typedef struct drm_tex_region drm_tex_region_t;
1322 typedef struct drm_hw_lock drm_hw_lock_t;
1323 typedef struct drm_version drm_version_t;
1324 typedef struct drm_unique drm_unique_t;
1325 typedef struct drm_list drm_list_t;
1326 typedef struct drm_block drm_block_t;
1327 typedef struct drm_control drm_control_t;
1328 typedef enum drm_map_type drm_map_type_t;
1329 typedef enum drm_map_flags drm_map_flags_t;
1330 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1331 typedef struct drm_map drm_map_t;
1332 typedef struct drm_client drm_client_t;
1333 typedef enum drm_stat_type drm_stat_type_t;
1334 typedef struct drm_stats drm_stats_t;
1335 typedef enum drm_lock_flags drm_lock_flags_t;
1336 typedef struct drm_lock drm_lock_t;
1337 typedef enum drm_dma_flags drm_dma_flags_t;
1338 typedef struct drm_buf_desc drm_buf_desc_t;
1339 typedef struct drm_buf_info drm_buf_info_t;
1340 typedef struct drm_buf_free drm_buf_free_t;
1341 typedef struct drm_buf_pub drm_buf_pub_t;
1342 typedef struct drm_buf_map drm_buf_map_t;
1343 typedef struct drm_dma drm_dma_t;
1344 typedef union drm_wait_vblank drm_wait_vblank_t;
1345 typedef struct drm_agp_mode drm_agp_mode_t;
1346 typedef enum drm_ctx_flags drm_ctx_flags_t;
1347 typedef struct drm_ctx drm_ctx_t;
1348 typedef struct drm_ctx_res drm_ctx_res_t;
1349 typedef struct drm_draw drm_draw_t;
1350 typedef struct drm_update_draw drm_update_draw_t;
1351 typedef struct drm_auth drm_auth_t;
1352 typedef struct drm_irq_busid drm_irq_busid_t;
1353 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1354 typedef struct drm_agp_buffer drm_agp_buffer_t;
1355 typedef struct drm_agp_binding drm_agp_binding_t;
1356 typedef struct drm_agp_info drm_agp_info_t;
1357 typedef struct drm_scatter_gather drm_scatter_gather_t;
1358 typedef struct drm_set_version drm_set_version_t;
1360 typedef struct drm_fence_arg drm_fence_arg_t;
1361 typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1362 typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1363 typedef enum drm_bo_type drm_bo_type_t;