shared/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "radeon.h"
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39
  40
  41 /* CP microcode (from ATI) */
  42 static u32 R200_cp_microcode[][2] = {
  43         { 0x21007000, 0000000000 },
  44         { 0x20007000, 0000000000 },
  45         { 0x000000ab, 0x00000004 },
  46         { 0x000000af, 0x00000004 },
  47         { 0x66544a49, 0000000000 },
  48         { 0x49494174, 0000000000 },
  49         { 0x54517d83, 0000000000 },
  50         { 0x498d8b64, 0000000000 },
  51         { 0x49494949, 0000000000 },
  52         { 0x49da493c, 0000000000 },
  53         { 0x49989898, 0000000000 },
  54         { 0xd34949d5, 0000000000 },
  55         { 0x9dc90e11, 0000000000 },
  56         { 0xce9b9b9b, 0000000000 },
  57         { 0x000f0000, 0x00000016 },
  58         { 0x352e232c, 0000000000 },
  59         { 0x00000013, 0x00000004 },
  60         { 0x000f0000, 0x00000016 },
  61         { 0x352e272c, 0000000000 },
  62         { 0x000f0001, 0x00000016 },
  63         { 0x3239362f, 0000000000 },
  64         { 0x000077ef, 0x00000002 },
  65         { 0x00061000, 0x00000002 },
  66         { 0x00000020, 0x0000001a },
  67         { 0x00004000, 0x0000001e },
  68         { 0x00061000, 0x00000002 },
  69         { 0x00000020, 0x0000001a },
  70         { 0x00004000, 0x0000001e },
  71         { 0x00061000, 0x00000002 },
  72         { 0x00000020, 0x0000001a },
  73         { 0x00004000, 0x0000001e },
  74         { 0x00000016, 0x00000004 },
  75         { 0x0003802a, 0x00000002 },
  76         { 0x040067e0, 0x00000002 },
  77         { 0x00000016, 0x00000004 },
  78         { 0x000077e0, 0x00000002 },
  79         { 0x00065000, 0x00000002 },
  80         { 0x000037e1, 0x00000002 },
  81         { 0x040067e1, 0x00000006 },
  82         { 0x000077e0, 0x00000002 },
  83         { 0x000077e1, 0x00000002 },
  84         { 0x000077e1, 0x00000006 },
  85         { 0xffffffff, 0000000000 },
  86         { 0x10000000, 0000000000 },
  87         { 0x0003802a, 0x00000002 },
  88         { 0x040067e0, 0x00000006 },
  89         { 0x00007675, 0x00000002 },
  90         { 0x00007676, 0x00000002 },
  91         { 0x00007677, 0x00000002 },
  92         { 0x00007678, 0x00000006 },
  93         { 0x0003802b, 0x00000002 },
  94         { 0x04002676, 0x00000002 },
  95         { 0x00007677, 0x00000002 },
  96         { 0x00007678, 0x00000006 },
  97         { 0x0000002e, 0x00000018 },
  98         { 0x0000002e, 0x00000018 },
  99         { 0000000000, 0x00000006 },
 100         { 0x0000002f, 0x00000018 },
 101         { 0x0000002f, 0x00000018 },
 102         { 0000000000, 0x00000006 },
 103         { 0x01605000, 0x00000002 },
 104         { 0x00065000, 0x00000002 },
 105         { 0x00098000, 0x00000002 },
 106         { 0x00061000, 0x00000002 },
 107         { 0x64c0603d, 0x00000004 },
 108         { 0x00080000, 0x00000016 },
 109         { 0000000000, 0000000000 },
 110         { 0x0400251d, 0x00000002 },
 111         { 0x00007580, 0x00000002 },
 112         { 0x00067581, 0x00000002 },
 113         { 0x04002580, 0x00000002 },
 114         { 0x00067581, 0x00000002 },
 115         { 0x00000046, 0x00000004 },
 116         { 0x00005000, 0000000000 },
 117         { 0x00061000, 0x00000002 },
 118         { 0x0000750e, 0x00000002 },
 119         { 0x00019000, 0x00000002 },
 120         { 0x00011055, 0x00000014 },
 121         { 0x00000055, 0x00000012 },
 122         { 0x0400250f, 0x00000002 },
 123         { 0x0000504a, 0x00000004 },
 124         { 0x00007565, 0x00000002 },
 125         { 0x00007566, 0x00000002 },
 126         { 0x00000051, 0x00000004 },
 127         { 0x01e655b4, 0x00000002 },
 128         { 0x4401b0dc, 0x00000002 },
 129         { 0x01c110dc, 0x00000002 },
 130         { 0x2666705d, 0x00000018 },
 131         { 0x040c2565, 0x00000002 },
 132         { 0x0000005d, 0x00000018 },
 133         { 0x04002564, 0x00000002 },
 134         { 0x00007566, 0x00000002 },
 135         { 0x00000054, 0x00000004 },
 136         { 0x00401060, 0x00000008 },
 137         { 0x00101000, 0x00000002 },
 138         { 0x000d80ff, 0x00000002 },
 139         { 0x00800063, 0x00000008 },
 140         { 0x000f9000, 0x00000002 },
 141         { 0x000e00ff, 0x00000002 },
 142         { 0000000000, 0x00000006 },
 143         { 0x00000080, 0x00000018 },
 144         { 0x00000054, 0x00000004 },
 145         { 0x00007576, 0x00000002 },
 146         { 0x00065000, 0x00000002 },
 147         { 0x00009000, 0x00000002 },
 148         { 0x00041000, 0x00000002 },
 149         { 0x0c00350e, 0x00000002 },
 150         { 0x00049000, 0x00000002 },
 151         { 0x00051000, 0x00000002 },
 152         { 0x01e785f8, 0x00000002 },
 153         { 0x00200000, 0x00000002 },
 154         { 0x00600073, 0x0000000c },
 155         { 0x00007563, 0x00000002 },
 156         { 0x006075f0, 0x00000021 },
 157         { 0x20007068, 0x00000004 },
 158         { 0x00005068, 0x00000004 },
 159         { 0x00007576, 0x00000002 },
 160         { 0x00007577, 0x00000002 },
 161         { 0x0000750e, 0x00000002 },
 162         { 0x0000750f, 0x00000002 },
 163         { 0x00a05000, 0x00000002 },
 164         { 0x00600076, 0x0000000c },
 165         { 0x006075f0, 0x00000021 },
 166         { 0x000075f8, 0x00000002 },
 167         { 0x00000076, 0x00000004 },
 168         { 0x000a750e, 0x00000002 },
 169         { 0x0020750f, 0x00000002 },
 170         { 0x00600079, 0x00000004 },
 171         { 0x00007570, 0x00000002 },
 172         { 0x00007571, 0x00000002 },
 173         { 0x00007572, 0x00000006 },
 174         { 0x00005000, 0x00000002 },
 175         { 0x00a05000, 0x00000002 },
 176         { 0x00007568, 0x00000002 },
 177         { 0x00061000, 0x00000002 },
 178         { 0x00000084, 0x0000000c },
 179         { 0x00058000, 0x00000002 },
 180         { 0x0c607562, 0x00000002 },
 181         { 0x00000086, 0x00000004 },
 182         { 0x00600085, 0x00000004 },
 183         { 0x400070dd, 0000000000 },
 184         { 0x000380dd, 0x00000002 },
 185         { 0x00000093, 0x0000001c },
 186         { 0x00065095, 0x00000018 },
 187         { 0x040025bb, 0x00000002 },
 188         { 0x00061096, 0x00000018 },
 189         { 0x040075bc, 0000000000 },
 190         { 0x000075bb, 0x00000002 },
 191         { 0x000075bc, 0000000000 },
 192         { 0x00090000, 0x00000006 },
 193         { 0x00090000, 0x00000002 },
 194         { 0x000d8002, 0x00000006 },
 195         { 0x00005000, 0x00000002 },
 196         { 0x00007821, 0x00000002 },
 197         { 0x00007800, 0000000000 },
 198         { 0x00007821, 0x00000002 },
 199         { 0x00007800, 0000000000 },
 200         { 0x01665000, 0x00000002 },
 201         { 0x000a0000, 0x00000002 },
 202         { 0x000671cc, 0x00000002 },
 203         { 0x0286f1cd, 0x00000002 },
 204         { 0x000000a3, 0x00000010 },
 205         { 0x21007000, 0000000000 },
 206         { 0x000000aa, 0x0000001c },
 207         { 0x00065000, 0x00000002 },
 208         { 0x000a0000, 0x00000002 },
 209         { 0x00061000, 0x00000002 },
 210         { 0x000b0000, 0x00000002 },
 211         { 0x38067000, 0x00000002 },
 212         { 0x000a00a6, 0x00000004 },
 213         { 0x20007000, 0000000000 },
 214         { 0x01200000, 0x00000002 },
 215         { 0x20077000, 0x00000002 },
 216         { 0x01200000, 0x00000002 },
 217         { 0x20007000, 0000000000 },
 218         { 0x00061000, 0x00000002 },
 219         { 0x0120751b, 0x00000002 },
 220         { 0x8040750a, 0x00000002 },
 221         { 0x8040750b, 0x00000002 },
 222         { 0x00110000, 0x00000002 },
 223         { 0x000380dd, 0x00000002 },
 224         { 0x000000bd, 0x0000001c },
 225         { 0x00061096, 0x00000018 },
 226         { 0x844075bd, 0x00000002 },
 227         { 0x00061095, 0x00000018 },
 228         { 0x840075bb, 0x00000002 },
 229         { 0x00061096, 0x00000018 },
 230         { 0x844075bc, 0x00000002 },
 231         { 0x000000c0, 0x00000004 },
 232         { 0x804075bd, 0x00000002 },
 233         { 0x800075bb, 0x00000002 },
 234         { 0x804075bc, 0x00000002 },
 235         { 0x00108000, 0x00000002 },
 236         { 0x01400000, 0x00000002 },
 237         { 0x006000c4, 0x0000000c },
 238         { 0x20c07000, 0x00000020 },
 239         { 0x000000c6, 0x00000012 },
 240         { 0x00800000, 0x00000006 },
 241         { 0x0080751d, 0x00000006 },
 242         { 0x000025bb, 0x00000002 },
 243         { 0x000040c0, 0x00000004 },
 244         { 0x0000775c, 0x00000002 },
 245         { 0x00a05000, 0x00000002 },
 246         { 0x00661000, 0x00000002 },
 247         { 0x0460275d, 0x00000020 },
 248         { 0x00004000, 0000000000 },
 249         { 0x00007999, 0x00000002 },
 250         { 0x00a05000, 0x00000002 },
 251         { 0x00661000, 0x00000002 },
 252         { 0x0460299b, 0x00000020 },
 253         { 0x00004000, 0000000000 },
 254         { 0x01e00830, 0x00000002 },
 255         { 0x21007000, 0000000000 },
 256         { 0x00005000, 0x00000002 },
 257         { 0x00038042, 0x00000002 },
 258         { 0x040025e0, 0x00000002 },
 259         { 0x000075e1, 0000000000 },
 260         { 0x00000001, 0000000000 },
 261         { 0x000380d9, 0x00000002 },
 262         { 0x04007394, 0000000000 },
 263         { 0000000000, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299 };
 300
 301
 302 static u32 radeon_cp_microcode[][2] = {
 303         { 0x21007000, 0000000000 },
 304         { 0x20007000, 0000000000 },
 305         { 0x000000b4, 0x00000004 },
 306         { 0x000000b8, 0x00000004 },
 307         { 0x6f5b4d4c, 0000000000 },
 308         { 0x4c4c427f, 0000000000 },
 309         { 0x5b568a92, 0000000000 },
 310         { 0x4ca09c6d, 0000000000 },
 311         { 0xad4c4c4c, 0000000000 },
 312         { 0x4ce1af3d, 0000000000 },
 313         { 0xd8afafaf, 0000000000 },
 314         { 0xd64c4cdc, 0000000000 },
 315         { 0x4cd10d10, 0000000000 },
 316         { 0x000f0000, 0x00000016 },
 317         { 0x362f242d, 0000000000 },
 318         { 0x00000012, 0x00000004 },
 319         { 0x000f0000, 0x00000016 },
 320         { 0x362f282d, 0000000000 },
 321         { 0x000380e7, 0x00000002 },
 322         { 0x04002c97, 0x00000002 },
 323         { 0x000f0001, 0x00000016 },
 324         { 0x333a3730, 0000000000 },
 325         { 0x000077ef, 0x00000002 },
 326         { 0x00061000, 0x00000002 },
 327         { 0x00000021, 0x0000001a },
 328         { 0x00004000, 0x0000001e },
 329         { 0x00061000, 0x00000002 },
 330         { 0x00000021, 0x0000001a },
 331         { 0x00004000, 0x0000001e },
 332         { 0x00061000, 0x00000002 },
 333         { 0x00000021, 0x0000001a },
 334         { 0x00004000, 0x0000001e },
 335         { 0x00000017, 0x00000004 },
 336         { 0x0003802b, 0x00000002 },
 337         { 0x040067e0, 0x00000002 },
 338         { 0x00000017, 0x00000004 },
 339         { 0x000077e0, 0x00000002 },
 340         { 0x00065000, 0x00000002 },
 341         { 0x000037e1, 0x00000002 },
 342         { 0x040067e1, 0x00000006 },
 343         { 0x000077e0, 0x00000002 },
 344         { 0x000077e1, 0x00000002 },
 345         { 0x000077e1, 0x00000006 },
 346         { 0xffffffff, 0000000000 },
 347         { 0x10000000, 0000000000 },
 348         { 0x0003802b, 0x00000002 },
 349         { 0x040067e0, 0x00000006 },
 350         { 0x00007675, 0x00000002 },
 351         { 0x00007676, 0x00000002 },
 352         { 0x00007677, 0x00000002 },
 353         { 0x00007678, 0x00000006 },
 354         { 0x0003802c, 0x00000002 },
 355         { 0x04002676, 0x00000002 },
 356         { 0x00007677, 0x00000002 },
 357         { 0x00007678, 0x00000006 },
 358         { 0x0000002f, 0x00000018 },
 359         { 0x0000002f, 0x00000018 },
 360         { 0000000000, 0x00000006 },
 361         { 0x00000030, 0x00000018 },
 362         { 0x00000030, 0x00000018 },
 363         { 0000000000, 0x00000006 },
 364         { 0x01605000, 0x00000002 },
 365         { 0x00065000, 0x00000002 },
 366         { 0x00098000, 0x00000002 },
 367         { 0x00061000, 0x00000002 },
 368         { 0x64c0603e, 0x00000004 },
 369         { 0x000380e6, 0x00000002 },
 370         { 0x040025c5, 0x00000002 },
 371         { 0x00080000, 0x00000016 },
 372         { 0000000000, 0000000000 },
 373         { 0x0400251d, 0x00000002 },
 374         { 0x00007580, 0x00000002 },
 375         { 0x00067581, 0x00000002 },
 376         { 0x04002580, 0x00000002 },
 377         { 0x00067581, 0x00000002 },
 378         { 0x00000049, 0x00000004 },
 379         { 0x00005000, 0000000000 },
 380         { 0x000380e6, 0x00000002 },
 381         { 0x040025c5, 0x00000002 },
 382         { 0x00061000, 0x00000002 },
 383         { 0x0000750e, 0x00000002 },
 384         { 0x00019000, 0x00000002 },
 385         { 0x00011055, 0x00000014 },
 386         { 0x00000055, 0x00000012 },
 387         { 0x0400250f, 0x00000002 },
 388         { 0x0000504f, 0x00000004 },
 389         { 0x000380e6, 0x00000002 },
 390         { 0x040025c5, 0x00000002 },
 391         { 0x00007565, 0x00000002 },
 392         { 0x00007566, 0x00000002 },
 393         { 0x00000058, 0x00000004 },
 394         { 0x000380e6, 0x00000002 },
 395         { 0x040025c5, 0x00000002 },
 396         { 0x01e655b4, 0x00000002 },
 397         { 0x4401b0e4, 0x00000002 },
 398         { 0x01c110e4, 0x00000002 },
 399         { 0x26667066, 0x00000018 },
 400         { 0x040c2565, 0x00000002 },
 401         { 0x00000066, 0x00000018 },
 402         { 0x04002564, 0x00000002 },
 403         { 0x00007566, 0x00000002 },
 404         { 0x0000005d, 0x00000004 },
 405         { 0x00401069, 0x00000008 },
 406         { 0x00101000, 0x00000002 },
 407         { 0x000d80ff, 0x00000002 },
 408         { 0x0080006c, 0x00000008 },
 409         { 0x000f9000, 0x00000002 },
 410         { 0x000e00ff, 0x00000002 },
 411         { 0000000000, 0x00000006 },
 412         { 0x0000008f, 0x00000018 },
 413         { 0x0000005b, 0x00000004 },
 414         { 0x000380e6, 0x00000002 },
 415         { 0x040025c5, 0x00000002 },
 416         { 0x00007576, 0x00000002 },
 417         { 0x00065000, 0x00000002 },
 418         { 0x00009000, 0x00000002 },
 419         { 0x00041000, 0x00000002 },
 420         { 0x0c00350e, 0x00000002 },
 421         { 0x00049000, 0x00000002 },
 422         { 0x00051000, 0x00000002 },
 423         { 0x01e785f8, 0x00000002 },
 424         { 0x00200000, 0x00000002 },
 425         { 0x0060007e, 0x0000000c },
 426         { 0x00007563, 0x00000002 },
 427         { 0x006075f0, 0x00000021 },
 428         { 0x20007073, 0x00000004 },
 429         { 0x00005073, 0x00000004 },
 430         { 0x000380e6, 0x00000002 },
 431         { 0x040025c5, 0x00000002 },
 432         { 0x00007576, 0x00000002 },
 433         { 0x00007577, 0x00000002 },
 434         { 0x0000750e, 0x00000002 },
 435         { 0x0000750f, 0x00000002 },
 436         { 0x00a05000, 0x00000002 },
 437         { 0x00600083, 0x0000000c },
 438         { 0x006075f0, 0x00000021 },
 439         { 0x000075f8, 0x00000002 },
 440         { 0x00000083, 0x00000004 },
 441         { 0x000a750e, 0x00000002 },
 442         { 0x000380e6, 0x00000002 },
 443         { 0x040025c5, 0x00000002 },
 444         { 0x0020750f, 0x00000002 },
 445         { 0x00600086, 0x00000004 },
 446         { 0x00007570, 0x00000002 },
 447         { 0x00007571, 0x00000002 },
 448         { 0x00007572, 0x00000006 },
 449         { 0x000380e6, 0x00000002 },
 450         { 0x040025c5, 0x00000002 },
 451         { 0x00005000, 0x00000002 },
 452         { 0x00a05000, 0x00000002 },
 453         { 0x00007568, 0x00000002 },
 454         { 0x00061000, 0x00000002 },
 455         { 0x00000095, 0x0000000c },
 456         { 0x00058000, 0x00000002 },
 457         { 0x0c607562, 0x00000002 },
 458         { 0x00000097, 0x00000004 },
 459         { 0x000380e6, 0x00000002 },
 460         { 0x040025c5, 0x00000002 },
 461         { 0x00600096, 0x00000004 },
 462         { 0x400070e5, 0000000000 },
 463         { 0x000380e6, 0x00000002 },
 464         { 0x040025c5, 0x00000002 },
 465         { 0x000380e5, 0x00000002 },
 466         { 0x000000a8, 0x0000001c },
 467         { 0x000650aa, 0x00000018 },
 468         { 0x040025bb, 0x00000002 },
 469         { 0x000610ab, 0x00000018 },
 470         { 0x040075bc, 0000000000 },
 471         { 0x000075bb, 0x00000002 },
 472         { 0x000075bc, 0000000000 },
 473         { 0x00090000, 0x00000006 },
 474         { 0x00090000, 0x00000002 },
 475         { 0x000d8002, 0x00000006 },
 476         { 0x00007832, 0x00000002 },
 477         { 0x00005000, 0x00000002 },
 478         { 0x000380e7, 0x00000002 },
 479         { 0x04002c97, 0x00000002 },
 480         { 0x00007820, 0x00000002 },
 481         { 0x00007821, 0x00000002 },
 482         { 0x00007800, 0000000000 },
 483         { 0x01200000, 0x00000002 },
 484         { 0x20077000, 0x00000002 },
 485         { 0x01200000, 0x00000002 },
 486         { 0x20007000, 0x00000002 },
 487         { 0x00061000, 0x00000002 },
 488         { 0x0120751b, 0x00000002 },
 489         { 0x8040750a, 0x00000002 },
 490         { 0x8040750b, 0x00000002 },
 491         { 0x00110000, 0x00000002 },
 492         { 0x000380e5, 0x00000002 },
 493         { 0x000000c6, 0x0000001c },
 494         { 0x000610ab, 0x00000018 },
 495         { 0x844075bd, 0x00000002 },
 496         { 0x000610aa, 0x00000018 },
 497         { 0x840075bb, 0x00000002 },
 498         { 0x000610ab, 0x00000018 },
 499         { 0x844075bc, 0x00000002 },
 500         { 0x000000c9, 0x00000004 },
 501         { 0x804075bd, 0x00000002 },
 502         { 0x800075bb, 0x00000002 },
 503         { 0x804075bc, 0x00000002 },
 504         { 0x00108000, 0x00000002 },
 505         { 0x01400000, 0x00000002 },
 506         { 0x006000cd, 0x0000000c },
 507         { 0x20c07000, 0x00000020 },
 508         { 0x000000cf, 0x00000012 },
 509         { 0x00800000, 0x00000006 },
 510         { 0x0080751d, 0x00000006 },
 511         { 0000000000, 0000000000 },
 512         { 0x0000775c, 0x00000002 },
 513         { 0x00a05000, 0x00000002 },
 514         { 0x00661000, 0x00000002 },
 515         { 0x0460275d, 0x00000020 },
 516         { 0x00004000, 0000000000 },
 517         { 0x01e00830, 0x00000002 },
 518         { 0x21007000, 0000000000 },
 519         { 0x6464614d, 0000000000 },
 520         { 0x69687420, 0000000000 },
 521         { 0x00000073, 0000000000 },
 522         { 0000000000, 0000000000 },
 523         { 0x00005000, 0x00000002 },
 524         { 0x000380d0, 0x00000002 },
 525         { 0x040025e0, 0x00000002 },
 526         { 0x000075e1, 0000000000 },
 527         { 0x00000001, 0000000000 },
 528         { 0x000380e0, 0x00000002 },
 529         { 0x04002394, 0x00000002 },
 530         { 0x00005000, 0000000000 },
 531         { 0000000000, 0000000000 },
 532         { 0000000000, 0000000000 },
 533         { 0x00000008, 0000000000 },
 534         { 0x00000004, 0000000000 },
 535         { 0000000000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559 };
 560
 561
 562 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 563 {
 564         drm_radeon_private_t *dev_priv = dev->dev_private;
 565
 566         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 567         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 568 }
 569
 570 #if RADEON_FIFO_DEBUG
 571 static void radeon_status( drm_radeon_private_t *dev_priv )
 572 {
 573         printk( "%s:\n", __FUNCTION__ );
 574         printk( "RBBM_STATUS = 0x%08x\n",
 575                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 576         printk( "CP_RB_RTPR = 0x%08x\n",
 577                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 578         printk( "CP_RB_WTPR = 0x%08x\n",
 579                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 580         printk( "AIC_CNTL = 0x%08x\n",
 581                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 582         printk( "AIC_STAT = 0x%08x\n",
 583                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 584         printk( "AIC_PT_BASE = 0x%08x\n",
 585                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 586         printk( "TLB_ADDR = 0x%08x\n",
 587                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 588         printk( "TLB_DATA = 0x%08x\n",
 589                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 590 }
 591 #endif
 592
 593
 594 /* ================================================================
 595  * Engine, FIFO control
 596  */
 597
 598 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 599 {
 600         u32 tmp;
 601         int i;
 602
 603         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 604
 605         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 606         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 607         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 608
 609         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 610                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 611                        & RADEON_RB2D_DC_BUSY) ) {
 612                         return 0;
 613                 }
 614                 DRM_UDELAY( 1 );
 615         }
 616
 617 #if RADEON_FIFO_DEBUG
 618         DRM_ERROR( "failed!\n" );
 619         radeon_status( dev_priv );
 620 #endif
 621         return DRM_ERR(EBUSY);
 622 }
 623
 624 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 625                                     int entries )
 626 {
 627         int i;
 628
 629         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 630
 631         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 632                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 633                               & RADEON_RBBM_FIFOCNT_MASK );
 634                 if ( slots >= entries ) return 0;
 635                 DRM_UDELAY( 1 );
 636         }
 637
 638 #if RADEON_FIFO_DEBUG
 639         DRM_ERROR( "failed!\n" );
 640         radeon_status( dev_priv );
 641 #endif
 642         return DRM_ERR(EBUSY);
 643 }
 644
 645 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 646 {
 647         int i, ret;
 648
 649         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 650
 651         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 652         if ( ret ) return ret;
 653
 654         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 655                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 656                        & RADEON_RBBM_ACTIVE) ) {
 657                         radeon_do_pixcache_flush( dev_priv );
 658                         return 0;
 659                 }
 660                 DRM_UDELAY( 1 );
 661         }
 662
 663 #if RADEON_FIFO_DEBUG
 664         DRM_ERROR( "failed!\n" );
 665         radeon_status( dev_priv );
 666 #endif
 667         return DRM_ERR(EBUSY);
 668 }
 669
 670
 671 /* ================================================================
 672  * CP control, initialization
 673  */
 674
 675 /* Load the microcode for the CP */
 676 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 677 {
 678         int i;
 679         DRM_DEBUG( "\n" );
 680
 681         radeon_do_wait_for_idle( dev_priv );
 682
 683         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 684
 685         if (dev_priv->is_r200)
 686         {
 687                 DRM_INFO("Loading R200 Microcode\n");
 688                 for ( i = 0 ; i < 256 ; i++ )
 689                 {
 690                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 691                                       R200_cp_microcode[i][1] );
 692                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 693                                       R200_cp_microcode[i][0] );
 694                 }
 695         }
 696         else
 697         {
 698                 for ( i = 0 ; i < 256 ; i++ ) {
 699                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 700                                       radeon_cp_microcode[i][1] );
 701                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 702                                       radeon_cp_microcode[i][0] );
 703                 }
 704         }
 705 }
 706
 707 /* Flush any pending commands to the CP.  This should only be used just
 708  * prior to a wait for idle, as it informs the engine that the command
 709  * stream is ending.
 710  */
 711 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 712 {
 713         DRM_DEBUG( "\n" );
 714 #if 0
 715         u32 tmp;
 716
 717         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 718         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 719 #endif
 720 }
 721
 722 /* Wait for the CP to go idle.
 723  */
 724 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 725 {
 726         RING_LOCALS;
 727         DRM_DEBUG( "\n" );
 728
 729         BEGIN_RING( 6 );
 730
 731         RADEON_PURGE_CACHE();
 732         RADEON_PURGE_ZCACHE();
 733         RADEON_WAIT_UNTIL_IDLE();
 734
 735         ADVANCE_RING();
 736         COMMIT_RING();
 737
 738         return radeon_do_wait_for_idle( dev_priv );
 739 }
 740
 741 /* Start the Command Processor.
 742  */
 743 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 744 {
 745         RING_LOCALS;
 746         DRM_DEBUG( "\n" );
 747
 748         radeon_do_wait_for_idle( dev_priv );
 749
 750         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 751
 752         dev_priv->cp_running = 1;
 753
 754         BEGIN_RING( 6 );
 755
 756         RADEON_PURGE_CACHE();
 757         RADEON_PURGE_ZCACHE();
 758         RADEON_WAIT_UNTIL_IDLE();
 759
 760         ADVANCE_RING();
 761         COMMIT_RING();
 762 }
 763
 764 /* Reset the Command Processor.  This will not flush any pending
 765  * commands, so you must wait for the CP command stream to complete
 766  * before calling this routine.
 767  */
 768 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 769 {
 770         u32 cur_read_ptr;
 771         DRM_DEBUG( "\n" );
 772
 773         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 774         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 775         *dev_priv->ring.head = cur_read_ptr;
 776         dev_priv->ring.tail = cur_read_ptr;
 777 }
 778
 779 /* Stop the Command Processor.  This will not flush any pending
 780  * commands, so you must flush the command stream and wait for the CP
 781  * to go idle before calling this routine.
 782  */
 783 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 784 {
 785         DRM_DEBUG( "\n" );
 786
 787         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 788
 789         dev_priv->cp_running = 0;
 790 }
 791
 792 /* Reset the engine.  This will stop the CP if it is running.
 793  */
 794 static int radeon_do_engine_reset( drm_device_t *dev )
 795 {
 796         drm_radeon_private_t *dev_priv = dev->dev_private;
 797         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 798         DRM_DEBUG( "\n" );
 799
 800         radeon_do_pixcache_flush( dev_priv );
 801
 802         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 803         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 804
 805         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 806                                               RADEON_FORCEON_MCLKA |
 807                                               RADEON_FORCEON_MCLKB |
 808                                               RADEON_FORCEON_YCLKA |
 809                                               RADEON_FORCEON_YCLKB |
 810                                               RADEON_FORCEON_MC |
 811                                               RADEON_FORCEON_AIC ) );
 812
 813         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 814
 815         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 816                                                 RADEON_SOFT_RESET_CP |
 817                                                 RADEON_SOFT_RESET_HI |
 818                                                 RADEON_SOFT_RESET_SE |
 819                                                 RADEON_SOFT_RESET_RE |
 820                                                 RADEON_SOFT_RESET_PP |
 821                                                 RADEON_SOFT_RESET_E2 |
 822                                                 RADEON_SOFT_RESET_RB ) );
 823         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 824         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 825                                                 ~( RADEON_SOFT_RESET_CP |
 826                                                    RADEON_SOFT_RESET_HI |
 827                                                    RADEON_SOFT_RESET_SE |
 828                                                    RADEON_SOFT_RESET_RE |
 829                                                    RADEON_SOFT_RESET_PP |
 830                                                    RADEON_SOFT_RESET_E2 |
 831                                                    RADEON_SOFT_RESET_RB ) ) );
 832         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 833
 834
 835         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 836         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 837         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 838
 839         /* Reset the CP ring */
 840         radeon_do_cp_reset( dev_priv );
 841
 842         /* The CP is no longer running after an engine reset */
 843         dev_priv->cp_running = 0;
 844
 845         /* Reset any pending vertex, indirect buffers */
 846         radeon_freelist_reset( dev );
 847
 848         return 0;
 849 }
 850
 851 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 852                                         drm_radeon_private_t *dev_priv )
 853 {
 854         u32 ring_start, cur_read_ptr;
 855         u32 tmp;
 856
 857         /* Initialize the memory controller */
 858         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 859                       (dev_priv->agp_vm_start - 1) & 0xffff0000 );
 860
 861         if ( !dev_priv->is_pci ) {
 862                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 863                               (((dev_priv->agp_vm_start - 1 +
 864                                  dev_priv->agp_size) & 0xffff0000) |
 865                                (dev_priv->agp_vm_start >> 16)) );
 866         }
 867
 868 #if __REALLY_HAVE_AGP
 869         if ( !dev_priv->is_pci )
 870                 ring_start = (dev_priv->cp_ring->offset
 871                               - dev->agp->base
 872                               + dev_priv->agp_vm_start);
 873        else
 874 #endif
 875                 ring_start = (dev_priv->cp_ring->offset
 876                               - dev->sg->handle
 877                               + dev_priv->agp_vm_start);
 878
 879         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 880
 881         /* Set the write pointer delay */
 882         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 883         RADEON_READ( RADEON_CP_RB_WPTR_DELAY ); /* read back to propagate */
 884
 885         /* Initialize the ring buffer's read and write pointers */
 886         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 887         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 888         *dev_priv->ring.head = cur_read_ptr;
 889         dev_priv->ring.tail = cur_read_ptr;
 890
 891         if ( !dev_priv->is_pci ) {
 892                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 893                               dev_priv->ring_rptr->offset );
 894         } else {
 895                 drm_sg_mem_t *entry = dev->sg;
 896                 unsigned long tmp_ofs, page_ofs;
 897
 898                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 899                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 900
 901                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 902                              entry->busaddr[page_ofs]);
 903                 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 904                            entry->busaddr[page_ofs],
 905                            entry->handle + tmp_ofs );
 906         }
 907
 908         /* Initialize the scratch register pointer.  This will cause
 909          * the scratch register values to be written out to memory
 910          * whenever they are updated.
 911          *
 912          * We simply put this behind the ring read pointer, this works
 913          * with PCI GART as well as (whatever kind of) AGP GART
 914          */
 915         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
 916                                          + RADEON_SCRATCH_REG_OFFSET );
 917
 918         dev_priv->scratch = ((__volatile__ u32 *)
 919                              dev_priv->ring.head +
 920                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 921
 922         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 923
 924         /* Writeback doesn't seem to work everywhere, test it first */
 925         DRM_WRITE32( &dev_priv->scratch[1], 0 );
 926         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
 927
 928         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
 929                 if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef )
 930                         break;
 931                 DRM_UDELAY( 1 );
 932         }
 933
 934         if ( tmp < dev_priv->usec_timeout ) {
 935                 dev_priv->writeback_works = 1;
 936                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
 937         } else {
 938                 dev_priv->writeback_works = 0;
 939                 DRM_DEBUG( "writeback test failed\n" );
 940         }
 941
 942         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 943         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 944                       dev_priv->sarea_priv->last_frame );
 945
 946         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 947         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 948                       dev_priv->sarea_priv->last_dispatch );
 949
 950         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 951         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 952                       dev_priv->sarea_priv->last_clear );
 953
 954         /* Set ring buffer size */
 955 #ifdef __BIG_ENDIAN
 956         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 957 #else
 958         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 959 #endif
 960
 961         radeon_do_wait_for_idle( dev_priv );
 962
 963         /* Turn on bus mastering */
 964         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 965         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 966
 967         /* Sync everything up */
 968         RADEON_WRITE( RADEON_ISYNC_CNTL,
 969                       (RADEON_ISYNC_ANY2D_IDLE3D |
 970                        RADEON_ISYNC_ANY3D_IDLE2D |
 971                        RADEON_ISYNC_WAIT_IDLEGUI |
 972                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 973 }
 974
 975 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 976 {
 977         drm_radeon_private_t *dev_priv;
 978         u32 tmp;
 979         DRM_DEBUG( "\n" );
 980
 981         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
 982         if ( dev_priv == NULL )
 983                 return DRM_ERR(ENOMEM);
 984
 985         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
 986
 987         dev_priv->is_pci = init->is_pci;
 988
 989         if ( dev_priv->is_pci && !dev->sg ) {
 990                 DRM_ERROR( "PCI GART memory not allocated!\n" );
 991                 dev->dev_private = (void *)dev_priv;
 992                 radeon_do_cleanup_cp(dev);
 993                 return DRM_ERR(EINVAL);
 994         }
 995
 996         dev_priv->usec_timeout = init->usec_timeout;
 997         if ( dev_priv->usec_timeout < 1 ||
 998              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
 999                 DRM_DEBUG( "TIMEOUT problem!\n" );
1000                 dev->dev_private = (void *)dev_priv;
1001                 radeon_do_cleanup_cp(dev);
1002                 return DRM_ERR(EINVAL);
1003         }
1004
1005         dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1006         dev_priv->do_boxes = 0;
1007         dev_priv->cp_mode = init->cp_mode;
1008
1009         /* We don't support anything other than bus-mastering ring mode,
1010          * but the ring can be in either AGP or PCI space for the ring
1011          * read pointer.
1012          */
1013         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1014              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1015                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1016                 dev->dev_private = (void *)dev_priv;
1017                 radeon_do_cleanup_cp(dev);
1018                 return DRM_ERR(EINVAL);
1019         }
1020
1021         switch ( init->fb_bpp ) {
1022         case 16:
1023                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1024                 break;
1025         case 32:
1026         default:
1027                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1028                 break;
1029         }
1030         dev_priv->front_offset  = init->front_offset;
1031         dev_priv->front_pitch   = init->front_pitch;
1032         dev_priv->back_offset   = init->back_offset;
1033         dev_priv->back_pitch    = init->back_pitch;
1034
1035         switch ( init->depth_bpp ) {
1036         case 16:
1037                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1038                 break;
1039         case 32:
1040         default:
1041                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1042                 break;
1043         }
1044         dev_priv->depth_offset  = init->depth_offset;
1045         dev_priv->depth_pitch   = init->depth_pitch;
1046
1047         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1048                                         (dev_priv->front_offset >> 10));
1049         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1050                                        (dev_priv->back_offset >> 10));
1051         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1052                                         (dev_priv->depth_offset >> 10));
1053
1054         /* Hardware state for depth clears.  Remove this if/when we no
1055          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1056          * all values to prevent unwanted 3D state from slipping through
1057          * and screwing with the clear operation.
1058          */
1059         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1060                                            (dev_priv->color_fmt << 10) |
1061                                            (1<<15));
1062
1063         dev_priv->depth_clear.rb3d_zstencilcntl =
1064                 (dev_priv->depth_fmt |
1065                  RADEON_Z_TEST_ALWAYS |
1066                  RADEON_STENCIL_TEST_ALWAYS |
1067                  RADEON_STENCIL_S_FAIL_REPLACE |
1068                  RADEON_STENCIL_ZPASS_REPLACE |
1069                  RADEON_STENCIL_ZFAIL_REPLACE |
1070                  RADEON_Z_WRITE_ENABLE);
1071
1072         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1073                                          RADEON_BFACE_SOLID |
1074                                          RADEON_FFACE_SOLID |
1075                                          RADEON_FLAT_SHADE_VTX_LAST |
1076                                          RADEON_DIFFUSE_SHADE_FLAT |
1077                                          RADEON_ALPHA_SHADE_FLAT |
1078                                          RADEON_SPECULAR_SHADE_FLAT |
1079                                          RADEON_FOG_SHADE_FLAT |
1080                                          RADEON_VTX_PIX_CENTER_OGL |
1081                                          RADEON_ROUND_MODE_TRUNC |
1082                                          RADEON_ROUND_PREC_8TH_PIX);
1083
1084         DRM_GETSAREA();
1085
1086         if(!dev_priv->sarea) {
1087                 DRM_ERROR("could not find sarea!\n");
1088                 dev->dev_private = (void *)dev_priv;
1089                 radeon_do_cleanup_cp(dev);
1090                 return DRM_ERR(EINVAL);
1091         }
1092
1093         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1094         if(!dev_priv->fb) {
1095                 DRM_ERROR("could not find framebuffer!\n");
1096                 dev->dev_private = (void *)dev_priv;
1097                 radeon_do_cleanup_cp(dev);
1098                 return DRM_ERR(EINVAL);
1099         }
1100         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1101         if(!dev_priv->mmio) {
1102                 DRM_ERROR("could not find mmio region!\n");
1103                 dev->dev_private = (void *)dev_priv;
1104                 radeon_do_cleanup_cp(dev);
1105                 return DRM_ERR(EINVAL);
1106         }
1107         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1108         if(!dev_priv->cp_ring) {
1109                 DRM_ERROR("could not find cp ring region!\n");
1110                 dev->dev_private = (void *)dev_priv;
1111                 radeon_do_cleanup_cp(dev);
1112                 return DRM_ERR(EINVAL);
1113         }
1114         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1115         if(!dev_priv->ring_rptr) {
1116                 DRM_ERROR("could not find ring read pointer!\n");
1117                 dev->dev_private = (void *)dev_priv;
1118                 radeon_do_cleanup_cp(dev);
1119                 return DRM_ERR(EINVAL);
1120         }
1121         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1122         if(!dev_priv->buffers) {
1123                 DRM_ERROR("could not find dma buffer region!\n");
1124                 dev->dev_private = (void *)dev_priv;
1125                 radeon_do_cleanup_cp(dev);
1126                 return DRM_ERR(EINVAL);
1127         }
1128
1129         if ( !dev_priv->is_pci ) {
1130                 DRM_FIND_MAP( dev_priv->agp_textures,
1131                               init->agp_textures_offset );
1132                 if(!dev_priv->agp_textures) {
1133                         DRM_ERROR("could not find agp texture region!\n");
1134                         dev->dev_private = (void *)dev_priv;
1135                         radeon_do_cleanup_cp(dev);
1136                         return DRM_ERR(EINVAL);
1137                 }
1138         }
1139
1140         dev_priv->sarea_priv =
1141                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1142                                        init->sarea_priv_offset);
1143
1144         if ( !dev_priv->is_pci ) {
1145                 DRM_IOREMAP( dev_priv->cp_ring );
1146                 DRM_IOREMAP( dev_priv->ring_rptr );
1147                 DRM_IOREMAP( dev_priv->buffers );
1148                 if(!dev_priv->cp_ring->handle ||
1149                    !dev_priv->ring_rptr->handle ||
1150                    !dev_priv->buffers->handle) {
1151                         DRM_ERROR("could not find ioremap agp regions!\n");
1152                         dev->dev_private = (void *)dev_priv;
1153                         radeon_do_cleanup_cp(dev);
1154                         return DRM_ERR(EINVAL);
1155                 }
1156         } else {
1157                 dev_priv->cp_ring->handle =
1158                         (void *)dev_priv->cp_ring->offset;
1159                 dev_priv->ring_rptr->handle =
1160                         (void *)dev_priv->ring_rptr->offset;
1161                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1162
1163                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1164                            dev_priv->cp_ring->handle );
1165                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1166                            dev_priv->ring_rptr->handle );
1167                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1168                            dev_priv->buffers->handle );
1169         }
1170
1171
1172         dev_priv->agp_size = init->agp_size;
1173         dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1174 #if __REALLY_HAVE_AGP
1175         if ( !dev_priv->is_pci )
1176                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1177                                                 - dev->agp->base
1178                                                 + dev_priv->agp_vm_start);
1179         else
1180 #endif
1181                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1182                                                 - dev->sg->handle
1183                                                 + dev_priv->agp_vm_start);
1184
1185         DRM_DEBUG( "dev_priv->agp_size %d\n",
1186                    dev_priv->agp_size );
1187         DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1188                    dev_priv->agp_vm_start );
1189         DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1190                    dev_priv->agp_buffers_offset );
1191
1192         dev_priv->ring.head = ((__volatile__ u32 *)
1193                                dev_priv->ring_rptr->handle);
1194
1195         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1196         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1197                               + init->ring_size / sizeof(u32));
1198         dev_priv->ring.size = init->ring_size;
1199         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1200
1201         dev_priv->ring.tail_mask =
1202                 (dev_priv->ring.size / sizeof(u32)) - 1;
1203
1204         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1205
1206 #if __REALLY_HAVE_SG
1207         if ( dev_priv->is_pci ) {
1208                 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1209                                             &dev_priv->bus_pci_gart)) {
1210                         DRM_ERROR( "failed to init PCI GART!\n" );
1211                         dev->dev_private = (void *)dev_priv;
1212                         radeon_do_cleanup_cp(dev);
1213                         return DRM_ERR(ENOMEM);
1214                 }
1215                 /* Turn on PCI GART
1216                  */
1217                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1218                       | RADEON_PCIGART_TRANSLATE_EN;
1219                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1220
1221                 /* set PCI GART page-table base address
1222                  */
1223                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1224
1225                 /* set address range for PCI address translate
1226                  */
1227                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1228                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1229                                                   + dev_priv->agp_size - 1);
1230
1231                 /* Turn off AGP aperture -- is this required for PCIGART?
1232                  */
1233                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1234                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1235         } else {
1236 #endif /* __REALLY_HAVE_SG */
1237                 /* Turn off PCI GART
1238                  */
1239                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1240                       & ~RADEON_PCIGART_TRANSLATE_EN;
1241                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1242 #if __REALLY_HAVE_SG
1243         }
1244 #endif /* __REALLY_HAVE_SG */
1245
1246         radeon_cp_load_microcode( dev_priv );
1247         radeon_cp_init_ring_buffer( dev, dev_priv );
1248
1249         dev_priv->last_buf = 0;
1250
1251         dev->dev_private = (void *)dev_priv;
1252
1253         radeon_do_engine_reset( dev );
1254
1255         return 0;
1256 }
1257
1258 int radeon_do_cleanup_cp( drm_device_t *dev )
1259 {
1260         DRM_DEBUG( "\n" );
1261
1262         if ( dev->dev_private ) {
1263                 drm_radeon_private_t *dev_priv = dev->dev_private;
1264
1265                 if ( !dev_priv->is_pci ) {
1266                         DRM_IOREMAPFREE( dev_priv->cp_ring );
1267                         DRM_IOREMAPFREE( dev_priv->ring_rptr );
1268                         DRM_IOREMAPFREE( dev_priv->buffers );
1269                 } else {
1270 #if __REALLY_HAVE_SG
1271                         if (!DRM(ati_pcigart_cleanup)( dev,
1272                                                 dev_priv->phys_pci_gart,
1273                                                 dev_priv->bus_pci_gart ))
1274                                 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1275 #endif /* __REALLY_HAVE_SG */
1276                 }
1277
1278                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1279                            DRM_MEM_DRIVER );
1280                 dev->dev_private = NULL;
1281         }
1282
1283         return 0;
1284 }
1285
1286 int radeon_cp_init( DRM_IOCTL_ARGS )
1287 {
1288         DRM_DEVICE;
1289         drm_radeon_init_t init;
1290
1291         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1292
1293         switch ( init.func ) {
1294         case RADEON_INIT_CP:
1295         case RADEON_INIT_R200_CP:
1296                 return radeon_do_init_cp( dev, &init );
1297         case RADEON_CLEANUP_CP:
1298                 return radeon_do_cleanup_cp( dev );
1299         }
1300
1301         return DRM_ERR(EINVAL);
1302 }
1303
1304 int radeon_cp_start( DRM_IOCTL_ARGS )
1305 {
1306         DRM_DEVICE;
1307         drm_radeon_private_t *dev_priv = dev->dev_private;
1308         DRM_DEBUG( "\n" );
1309
1310         LOCK_TEST_WITH_RETURN( dev );
1311
1312         if ( dev_priv->cp_running ) {
1313                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1314                 return 0;
1315         }
1316         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1317                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1318                            __FUNCTION__, dev_priv->cp_mode );
1319                 return 0;
1320         }
1321
1322         radeon_do_cp_start( dev_priv );
1323
1324         return 0;
1325 }
1326
1327 /* Stop the CP.  The engine must have been idled before calling this
1328  * routine.
1329  */
1330 int radeon_cp_stop( DRM_IOCTL_ARGS )
1331 {
1332         DRM_DEVICE;
1333         drm_radeon_private_t *dev_priv = dev->dev_private;
1334         drm_radeon_cp_stop_t stop;
1335         int ret;
1336         DRM_DEBUG( "\n" );
1337
1338         LOCK_TEST_WITH_RETURN( dev );
1339
1340         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1341
1342         /* Flush any pending CP commands.  This ensures any outstanding
1343          * commands are exectuted by the engine before we turn it off.
1344          */
1345         if ( stop.flush ) {
1346                 radeon_do_cp_flush( dev_priv );
1347         }
1348
1349         /* If we fail to make the engine go idle, we return an error
1350          * code so that the DRM ioctl wrapper can try again.
1351          */
1352         if ( stop.idle ) {
1353                 ret = radeon_do_cp_idle( dev_priv );
1354                 if ( ret ) return ret;
1355         }
1356
1357         /* Finally, we can turn off the CP.  If the engine isn't idle,
1358          * we will get some dropped triangles as they won't be fully
1359          * rendered before the CP is shut down.
1360          */
1361         radeon_do_cp_stop( dev_priv );
1362
1363         /* Reset the engine */
1364         radeon_do_engine_reset( dev );
1365
1366         return 0;
1367 }
1368
1369 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1370  */
1371 int radeon_cp_reset( DRM_IOCTL_ARGS )
1372 {
1373         DRM_DEVICE;
1374         drm_radeon_private_t *dev_priv = dev->dev_private;
1375         DRM_DEBUG( "\n" );
1376
1377         LOCK_TEST_WITH_RETURN( dev );
1378
1379         if ( !dev_priv ) {
1380                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1381                 return DRM_ERR(EINVAL);
1382         }
1383
1384         radeon_do_cp_reset( dev_priv );
1385
1386         /* The CP is no longer running after an engine reset */
1387         dev_priv->cp_running = 0;
1388
1389         return 0;
1390 }
1391
1392 int radeon_cp_idle( DRM_IOCTL_ARGS )
1393 {
1394         DRM_DEVICE;
1395         drm_radeon_private_t *dev_priv = dev->dev_private;
1396         DRM_DEBUG( "\n" );
1397
1398         LOCK_TEST_WITH_RETURN( dev );
1399
1400 /*      if (dev->irq)  */
1401 /*              radeon_emit_and_wait_irq( dev ); */
1402
1403         return radeon_do_cp_idle( dev_priv );
1404 }
1405
1406 int radeon_engine_reset( DRM_IOCTL_ARGS )
1407 {
1408         DRM_DEVICE;
1409         DRM_DEBUG( "\n" );
1410
1411         LOCK_TEST_WITH_RETURN( dev );
1412
1413         return radeon_do_engine_reset( dev );
1414 }
1415
1416
1417 /* ================================================================
1418  * Fullscreen mode
1419  */
1420
1421 /* KW: Deprecated to say the least:
1422  */
1423 int radeon_fullscreen( DRM_IOCTL_ARGS )
1424 {
1425         return 0;
1426 }
1427
1428
1429 /* ================================================================
1430  * Freelist management
1431  */
1432
1433 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1434  *   bufs until freelist code is used.  Note this hides a problem with
1435  *   the scratch register * (used to keep track of last buffer
1436  *   completed) being written to before * the last buffer has actually
1437  *   completed rendering.
1438  *
1439  * KW:  It's also a good way to find free buffers quickly.
1440  *
1441  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1442  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1443  * we essentially have to do this, else old clients will break.
1444  *
1445  * However, it does leave open a potential deadlock where all the
1446  * buffers are held by other clients, which can't release them because
1447  * they can't get the lock.
1448  */
1449
1450 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1451 {
1452         drm_device_dma_t *dma = dev->dma;
1453         drm_radeon_private_t *dev_priv = dev->dev_private;
1454         drm_radeon_buf_priv_t *buf_priv;
1455         drm_buf_t *buf;
1456         int i, t;
1457         int start;
1458
1459         if ( ++dev_priv->last_buf >= dma->buf_count )
1460                 dev_priv->last_buf = 0;
1461
1462         start = dev_priv->last_buf;
1463
1464         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1465                 u32 done_age = GET_SCRATCH( 1 );
1466                 DRM_DEBUG("done_age = %d\n",done_age);
1467                 for ( i = start ; i < dma->buf_count ; i++ ) {
1468                         buf = dma->buflist[i];
1469                         buf_priv = buf->dev_private;
1470                         if ( buf->pid == 0 || (buf->pending &&
1471                                                buf_priv->age <= done_age) ) {
1472                                 dev_priv->stats.requested_bufs++;
1473                                 buf->pending = 0;
1474                                 return buf;
1475                         }
1476                         start = 0;
1477                 }
1478
1479                 if (t) {
1480                         DRM_UDELAY( 1 );
1481                         dev_priv->stats.freelist_loops++;
1482                 }
1483         }
1484
1485         DRM_DEBUG( "returning NULL!\n" );
1486         return NULL;
1487 }
1488 #if 0
1489 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1490 {
1491         drm_device_dma_t *dma = dev->dma;
1492         drm_radeon_private_t *dev_priv = dev->dev_private;
1493         drm_radeon_buf_priv_t *buf_priv;
1494         drm_buf_t *buf;
1495         int i, t;
1496         int start;
1497         u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
1498
1499         if ( ++dev_priv->last_buf >= dma->buf_count )
1500                 dev_priv->last_buf = 0;
1501
1502         start = dev_priv->last_buf;
1503         dev_priv->stats.freelist_loops++;
1504
1505         for ( t = 0 ; t < 2 ; t++ ) {
1506                 for ( i = start ; i < dma->buf_count ; i++ ) {
1507                         buf = dma->buflist[i];
1508                         buf_priv = buf->dev_private;
1509                         if ( buf->pid == 0 || (buf->pending &&
1510                                                buf_priv->age <= done_age) ) {
1511                                 dev_priv->stats.requested_bufs++;
1512                                 buf->pending = 0;
1513                                 return buf;
1514                         }
1515                 }
1516                 start = 0;
1517         }
1518
1519         return NULL;
1520 }
1521 #endif
1522
1523 void radeon_freelist_reset( drm_device_t *dev )
1524 {
1525         drm_device_dma_t *dma = dev->dma;
1526         drm_radeon_private_t *dev_priv = dev->dev_private;
1527         int i;
1528
1529         dev_priv->last_buf = 0;
1530         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1531                 drm_buf_t *buf = dma->buflist[i];
1532                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1533                 buf_priv->age = 0;
1534         }
1535 }
1536
1537
1538 /* ================================================================
1539  * CP command submission
1540  */
1541
1542 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1543 {
1544         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1545         int i;
1546         u32 last_head = GET_RING_HEAD(ring);
1547
1548         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1549                 u32 head = GET_RING_HEAD(ring);
1550
1551                 ring->space = (head - ring->tail) * sizeof(u32);
1552                 if ( ring->space <= 0 )
1553                         ring->space += ring->size;
1554                 if ( ring->space > n )
1555                         return 0;
1556
1557                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1558
1559                 if (head != last_head)
1560                         i = 0;
1561                 last_head = head;
1562
1563                 DRM_UDELAY( 1 );
1564         }
1565
1566         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1567 #if RADEON_FIFO_DEBUG
1568         radeon_status( dev_priv );
1569         DRM_ERROR( "failed!\n" );
1570 #endif
1571         return DRM_ERR(EBUSY);
1572 }
1573
1574 static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
1575 {
1576         int i;
1577         drm_buf_t *buf;
1578
1579         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1580                 buf = radeon_freelist_get( dev );
1581                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1582
1583                 buf->pid = DRM_CURRENTPID;
1584
1585                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1586                                    sizeof(buf->idx) ) )
1587                         return DRM_ERR(EFAULT);
1588                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1589                                    sizeof(buf->total) ) )
1590                         return DRM_ERR(EFAULT);
1591
1592                 d->granted_count++;
1593         }
1594         return 0;
1595 }
1596
1597 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1598 {
1599         DRM_DEVICE;
1600         drm_device_dma_t *dma = dev->dma;
1601         int ret = 0;
1602         drm_dma_t d;
1603
1604         LOCK_TEST_WITH_RETURN( dev );
1605
1606         DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1607
1608         /* Please don't send us buffers.
1609          */
1610         if ( d.send_count != 0 ) {
1611                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1612                            DRM_CURRENTPID, d.send_count );
1613                 return DRM_ERR(EINVAL);
1614         }
1615
1616         /* We'll send you buffers.
1617          */
1618         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1619                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1620                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1621                 return DRM_ERR(EINVAL);
1622         }
1623
1624         d.granted_count = 0;
1625
1626         if ( d.request_count ) {
1627                 ret = radeon_cp_get_buffers( dev, &d );
1628         }
1629
1630         DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1631
1632         return ret;
1633 }