shared/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "radeon.h"
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 #if defined(__alpha__) || defined(__powerpc__)
  40 # define PCIGART_ENABLED
  41 #else
  42 # undef PCIGART_ENABLED
  43 #endif
  44
  45
  46 /* CP microcode (from ATI) */
  47 static u32 radeon_cp_microcode[][2] = {
  48         { 0x21007000, 0000000000 },
  49         { 0x20007000, 0000000000 },
  50         { 0x000000b4, 0x00000004 },
  51         { 0x000000b8, 0x00000004 },
  52         { 0x6f5b4d4c, 0000000000 },
  53         { 0x4c4c427f, 0000000000 },
  54         { 0x5b568a92, 0000000000 },
  55         { 0x4ca09c6d, 0000000000 },
  56         { 0xad4c4c4c, 0000000000 },
  57         { 0x4ce1af3d, 0000000000 },
  58         { 0xd8afafaf, 0000000000 },
  59         { 0xd64c4cdc, 0000000000 },
  60         { 0x4cd10d10, 0000000000 },
  61         { 0x000f0000, 0x00000016 },
  62         { 0x362f242d, 0000000000 },
  63         { 0x00000012, 0x00000004 },
  64         { 0x000f0000, 0x00000016 },
  65         { 0x362f282d, 0000000000 },
  66         { 0x000380e7, 0x00000002 },
  67         { 0x04002c97, 0x00000002 },
  68         { 0x000f0001, 0x00000016 },
  69         { 0x333a3730, 0000000000 },
  70         { 0x000077ef, 0x00000002 },
  71         { 0x00061000, 0x00000002 },
  72         { 0x00000021, 0x0000001a },
  73         { 0x00004000, 0x0000001e },
  74         { 0x00061000, 0x00000002 },
  75         { 0x00000021, 0x0000001a },
  76         { 0x00004000, 0x0000001e },
  77         { 0x00061000, 0x00000002 },
  78         { 0x00000021, 0x0000001a },
  79         { 0x00004000, 0x0000001e },
  80         { 0x00000017, 0x00000004 },
  81         { 0x0003802b, 0x00000002 },
  82         { 0x040067e0, 0x00000002 },
  83         { 0x00000017, 0x00000004 },
  84         { 0x000077e0, 0x00000002 },
  85         { 0x00065000, 0x00000002 },
  86         { 0x000037e1, 0x00000002 },
  87         { 0x040067e1, 0x00000006 },
  88         { 0x000077e0, 0x00000002 },
  89         { 0x000077e1, 0x00000002 },
  90         { 0x000077e1, 0x00000006 },
  91         { 0xffffffff, 0000000000 },
  92         { 0x10000000, 0000000000 },
  93         { 0x0003802b, 0x00000002 },
  94         { 0x040067e0, 0x00000006 },
  95         { 0x00007675, 0x00000002 },
  96         { 0x00007676, 0x00000002 },
  97         { 0x00007677, 0x00000002 },
  98         { 0x00007678, 0x00000006 },
  99         { 0x0003802c, 0x00000002 },
 100         { 0x04002676, 0x00000002 },
 101         { 0x00007677, 0x00000002 },
 102         { 0x00007678, 0x00000006 },
 103         { 0x0000002f, 0x00000018 },
 104         { 0x0000002f, 0x00000018 },
 105         { 0000000000, 0x00000006 },
 106         { 0x00000030, 0x00000018 },
 107         { 0x00000030, 0x00000018 },
 108         { 0000000000, 0x00000006 },
 109         { 0x01605000, 0x00000002 },
 110         { 0x00065000, 0x00000002 },
 111         { 0x00098000, 0x00000002 },
 112         { 0x00061000, 0x00000002 },
 113         { 0x64c0603e, 0x00000004 },
 114         { 0x000380e6, 0x00000002 },
 115         { 0x040025c5, 0x00000002 },
 116         { 0x00080000, 0x00000016 },
 117         { 0000000000, 0000000000 },
 118         { 0x0400251d, 0x00000002 },
 119         { 0x00007580, 0x00000002 },
 120         { 0x00067581, 0x00000002 },
 121         { 0x04002580, 0x00000002 },
 122         { 0x00067581, 0x00000002 },
 123         { 0x00000049, 0x00000004 },
 124         { 0x00005000, 0000000000 },
 125         { 0x000380e6, 0x00000002 },
 126         { 0x040025c5, 0x00000002 },
 127         { 0x00061000, 0x00000002 },
 128         { 0x0000750e, 0x00000002 },
 129         { 0x00019000, 0x00000002 },
 130         { 0x00011055, 0x00000014 },
 131         { 0x00000055, 0x00000012 },
 132         { 0x0400250f, 0x00000002 },
 133         { 0x0000504f, 0x00000004 },
 134         { 0x000380e6, 0x00000002 },
 135         { 0x040025c5, 0x00000002 },
 136         { 0x00007565, 0x00000002 },
 137         { 0x00007566, 0x00000002 },
 138         { 0x00000058, 0x00000004 },
 139         { 0x000380e6, 0x00000002 },
 140         { 0x040025c5, 0x00000002 },
 141         { 0x01e655b4, 0x00000002 },
 142         { 0x4401b0e4, 0x00000002 },
 143         { 0x01c110e4, 0x00000002 },
 144         { 0x26667066, 0x00000018 },
 145         { 0x040c2565, 0x00000002 },
 146         { 0x00000066, 0x00000018 },
 147         { 0x04002564, 0x00000002 },
 148         { 0x00007566, 0x00000002 },
 149         { 0x0000005d, 0x00000004 },
 150         { 0x00401069, 0x00000008 },
 151         { 0x00101000, 0x00000002 },
 152         { 0x000d80ff, 0x00000002 },
 153         { 0x0080006c, 0x00000008 },
 154         { 0x000f9000, 0x00000002 },
 155         { 0x000e00ff, 0x00000002 },
 156         { 0000000000, 0x00000006 },
 157         { 0x0000008f, 0x00000018 },
 158         { 0x0000005b, 0x00000004 },
 159         { 0x000380e6, 0x00000002 },
 160         { 0x040025c5, 0x00000002 },
 161         { 0x00007576, 0x00000002 },
 162         { 0x00065000, 0x00000002 },
 163         { 0x00009000, 0x00000002 },
 164         { 0x00041000, 0x00000002 },
 165         { 0x0c00350e, 0x00000002 },
 166         { 0x00049000, 0x00000002 },
 167         { 0x00051000, 0x00000002 },
 168         { 0x01e785f8, 0x00000002 },
 169         { 0x00200000, 0x00000002 },
 170         { 0x0060007e, 0x0000000c },
 171         { 0x00007563, 0x00000002 },
 172         { 0x006075f0, 0x00000021 },
 173         { 0x20007073, 0x00000004 },
 174         { 0x00005073, 0x00000004 },
 175         { 0x000380e6, 0x00000002 },
 176         { 0x040025c5, 0x00000002 },
 177         { 0x00007576, 0x00000002 },
 178         { 0x00007577, 0x00000002 },
 179         { 0x0000750e, 0x00000002 },
 180         { 0x0000750f, 0x00000002 },
 181         { 0x00a05000, 0x00000002 },
 182         { 0x00600083, 0x0000000c },
 183         { 0x006075f0, 0x00000021 },
 184         { 0x000075f8, 0x00000002 },
 185         { 0x00000083, 0x00000004 },
 186         { 0x000a750e, 0x00000002 },
 187         { 0x000380e6, 0x00000002 },
 188         { 0x040025c5, 0x00000002 },
 189         { 0x0020750f, 0x00000002 },
 190         { 0x00600086, 0x00000004 },
 191         { 0x00007570, 0x00000002 },
 192         { 0x00007571, 0x00000002 },
 193         { 0x00007572, 0x00000006 },
 194         { 0x000380e6, 0x00000002 },
 195         { 0x040025c5, 0x00000002 },
 196         { 0x00005000, 0x00000002 },
 197         { 0x00a05000, 0x00000002 },
 198         { 0x00007568, 0x00000002 },
 199         { 0x00061000, 0x00000002 },
 200         { 0x00000095, 0x0000000c },
 201         { 0x00058000, 0x00000002 },
 202         { 0x0c607562, 0x00000002 },
 203         { 0x00000097, 0x00000004 },
 204         { 0x000380e6, 0x00000002 },
 205         { 0x040025c5, 0x00000002 },
 206         { 0x00600096, 0x00000004 },
 207         { 0x400070e5, 0000000000 },
 208         { 0x000380e6, 0x00000002 },
 209         { 0x040025c5, 0x00000002 },
 210         { 0x000380e5, 0x00000002 },
 211         { 0x000000a8, 0x0000001c },
 212         { 0x000650aa, 0x00000018 },
 213         { 0x040025bb, 0x00000002 },
 214         { 0x000610ab, 0x00000018 },
 215         { 0x040075bc, 0000000000 },
 216         { 0x000075bb, 0x00000002 },
 217         { 0x000075bc, 0000000000 },
 218         { 0x00090000, 0x00000006 },
 219         { 0x00090000, 0x00000002 },
 220         { 0x000d8002, 0x00000006 },
 221         { 0x00007832, 0x00000002 },
 222         { 0x00005000, 0x00000002 },
 223         { 0x000380e7, 0x00000002 },
 224         { 0x04002c97, 0x00000002 },
 225         { 0x00007820, 0x00000002 },
 226         { 0x00007821, 0x00000002 },
 227         { 0x00007800, 0000000000 },
 228         { 0x01200000, 0x00000002 },
 229         { 0x20077000, 0x00000002 },
 230         { 0x01200000, 0x00000002 },
 231         { 0x20007000, 0x00000002 },
 232         { 0x00061000, 0x00000002 },
 233         { 0x0120751b, 0x00000002 },
 234         { 0x8040750a, 0x00000002 },
 235         { 0x8040750b, 0x00000002 },
 236         { 0x00110000, 0x00000002 },
 237         { 0x000380e5, 0x00000002 },
 238         { 0x000000c6, 0x0000001c },
 239         { 0x000610ab, 0x00000018 },
 240         { 0x844075bd, 0x00000002 },
 241         { 0x000610aa, 0x00000018 },
 242         { 0x840075bb, 0x00000002 },
 243         { 0x000610ab, 0x00000018 },
 244         { 0x844075bc, 0x00000002 },
 245         { 0x000000c9, 0x00000004 },
 246         { 0x804075bd, 0x00000002 },
 247         { 0x800075bb, 0x00000002 },
 248         { 0x804075bc, 0x00000002 },
 249         { 0x00108000, 0x00000002 },
 250         { 0x01400000, 0x00000002 },
 251         { 0x006000cd, 0x0000000c },
 252         { 0x20c07000, 0x00000020 },
 253         { 0x000000cf, 0x00000012 },
 254         { 0x00800000, 0x00000006 },
 255         { 0x0080751d, 0x00000006 },
 256         { 0000000000, 0000000000 },
 257         { 0x0000775c, 0x00000002 },
 258         { 0x00a05000, 0x00000002 },
 259         { 0x00661000, 0x00000002 },
 260         { 0x0460275d, 0x00000020 },
 261         { 0x00004000, 0000000000 },
 262         { 0x01e00830, 0x00000002 },
 263         { 0x21007000, 0000000000 },
 264         { 0x6464614d, 0000000000 },
 265         { 0x69687420, 0000000000 },
 266         { 0x00000073, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0x00005000, 0x00000002 },
 269         { 0x000380d0, 0x00000002 },
 270         { 0x040025e0, 0x00000002 },
 271         { 0x000075e1, 0000000000 },
 272         { 0x00000001, 0000000000 },
 273         { 0x000380e0, 0x00000002 },
 274         { 0x04002394, 0x00000002 },
 275         { 0x00005000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0x00000008, 0000000000 },
 279         { 0x00000004, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299         { 0000000000, 0000000000 },
 300         { 0000000000, 0000000000 },
 301         { 0000000000, 0000000000 },
 302         { 0000000000, 0000000000 },
 303         { 0000000000, 0000000000 },
 304 };
 305
 306
 307 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 308 {
 309         drm_radeon_private_t *dev_priv = dev->dev_private;
 310
 311         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 312         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 313 }
 314
 315 #if RADEON_FIFO_DEBUG
 316 static void radeon_status( drm_radeon_private_t *dev_priv )
 317 {
 318         printk( "%s:\n", __FUNCTION__ );
 319         printk( "RBBM_STATUS = 0x%08x\n",
 320                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 321         printk( "CP_RB_RTPR = 0x%08x\n",
 322                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 323         printk( "CP_RB_WTPR = 0x%08x\n",
 324                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 325         printk( "AIC_CNTL = 0x%08x\n",
 326                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 327         printk( "AIC_STAT = 0x%08x\n",
 328                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 329         printk( "AIC_PT_BASE = 0x%08x\n",
 330                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 331         printk( "TLB_ADDR = 0x%08x\n",
 332                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 333         printk( "TLB_DATA = 0x%08x\n",
 334                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 335 }
 336 #endif
 337
 338
 339 /* ================================================================
 340  * Engine, FIFO control
 341  */
 342
 343 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 344 {
 345         u32 tmp;
 346         int i;
 347
 348         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 349         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 350         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 351
 352         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 353                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 354                        & RADEON_RB2D_DC_BUSY) ) {
 355                         return 0;
 356                 }
 357                 DRM_UDELAY( 1 );
 358         }
 359
 360 #if RADEON_FIFO_DEBUG
 361         DRM_ERROR( "failed!\n" );
 362         radeon_status( dev_priv );
 363 #endif
 364         return DRM_ERR(EBUSY);
 365 }
 366
 367 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 368                                     int entries )
 369 {
 370         int i;
 371
 372         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 373                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 374                               & RADEON_RBBM_FIFOCNT_MASK );
 375                 if ( slots >= entries ) return 0;
 376                 DRM_UDELAY( 1 );
 377         }
 378
 379 #if RADEON_FIFO_DEBUG
 380         DRM_ERROR( "failed!\n" );
 381         radeon_status( dev_priv );
 382 #endif
 383         return DRM_ERR(EBUSY);
 384 }
 385
 386 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 387 {
 388         int i, ret;
 389
 390         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 391         if ( ret ) return ret;
 392
 393         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 394                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 395                        & RADEON_RBBM_ACTIVE) ) {
 396                         radeon_do_pixcache_flush( dev_priv );
 397                         return 0;
 398                 }
 399                 DRM_UDELAY( 1 );
 400         }
 401
 402 #if RADEON_FIFO_DEBUG
 403         DRM_ERROR( "failed!\n" );
 404         radeon_status( dev_priv );
 405 #endif
 406         return DRM_ERR(EBUSY);
 407 }
 408
 409
 410 /* ================================================================
 411  * CP control, initialization
 412  */
 413
 414 /* Load the microcode for the CP */
 415 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 416 {
 417         int i;
 418         DRM_DEBUG( "\n" );
 419
 420         radeon_do_wait_for_idle( dev_priv );
 421
 422         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 423         for ( i = 0 ; i < 256 ; i++ ) {
 424                 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 425                               radeon_cp_microcode[i][1] );
 426                 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 427                               radeon_cp_microcode[i][0] );
 428         }
 429 }
 430
 431 /* Flush any pending commands to the CP.  This should only be used just
 432  * prior to a wait for idle, as it informs the engine that the command
 433  * stream is ending.
 434  */
 435 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 436 {
 437         DRM_DEBUG( "\n" );
 438 #if 0
 439         u32 tmp;
 440
 441         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 442         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 443 #endif
 444 }
 445
 446 /* Wait for the CP to go idle.
 447  */
 448 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 449 {
 450         RING_LOCALS;
 451         DRM_DEBUG( "\n" );
 452
 453         BEGIN_RING( 6 );
 454
 455         RADEON_PURGE_CACHE();
 456         RADEON_PURGE_ZCACHE();
 457         RADEON_WAIT_UNTIL_IDLE();
 458
 459         ADVANCE_RING();
 460         COMMIT_RING();
 461
 462         return radeon_do_wait_for_idle( dev_priv );
 463 }
 464
 465 /* Start the Command Processor.
 466  */
 467 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 468 {
 469         RING_LOCALS;
 470         DRM_DEBUG( "\n" );
 471
 472         radeon_do_wait_for_idle( dev_priv );
 473
 474         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 475
 476         dev_priv->cp_running = 1;
 477
 478         BEGIN_RING( 6 );
 479
 480         RADEON_PURGE_CACHE();
 481         RADEON_PURGE_ZCACHE();
 482         RADEON_WAIT_UNTIL_IDLE();
 483
 484         ADVANCE_RING();
 485         COMMIT_RING();
 486 }
 487
 488 /* Reset the Command Processor.  This will not flush any pending
 489  * commands, so you must wait for the CP command stream to complete
 490  * before calling this routine.
 491  */
 492 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 493 {
 494         u32 cur_read_ptr;
 495         DRM_DEBUG( "\n" );
 496
 497         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 498         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 499         *dev_priv->ring.head = cur_read_ptr;
 500         dev_priv->ring.tail = cur_read_ptr;
 501 }
 502
 503 /* Stop the Command Processor.  This will not flush any pending
 504  * commands, so you must flush the command stream and wait for the CP
 505  * to go idle before calling this routine.
 506  */
 507 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 508 {
 509         DRM_DEBUG( "\n" );
 510
 511         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 512
 513         dev_priv->cp_running = 0;
 514 }
 515
 516 /* Reset the engine.  This will stop the CP if it is running.
 517  */
 518 static int radeon_do_engine_reset( drm_device_t *dev )
 519 {
 520         drm_radeon_private_t *dev_priv = dev->dev_private;
 521         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 522         DRM_DEBUG( "\n" );
 523
 524         radeon_do_pixcache_flush( dev_priv );
 525
 526         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 527         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 528
 529         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 530                                               RADEON_FORCEON_MCLKA |
 531                                               RADEON_FORCEON_MCLKB |
 532                                               RADEON_FORCEON_YCLKA |
 533                                               RADEON_FORCEON_YCLKB |
 534                                               RADEON_FORCEON_MC |
 535                                               RADEON_FORCEON_AIC ) );
 536
 537         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 538
 539         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 540                                                 RADEON_SOFT_RESET_CP |
 541                                                 RADEON_SOFT_RESET_HI |
 542                                                 RADEON_SOFT_RESET_SE |
 543                                                 RADEON_SOFT_RESET_RE |
 544                                                 RADEON_SOFT_RESET_PP |
 545                                                 RADEON_SOFT_RESET_E2 |
 546                                                 RADEON_SOFT_RESET_RB ) );
 547         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 548         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 549                                                 ~( RADEON_SOFT_RESET_CP |
 550                                                    RADEON_SOFT_RESET_HI |
 551                                                    RADEON_SOFT_RESET_SE |
 552                                                    RADEON_SOFT_RESET_RE |
 553                                                    RADEON_SOFT_RESET_PP |
 554                                                    RADEON_SOFT_RESET_E2 |
 555                                                    RADEON_SOFT_RESET_RB ) ) );
 556         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 557
 558
 559         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 560         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 561         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 562
 563         /* Reset the CP ring */
 564         radeon_do_cp_reset( dev_priv );
 565
 566         /* The CP is no longer running after an engine reset */
 567         dev_priv->cp_running = 0;
 568
 569         /* Reset any pending vertex, indirect buffers */
 570         radeon_freelist_reset( dev );
 571
 572         return 0;
 573 }
 574
 575 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 576                                         drm_radeon_private_t *dev_priv )
 577 {
 578         u32 ring_start, cur_read_ptr;
 579         u32 tmp;
 580
 581         /* Initialize the memory controller */
 582         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 583                       (dev_priv->agp_vm_start - 1) & 0xffff0000 );
 584
 585         if ( !dev_priv->is_pci ) {
 586                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 587                               (((dev_priv->agp_vm_start - 1 +
 588                                  dev_priv->agp_size) & 0xffff0000) |
 589                                (dev_priv->agp_vm_start >> 16)) );
 590         }
 591
 592 #if __REALLY_HAVE_AGP
 593         if ( !dev_priv->is_pci )
 594                 ring_start = (dev_priv->cp_ring->offset
 595                               - dev->agp->base
 596                               + dev_priv->agp_vm_start);
 597        else
 598 #endif
 599                 ring_start = (dev_priv->cp_ring->offset
 600                               - dev->sg->handle
 601                               + dev_priv->agp_vm_start);
 602
 603         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 604
 605         /* Set the write pointer delay */
 606         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 607
 608         /* Initialize the ring buffer's read and write pointers */
 609         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 610         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 611         *dev_priv->ring.head = cur_read_ptr;
 612         dev_priv->ring.tail = cur_read_ptr;
 613
 614         if ( !dev_priv->is_pci ) {
 615                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 616                               dev_priv->ring_rptr->offset );
 617         } else {
 618                 drm_sg_mem_t *entry = dev->sg;
 619                 unsigned long tmp_ofs, page_ofs;
 620
 621                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 622                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 623
 624                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 625                              entry->busaddr[page_ofs]);
 626                 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 627                            entry->busaddr[page_ofs],
 628                            entry->handle + tmp_ofs );
 629         }
 630
 631         /* Set ring buffer size */
 632 #ifdef __BIG_ENDIAN
 633         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 634 #else
 635         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 636 #endif
 637
 638         radeon_do_wait_for_idle( dev_priv );
 639
 640         /* Turn on bus mastering */
 641         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 642         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 643
 644         /* Sync everything up */
 645         RADEON_WRITE( RADEON_ISYNC_CNTL,
 646                       (RADEON_ISYNC_ANY2D_IDLE3D |
 647                        RADEON_ISYNC_ANY3D_IDLE2D |
 648                        RADEON_ISYNC_WAIT_IDLEGUI |
 649                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 650 }
 651
 652 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 653 {
 654         drm_radeon_private_t *dev_priv;
 655         u32 tmp;
 656         DRM_DEBUG( "\n" );
 657
 658         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
 659         if ( dev_priv == NULL )
 660                 return DRM_ERR(ENOMEM);
 661
 662         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
 663
 664         dev_priv->is_pci = init->is_pci;
 665
 666 #if !defined(PCIGART_ENABLED)
 667         /* PCI support is not 100% working, so we disable it here.
 668          */
 669         if ( dev_priv->is_pci ) {
 670                 DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
 671                 dev->dev_private = (void *)dev_priv;
 672                 radeon_do_cleanup_cp(dev);
 673                 return DRM_ERR(EINVAL);
 674         }
 675 #endif
 676
 677         if ( dev_priv->is_pci && !dev->sg ) {
 678                 DRM_ERROR( "PCI GART memory not allocated!\n" );
 679                 dev->dev_private = (void *)dev_priv;
 680                 radeon_do_cleanup_cp(dev);
 681                 return DRM_ERR(EINVAL);
 682         }
 683
 684         dev_priv->usec_timeout = init->usec_timeout;
 685         if ( dev_priv->usec_timeout < 1 ||
 686              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
 687                 DRM_DEBUG( "TIMEOUT problem!\n" );
 688                 dev->dev_private = (void *)dev_priv;
 689                 radeon_do_cleanup_cp(dev);
 690                 return DRM_ERR(EINVAL);
 691         }
 692
 693         dev_priv->cp_mode = init->cp_mode;
 694
 695         /* Simple idle check.
 696          */
 697         atomic_set( &dev_priv->idle_count, 0 );
 698
 699         /* We don't support anything other than bus-mastering ring mode,
 700          * but the ring can be in either AGP or PCI space for the ring
 701          * read pointer.
 702          */
 703         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
 704              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
 705                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
 706                 dev->dev_private = (void *)dev_priv;
 707                 radeon_do_cleanup_cp(dev);
 708                 return DRM_ERR(EINVAL);
 709         }
 710
 711         switch ( init->fb_bpp ) {
 712         case 16:
 713                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 714                 break;
 715         case 32:
 716         default:
 717                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 718                 break;
 719         }
 720         dev_priv->front_offset  = init->front_offset;
 721         dev_priv->front_pitch   = init->front_pitch;
 722         dev_priv->back_offset   = init->back_offset;
 723         dev_priv->back_pitch    = init->back_pitch;
 724
 725         switch ( init->depth_bpp ) {
 726         case 16:
 727                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 728                 break;
 729         case 32:
 730         default:
 731                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 732                 break;
 733         }
 734         dev_priv->depth_offset  = init->depth_offset;
 735         dev_priv->depth_pitch   = init->depth_pitch;
 736
 737         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
 738                                         (dev_priv->front_offset >> 10));
 739         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
 740                                        (dev_priv->back_offset >> 10));
 741         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
 742                                         (dev_priv->depth_offset >> 10));
 743
 744         /* Hardware state for depth clears.  Remove this if/when we no
 745          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 746          * all values to prevent unwanted 3D state from slipping through
 747          * and screwing with the clear operation.
 748          */
 749         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 750                                            (dev_priv->color_fmt << 10) |
 751                                            (1<<15));
 752
 753         dev_priv->depth_clear.rb3d_zstencilcntl =
 754                 (dev_priv->depth_fmt |
 755                  RADEON_Z_TEST_ALWAYS |
 756                  RADEON_STENCIL_TEST_ALWAYS |
 757                  RADEON_STENCIL_S_FAIL_REPLACE |
 758                  RADEON_STENCIL_ZPASS_REPLACE |
 759                  RADEON_STENCIL_ZFAIL_REPLACE |
 760                  RADEON_Z_WRITE_ENABLE);
 761
 762         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 763                                          RADEON_BFACE_SOLID |
 764                                          RADEON_FFACE_SOLID |
 765                                          RADEON_FLAT_SHADE_VTX_LAST |
 766                                          RADEON_DIFFUSE_SHADE_FLAT |
 767                                          RADEON_ALPHA_SHADE_FLAT |
 768                                          RADEON_SPECULAR_SHADE_FLAT |
 769                                          RADEON_FOG_SHADE_FLAT |
 770                                          RADEON_VTX_PIX_CENTER_OGL |
 771                                          RADEON_ROUND_MODE_TRUNC |
 772                                          RADEON_ROUND_PREC_8TH_PIX);
 773
 774         DRM_GETSAREA();
 775
 776         if(!dev_priv->sarea) {
 777                 DRM_ERROR("could not find sarea!\n");
 778                 dev->dev_private = (void *)dev_priv;
 779                 radeon_do_cleanup_cp(dev);
 780                 return DRM_ERR(EINVAL);
 781         }
 782
 783         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
 784         if(!dev_priv->fb) {
 785                 DRM_ERROR("could not find framebuffer!\n");
 786                 dev->dev_private = (void *)dev_priv;
 787                 radeon_do_cleanup_cp(dev);
 788                 return DRM_ERR(EINVAL);
 789         }
 790         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
 791         if(!dev_priv->mmio) {
 792                 DRM_ERROR("could not find mmio region!\n");
 793                 dev->dev_private = (void *)dev_priv;
 794                 radeon_do_cleanup_cp(dev);
 795                 return DRM_ERR(EINVAL);
 796         }
 797         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
 798         if(!dev_priv->cp_ring) {
 799                 DRM_ERROR("could not find cp ring region!\n");
 800                 dev->dev_private = (void *)dev_priv;
 801                 radeon_do_cleanup_cp(dev);
 802                 return DRM_ERR(EINVAL);
 803         }
 804         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
 805         if(!dev_priv->ring_rptr) {
 806                 DRM_ERROR("could not find ring read pointer!\n");
 807                 dev->dev_private = (void *)dev_priv;
 808                 radeon_do_cleanup_cp(dev);
 809                 return DRM_ERR(EINVAL);
 810         }
 811         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
 812         if(!dev_priv->buffers) {
 813                 DRM_ERROR("could not find dma buffer region!\n");
 814                 dev->dev_private = (void *)dev_priv;
 815                 radeon_do_cleanup_cp(dev);
 816                 return DRM_ERR(EINVAL);
 817         }
 818
 819         if ( !dev_priv->is_pci ) {
 820                 DRM_FIND_MAP( dev_priv->agp_textures,
 821                               init->agp_textures_offset );
 822                 if(!dev_priv->agp_textures) {
 823                         DRM_ERROR("could not find agp texture region!\n");
 824                         dev->dev_private = (void *)dev_priv;
 825                         radeon_do_cleanup_cp(dev);
 826                         return DRM_ERR(EINVAL);
 827                 }
 828         }
 829
 830         dev_priv->sarea_priv =
 831                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
 832                                        init->sarea_priv_offset);
 833
 834         if ( !dev_priv->is_pci ) {
 835                 DRM_IOREMAP( dev_priv->cp_ring );
 836                 DRM_IOREMAP( dev_priv->ring_rptr );
 837                 DRM_IOREMAP( dev_priv->buffers );
 838                 if(!dev_priv->cp_ring->handle ||
 839                    !dev_priv->ring_rptr->handle ||
 840                    !dev_priv->buffers->handle) {
 841                         DRM_ERROR("could not find ioremap agp regions!\n");
 842                         dev->dev_private = (void *)dev_priv;
 843                         radeon_do_cleanup_cp(dev);
 844                         return DRM_ERR(EINVAL);
 845                 }
 846         } else {
 847                 dev_priv->cp_ring->handle =
 848                         (void *)dev_priv->cp_ring->offset;
 849                 dev_priv->ring_rptr->handle =
 850                         (void *)dev_priv->ring_rptr->offset;
 851                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
 852
 853                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
 854                            dev_priv->cp_ring->handle );
 855                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
 856                            dev_priv->ring_rptr->handle );
 857                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
 858                            dev_priv->buffers->handle );
 859         }
 860
 861
 862         dev_priv->agp_size = init->agp_size;
 863         dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
 864 #if __REALLY_HAVE_AGP
 865         if ( !dev_priv->is_pci )
 866                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
 867                                                 - dev->agp->base
 868                                                 + dev_priv->agp_vm_start);
 869         else
 870 #endif
 871                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
 872                                                 - dev->sg->handle
 873                                                 + dev_priv->agp_vm_start);
 874
 875         DRM_DEBUG( "dev_priv->agp_size %d\n",
 876                    dev_priv->agp_size );
 877         DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
 878                    dev_priv->agp_vm_start );
 879         DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
 880                    dev_priv->agp_buffers_offset );
 881
 882         dev_priv->ring.head = ((__volatile__ u32 *)
 883                                dev_priv->ring_rptr->handle);
 884
 885         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
 886         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
 887                               + init->ring_size / sizeof(u32));
 888         dev_priv->ring.size = init->ring_size;
 889         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
 890
 891         dev_priv->ring.tail_mask =
 892                 (dev_priv->ring.size / sizeof(u32)) - 1;
 893
 894         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
 895
 896 #if 0
 897         /* Initialize the scratch register pointer.  This will cause
 898          * the scratch register values to be written out to memory
 899          * whenever they are updated.
 900          * FIXME: This doesn't quite work yet, so we're disabling it
 901          * for the release.
 902          */
 903         RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
 904                                             RADEON_SCRATCH_REG_OFFSET) );
 905         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 906 #endif
 907
 908         dev_priv->scratch = ((__volatile__ u32 *)
 909                              dev_priv->ring_rptr->handle +
 910                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 911
 912         dev_priv->sarea_priv->last_frame = 0;
 913         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 914                       dev_priv->sarea_priv->last_frame );
 915
 916         dev_priv->sarea_priv->last_dispatch = 0;
 917         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 918                       dev_priv->sarea_priv->last_dispatch );
 919
 920         dev_priv->sarea_priv->last_clear = 0;
 921         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 922                       dev_priv->sarea_priv->last_clear );
 923
 924 #if __REALLY_HAVE_SG
 925         if ( dev_priv->is_pci ) {
 926                 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
 927                                             &dev_priv->bus_pci_gart)) {
 928                         DRM_ERROR( "failed to init PCI GART!\n" );
 929                         dev->dev_private = (void *)dev_priv;
 930                         radeon_do_cleanup_cp(dev);
 931                         return DRM_ERR(ENOMEM);
 932                 }
 933                 /* Turn on PCI GART
 934                  */
 935                 tmp = RADEON_READ( RADEON_AIC_CNTL )
 936                       | RADEON_PCIGART_TRANSLATE_EN;
 937                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
 938
 939                 /* set PCI GART page-table base address
 940                  */
 941                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
 942
 943                 /* set address range for PCI address translate
 944                  */
 945                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
 946                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
 947                                                   + dev_priv->agp_size - 1);
 948
 949                 /* Turn off AGP aperture -- is this required for PCIGART?
 950                  */
 951                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
 952                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
 953         } else {
 954 #endif /* __REALLY_HAVE_SG */
 955                 /* Turn off PCI GART
 956                  */
 957                 tmp = RADEON_READ( RADEON_AIC_CNTL )
 958                       & ~RADEON_PCIGART_TRANSLATE_EN;
 959                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
 960 #if __REALLY_HAVE_SG
 961         }
 962 #endif /* __REALLY_HAVE_SG */
 963
 964         radeon_cp_load_microcode( dev_priv );
 965         radeon_cp_init_ring_buffer( dev, dev_priv );
 966
 967         dev_priv->last_buf = 0;
 968
 969         dev->dev_private = (void *)dev_priv;
 970
 971         radeon_do_engine_reset( dev );
 972
 973         return 0;
 974 }
 975
 976 int radeon_do_cleanup_cp( drm_device_t *dev )
 977 {
 978         DRM_DEBUG( "\n" );
 979
 980         if ( dev->dev_private ) {
 981                 drm_radeon_private_t *dev_priv = dev->dev_private;
 982
 983                 if ( !dev_priv->is_pci ) {
 984                         DRM_IOREMAPFREE( dev_priv->cp_ring );
 985                         DRM_IOREMAPFREE( dev_priv->ring_rptr );
 986                         DRM_IOREMAPFREE( dev_priv->buffers );
 987                 } else {
 988 #if __REALLY_HAVE_SG
 989                         if (!DRM(ati_pcigart_cleanup)( dev,
 990                                                 dev_priv->phys_pci_gart,
 991                                                 dev_priv->bus_pci_gart ))
 992                                 DRM_ERROR( "failed to cleanup PCI GART!\n" );
 993 #endif /* __REALLY_HAVE_SG */
 994                 }
 995
 996                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
 997                            DRM_MEM_DRIVER );
 998                 dev->dev_private = NULL;
 999         }
1000
1001         return 0;
1002 }
1003
1004 int radeon_cp_init( DRM_IOCTL_ARGS )
1005 {
1006         DRM_DEVICE;
1007         drm_radeon_init_t init;
1008
1009         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1010
1011         switch ( init.func ) {
1012         case RADEON_INIT_CP:
1013                 return radeon_do_init_cp( dev, &init );
1014         case RADEON_CLEANUP_CP:
1015                 return radeon_do_cleanup_cp( dev );
1016         }
1017
1018         return DRM_ERR(EINVAL);
1019 }
1020
1021 int radeon_cp_start( DRM_IOCTL_ARGS )
1022 {
1023         DRM_DEVICE;
1024         drm_radeon_private_t *dev_priv = dev->dev_private;
1025         DRM_DEBUG( "\n" );
1026
1027         LOCK_TEST_WITH_RETURN( dev );
1028
1029         if ( dev_priv->cp_running ) {
1030                 DRM_DEBUG( "%s while CP running\n", __func__ );
1031                 return 0;
1032         }
1033         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1034                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1035                            __func__, dev_priv->cp_mode );
1036                 return 0;
1037         }
1038
1039         radeon_do_cp_start( dev_priv );
1040
1041         return 0;
1042 }
1043
1044 /* Stop the CP.  The engine must have been idled before calling this
1045  * routine.
1046  */
1047 int radeon_cp_stop( DRM_IOCTL_ARGS )
1048 {
1049         DRM_DEVICE;
1050         drm_radeon_private_t *dev_priv = dev->dev_private;
1051         drm_radeon_cp_stop_t stop;
1052         int ret;
1053         DRM_DEBUG( "\n" );
1054
1055         LOCK_TEST_WITH_RETURN( dev );
1056
1057         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1058
1059         /* Flush any pending CP commands.  This ensures any outstanding
1060          * commands are exectuted by the engine before we turn it off.
1061          */
1062         if ( stop.flush ) {
1063                 radeon_do_cp_flush( dev_priv );
1064         }
1065
1066         /* If we fail to make the engine go idle, we return an error
1067          * code so that the DRM ioctl wrapper can try again.
1068          */
1069         if ( stop.idle ) {
1070                 ret = radeon_do_cp_idle( dev_priv );
1071                 if ( ret ) return ret;
1072         }
1073
1074         /* Finally, we can turn off the CP.  If the engine isn't idle,
1075          * we will get some dropped triangles as they won't be fully
1076          * rendered before the CP is shut down.
1077          */
1078         radeon_do_cp_stop( dev_priv );
1079
1080         /* Reset the engine */
1081         radeon_do_engine_reset( dev );
1082
1083         return 0;
1084 }
1085
1086 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1087  */
1088 int radeon_cp_reset( DRM_IOCTL_ARGS )
1089 {
1090         DRM_DEVICE;
1091         drm_radeon_private_t *dev_priv = dev->dev_private;
1092         DRM_DEBUG( "\n" );
1093
1094         LOCK_TEST_WITH_RETURN( dev );
1095
1096         if ( !dev_priv ) {
1097                 DRM_DEBUG( "%s called before init done\n", __func__ );
1098                 return DRM_ERR(EINVAL);
1099         }
1100
1101         radeon_do_cp_reset( dev_priv );
1102
1103         /* The CP is no longer running after an engine reset */
1104         dev_priv->cp_running = 0;
1105
1106         return 0;
1107 }
1108
1109 int radeon_cp_idle( DRM_IOCTL_ARGS )
1110 {
1111         DRM_DEVICE;
1112         drm_radeon_private_t *dev_priv = dev->dev_private;
1113         DRM_DEBUG( "\n" );
1114
1115         LOCK_TEST_WITH_RETURN( dev );
1116
1117         return radeon_do_cp_idle( dev_priv );
1118 }
1119
1120 int radeon_engine_reset( DRM_IOCTL_ARGS )
1121 {
1122         DRM_DEVICE;
1123         DRM_DEBUG( "\n" );
1124
1125         LOCK_TEST_WITH_RETURN( dev );
1126
1127         return radeon_do_engine_reset( dev );
1128 }
1129
1130
1131 /* ================================================================
1132  * Fullscreen mode
1133  */
1134
1135 /* KW: Deprecated to say the least:
1136  */
1137 int radeon_fullscreen( DRM_IOCTL_ARGS )
1138 {
1139         return 0;
1140 }
1141
1142
1143 /* ================================================================
1144  * Freelist management
1145  */
1146
1147 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1148  *   bufs until freelist code is used.  Note this hides a problem with
1149  *   the scratch register * (used to keep track of last buffer
1150  *   completed) being written to before * the last buffer has actually
1151  *   completed rendering.
1152  *
1153  * KW:  It's also a good way to find free buffers quickly.
1154  */
1155
1156 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1157 {
1158         drm_device_dma_t *dma = dev->dma;
1159         drm_radeon_private_t *dev_priv = dev->dev_private;
1160         drm_radeon_buf_priv_t *buf_priv;
1161         drm_buf_t *buf;
1162         int i, t;
1163         int start;
1164
1165         if ( ++dev_priv->last_buf >= dma->buf_count )
1166                 dev_priv->last_buf = 0;
1167
1168         start = dev_priv->last_buf;
1169
1170         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1171                 u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
1172                 for ( i = start ; i < dma->buf_count ; i++ ) {
1173                         buf = dma->buflist[i];
1174                         buf_priv = buf->dev_private;
1175                         if ( buf->pid == 0 || (buf->pending &&
1176                                                buf_priv->age <= done_age) ) {
1177                                 buf->pending = 0;
1178                                 return buf;
1179                         }
1180                         start = 0;
1181                 }
1182                 DRM_UDELAY( 1 );
1183         }
1184
1185         DRM_ERROR( "returning NULL!\n" );
1186         return NULL;
1187 }
1188
1189 void radeon_freelist_reset( drm_device_t *dev )
1190 {
1191         drm_device_dma_t *dma = dev->dma;
1192         drm_radeon_private_t *dev_priv = dev->dev_private;
1193         int i;
1194
1195         dev_priv->last_buf = 0;
1196         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1197                 drm_buf_t *buf = dma->buflist[i];
1198                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1199                 buf_priv->age = 0;
1200         }
1201 }
1202
1203
1204 /* ================================================================
1205  * CP command submission
1206  */
1207
1208 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1209 {
1210         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1211         int i;
1212
1213         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1214                 radeon_update_ring_snapshot( ring );
1215                 if ( ring->space > n )
1216                         return 0;
1217                 DRM_UDELAY( 1 );
1218         }
1219
1220         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1221 #if RADEON_FIFO_DEBUG
1222         radeon_status( dev_priv );
1223         DRM_ERROR( "failed!\n" );
1224 #endif
1225         return DRM_ERR(EBUSY);
1226 }
1227
1228 static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
1229 {
1230         int i;
1231         drm_buf_t *buf;
1232
1233         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1234                 buf = radeon_freelist_get( dev );
1235                 if ( !buf ) return DRM_ERR(EAGAIN);
1236
1237                 buf->pid = DRM_CURRENTPID;
1238
1239                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1240                                    sizeof(buf->idx) ) )
1241                         return DRM_ERR(EFAULT);
1242                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1243                                    sizeof(buf->total) ) )
1244                         return DRM_ERR(EFAULT);
1245
1246                 d->granted_count++;
1247         }
1248         return 0;
1249 }
1250
1251 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1252 {
1253         DRM_DEVICE;
1254         drm_device_dma_t *dma = dev->dma;
1255         int ret = 0;
1256         drm_dma_t d;
1257
1258         LOCK_TEST_WITH_RETURN( dev );
1259
1260         DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1261
1262         /* Please don't send us buffers.
1263          */
1264         if ( d.send_count != 0 ) {
1265                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1266                            DRM_CURRENTPID, d.send_count );
1267                 return DRM_ERR(EINVAL);
1268         }
1269
1270         /* We'll send you buffers.
1271          */
1272         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1273                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1274                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1275                 return DRM_ERR(EINVAL);
1276         }
1277
1278         d.granted_count = 0;
1279
1280         if ( d.request_count ) {
1281                 ret = radeon_cp_get_buffers( dev, &d );
1282         }
1283
1284         DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1285
1286         return ret;
1287 }