1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
37 #define RADEON_FIFO_DEBUG 0
39 #if defined(__alpha__) || defined(__powerpc__)
40 # define PCIGART_ENABLED
42 # undef PCIGART_ENABLED
46 /* CP microcode (from ATI) */
47 static u32 R200_cp_microcode[][2] = {
48 { 0x21007000, 0000000000 },
49 { 0x20007000, 0000000000 },
50 { 0x000000ab, 0x00000004 },
51 { 0x000000af, 0x00000004 },
52 { 0x66544a49, 0000000000 },
53 { 0x49494174, 0000000000 },
54 { 0x54517d83, 0000000000 },
55 { 0x498d8b64, 0000000000 },
56 { 0x49494949, 0000000000 },
57 { 0x49da493c, 0000000000 },
58 { 0x49989898, 0000000000 },
59 { 0xd34949d5, 0000000000 },
60 { 0x9dc90e11, 0000000000 },
61 { 0xce9b9b9b, 0000000000 },
62 { 0x000f0000, 0x00000016 },
63 { 0x352e232c, 0000000000 },
64 { 0x00000013, 0x00000004 },
65 { 0x000f0000, 0x00000016 },
66 { 0x352e272c, 0000000000 },
67 { 0x000f0001, 0x00000016 },
68 { 0x3239362f, 0000000000 },
69 { 0x000077ef, 0x00000002 },
70 { 0x00061000, 0x00000002 },
71 { 0x00000020, 0x0000001a },
72 { 0x00004000, 0x0000001e },
73 { 0x00061000, 0x00000002 },
74 { 0x00000020, 0x0000001a },
75 { 0x00004000, 0x0000001e },
76 { 0x00061000, 0x00000002 },
77 { 0x00000020, 0x0000001a },
78 { 0x00004000, 0x0000001e },
79 { 0x00000016, 0x00000004 },
80 { 0x0003802a, 0x00000002 },
81 { 0x040067e0, 0x00000002 },
82 { 0x00000016, 0x00000004 },
83 { 0x000077e0, 0x00000002 },
84 { 0x00065000, 0x00000002 },
85 { 0x000037e1, 0x00000002 },
86 { 0x040067e1, 0x00000006 },
87 { 0x000077e0, 0x00000002 },
88 { 0x000077e1, 0x00000002 },
89 { 0x000077e1, 0x00000006 },
90 { 0xffffffff, 0000000000 },
91 { 0x10000000, 0000000000 },
92 { 0x0003802a, 0x00000002 },
93 { 0x040067e0, 0x00000006 },
94 { 0x00007675, 0x00000002 },
95 { 0x00007676, 0x00000002 },
96 { 0x00007677, 0x00000002 },
97 { 0x00007678, 0x00000006 },
98 { 0x0003802b, 0x00000002 },
99 { 0x04002676, 0x00000002 },
100 { 0x00007677, 0x00000002 },
101 { 0x00007678, 0x00000006 },
102 { 0x0000002e, 0x00000018 },
103 { 0x0000002e, 0x00000018 },
104 { 0000000000, 0x00000006 },
105 { 0x0000002f, 0x00000018 },
106 { 0x0000002f, 0x00000018 },
107 { 0000000000, 0x00000006 },
108 { 0x01605000, 0x00000002 },
109 { 0x00065000, 0x00000002 },
110 { 0x00098000, 0x00000002 },
111 { 0x00061000, 0x00000002 },
112 { 0x64c0603d, 0x00000004 },
113 { 0x00080000, 0x00000016 },
114 { 0000000000, 0000000000 },
115 { 0x0400251d, 0x00000002 },
116 { 0x00007580, 0x00000002 },
117 { 0x00067581, 0x00000002 },
118 { 0x04002580, 0x00000002 },
119 { 0x00067581, 0x00000002 },
120 { 0x00000046, 0x00000004 },
121 { 0x00005000, 0000000000 },
122 { 0x00061000, 0x00000002 },
123 { 0x0000750e, 0x00000002 },
124 { 0x00019000, 0x00000002 },
125 { 0x00011055, 0x00000014 },
126 { 0x00000055, 0x00000012 },
127 { 0x0400250f, 0x00000002 },
128 { 0x0000504a, 0x00000004 },
129 { 0x00007565, 0x00000002 },
130 { 0x00007566, 0x00000002 },
131 { 0x00000051, 0x00000004 },
132 { 0x01e655b4, 0x00000002 },
133 { 0x4401b0dc, 0x00000002 },
134 { 0x01c110dc, 0x00000002 },
135 { 0x2666705d, 0x00000018 },
136 { 0x040c2565, 0x00000002 },
137 { 0x0000005d, 0x00000018 },
138 { 0x04002564, 0x00000002 },
139 { 0x00007566, 0x00000002 },
140 { 0x00000054, 0x00000004 },
141 { 0x00401060, 0x00000008 },
142 { 0x00101000, 0x00000002 },
143 { 0x000d80ff, 0x00000002 },
144 { 0x00800063, 0x00000008 },
145 { 0x000f9000, 0x00000002 },
146 { 0x000e00ff, 0x00000002 },
147 { 0000000000, 0x00000006 },
148 { 0x00000080, 0x00000018 },
149 { 0x00000054, 0x00000004 },
150 { 0x00007576, 0x00000002 },
151 { 0x00065000, 0x00000002 },
152 { 0x00009000, 0x00000002 },
153 { 0x00041000, 0x00000002 },
154 { 0x0c00350e, 0x00000002 },
155 { 0x00049000, 0x00000002 },
156 { 0x00051000, 0x00000002 },
157 { 0x01e785f8, 0x00000002 },
158 { 0x00200000, 0x00000002 },
159 { 0x00600073, 0x0000000c },
160 { 0x00007563, 0x00000002 },
161 { 0x006075f0, 0x00000021 },
162 { 0x20007068, 0x00000004 },
163 { 0x00005068, 0x00000004 },
164 { 0x00007576, 0x00000002 },
165 { 0x00007577, 0x00000002 },
166 { 0x0000750e, 0x00000002 },
167 { 0x0000750f, 0x00000002 },
168 { 0x00a05000, 0x00000002 },
169 { 0x00600076, 0x0000000c },
170 { 0x006075f0, 0x00000021 },
171 { 0x000075f8, 0x00000002 },
172 { 0x00000076, 0x00000004 },
173 { 0x000a750e, 0x00000002 },
174 { 0x0020750f, 0x00000002 },
175 { 0x00600079, 0x00000004 },
176 { 0x00007570, 0x00000002 },
177 { 0x00007571, 0x00000002 },
178 { 0x00007572, 0x00000006 },
179 { 0x00005000, 0x00000002 },
180 { 0x00a05000, 0x00000002 },
181 { 0x00007568, 0x00000002 },
182 { 0x00061000, 0x00000002 },
183 { 0x00000084, 0x0000000c },
184 { 0x00058000, 0x00000002 },
185 { 0x0c607562, 0x00000002 },
186 { 0x00000086, 0x00000004 },
187 { 0x00600085, 0x00000004 },
188 { 0x400070dd, 0000000000 },
189 { 0x000380dd, 0x00000002 },
190 { 0x00000093, 0x0000001c },
191 { 0x00065095, 0x00000018 },
192 { 0x040025bb, 0x00000002 },
193 { 0x00061096, 0x00000018 },
194 { 0x040075bc, 0000000000 },
195 { 0x000075bb, 0x00000002 },
196 { 0x000075bc, 0000000000 },
197 { 0x00090000, 0x00000006 },
198 { 0x00090000, 0x00000002 },
199 { 0x000d8002, 0x00000006 },
200 { 0x00005000, 0x00000002 },
201 { 0x00007821, 0x00000002 },
202 { 0x00007800, 0000000000 },
203 { 0x00007821, 0x00000002 },
204 { 0x00007800, 0000000000 },
205 { 0x01665000, 0x00000002 },
206 { 0x000a0000, 0x00000002 },
207 { 0x000671cc, 0x00000002 },
208 { 0x0286f1cd, 0x00000002 },
209 { 0x000000a3, 0x00000010 },
210 { 0x21007000, 0000000000 },
211 { 0x000000aa, 0x0000001c },
212 { 0x00065000, 0x00000002 },
213 { 0x000a0000, 0x00000002 },
214 { 0x00061000, 0x00000002 },
215 { 0x000b0000, 0x00000002 },
216 { 0x38067000, 0x00000002 },
217 { 0x000a00a6, 0x00000004 },
218 { 0x20007000, 0000000000 },
219 { 0x01200000, 0x00000002 },
220 { 0x20077000, 0x00000002 },
221 { 0x01200000, 0x00000002 },
222 { 0x20007000, 0000000000 },
223 { 0x00061000, 0x00000002 },
224 { 0x0120751b, 0x00000002 },
225 { 0x8040750a, 0x00000002 },
226 { 0x8040750b, 0x00000002 },
227 { 0x00110000, 0x00000002 },
228 { 0x000380dd, 0x00000002 },
229 { 0x000000bd, 0x0000001c },
230 { 0x00061096, 0x00000018 },
231 { 0x844075bd, 0x00000002 },
232 { 0x00061095, 0x00000018 },
233 { 0x840075bb, 0x00000002 },
234 { 0x00061096, 0x00000018 },
235 { 0x844075bc, 0x00000002 },
236 { 0x000000c0, 0x00000004 },
237 { 0x804075bd, 0x00000002 },
238 { 0x800075bb, 0x00000002 },
239 { 0x804075bc, 0x00000002 },
240 { 0x00108000, 0x00000002 },
241 { 0x01400000, 0x00000002 },
242 { 0x006000c4, 0x0000000c },
243 { 0x20c07000, 0x00000020 },
244 { 0x000000c6, 0x00000012 },
245 { 0x00800000, 0x00000006 },
246 { 0x0080751d, 0x00000006 },
247 { 0x000025bb, 0x00000002 },
248 { 0x000040c0, 0x00000004 },
249 { 0x0000775c, 0x00000002 },
250 { 0x00a05000, 0x00000002 },
251 { 0x00661000, 0x00000002 },
252 { 0x0460275d, 0x00000020 },
253 { 0x00004000, 0000000000 },
254 { 0x00007999, 0x00000002 },
255 { 0x00a05000, 0x00000002 },
256 { 0x00661000, 0x00000002 },
257 { 0x0460299b, 0x00000020 },
258 { 0x00004000, 0000000000 },
259 { 0x01e00830, 0x00000002 },
260 { 0x21007000, 0000000000 },
261 { 0x00005000, 0x00000002 },
262 { 0x00038042, 0x00000002 },
263 { 0x040025e0, 0x00000002 },
264 { 0x000075e1, 0000000000 },
265 { 0x00000001, 0000000000 },
266 { 0x000380d9, 0x00000002 },
267 { 0x04007394, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 { 0000000000, 0000000000 },
300 { 0000000000, 0000000000 },
301 { 0000000000, 0000000000 },
302 { 0000000000, 0000000000 },
303 { 0000000000, 0000000000 },
307 static u32 radeon_cp_microcode[][2] = {
308 { 0x21007000, 0000000000 },
309 { 0x20007000, 0000000000 },
310 { 0x000000b4, 0x00000004 },
311 { 0x000000b8, 0x00000004 },
312 { 0x6f5b4d4c, 0000000000 },
313 { 0x4c4c427f, 0000000000 },
314 { 0x5b568a92, 0000000000 },
315 { 0x4ca09c6d, 0000000000 },
316 { 0xad4c4c4c, 0000000000 },
317 { 0x4ce1af3d, 0000000000 },
318 { 0xd8afafaf, 0000000000 },
319 { 0xd64c4cdc, 0000000000 },
320 { 0x4cd10d10, 0000000000 },
321 { 0x000f0000, 0x00000016 },
322 { 0x362f242d, 0000000000 },
323 { 0x00000012, 0x00000004 },
324 { 0x000f0000, 0x00000016 },
325 { 0x362f282d, 0000000000 },
326 { 0x000380e7, 0x00000002 },
327 { 0x04002c97, 0x00000002 },
328 { 0x000f0001, 0x00000016 },
329 { 0x333a3730, 0000000000 },
330 { 0x000077ef, 0x00000002 },
331 { 0x00061000, 0x00000002 },
332 { 0x00000021, 0x0000001a },
333 { 0x00004000, 0x0000001e },
334 { 0x00061000, 0x00000002 },
335 { 0x00000021, 0x0000001a },
336 { 0x00004000, 0x0000001e },
337 { 0x00061000, 0x00000002 },
338 { 0x00000021, 0x0000001a },
339 { 0x00004000, 0x0000001e },
340 { 0x00000017, 0x00000004 },
341 { 0x0003802b, 0x00000002 },
342 { 0x040067e0, 0x00000002 },
343 { 0x00000017, 0x00000004 },
344 { 0x000077e0, 0x00000002 },
345 { 0x00065000, 0x00000002 },
346 { 0x000037e1, 0x00000002 },
347 { 0x040067e1, 0x00000006 },
348 { 0x000077e0, 0x00000002 },
349 { 0x000077e1, 0x00000002 },
350 { 0x000077e1, 0x00000006 },
351 { 0xffffffff, 0000000000 },
352 { 0x10000000, 0000000000 },
353 { 0x0003802b, 0x00000002 },
354 { 0x040067e0, 0x00000006 },
355 { 0x00007675, 0x00000002 },
356 { 0x00007676, 0x00000002 },
357 { 0x00007677, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0003802c, 0x00000002 },
360 { 0x04002676, 0x00000002 },
361 { 0x00007677, 0x00000002 },
362 { 0x00007678, 0x00000006 },
363 { 0x0000002f, 0x00000018 },
364 { 0x0000002f, 0x00000018 },
365 { 0000000000, 0x00000006 },
366 { 0x00000030, 0x00000018 },
367 { 0x00000030, 0x00000018 },
368 { 0000000000, 0x00000006 },
369 { 0x01605000, 0x00000002 },
370 { 0x00065000, 0x00000002 },
371 { 0x00098000, 0x00000002 },
372 { 0x00061000, 0x00000002 },
373 { 0x64c0603e, 0x00000004 },
374 { 0x000380e6, 0x00000002 },
375 { 0x040025c5, 0x00000002 },
376 { 0x00080000, 0x00000016 },
377 { 0000000000, 0000000000 },
378 { 0x0400251d, 0x00000002 },
379 { 0x00007580, 0x00000002 },
380 { 0x00067581, 0x00000002 },
381 { 0x04002580, 0x00000002 },
382 { 0x00067581, 0x00000002 },
383 { 0x00000049, 0x00000004 },
384 { 0x00005000, 0000000000 },
385 { 0x000380e6, 0x00000002 },
386 { 0x040025c5, 0x00000002 },
387 { 0x00061000, 0x00000002 },
388 { 0x0000750e, 0x00000002 },
389 { 0x00019000, 0x00000002 },
390 { 0x00011055, 0x00000014 },
391 { 0x00000055, 0x00000012 },
392 { 0x0400250f, 0x00000002 },
393 { 0x0000504f, 0x00000004 },
394 { 0x000380e6, 0x00000002 },
395 { 0x040025c5, 0x00000002 },
396 { 0x00007565, 0x00000002 },
397 { 0x00007566, 0x00000002 },
398 { 0x00000058, 0x00000004 },
399 { 0x000380e6, 0x00000002 },
400 { 0x040025c5, 0x00000002 },
401 { 0x01e655b4, 0x00000002 },
402 { 0x4401b0e4, 0x00000002 },
403 { 0x01c110e4, 0x00000002 },
404 { 0x26667066, 0x00000018 },
405 { 0x040c2565, 0x00000002 },
406 { 0x00000066, 0x00000018 },
407 { 0x04002564, 0x00000002 },
408 { 0x00007566, 0x00000002 },
409 { 0x0000005d, 0x00000004 },
410 { 0x00401069, 0x00000008 },
411 { 0x00101000, 0x00000002 },
412 { 0x000d80ff, 0x00000002 },
413 { 0x0080006c, 0x00000008 },
414 { 0x000f9000, 0x00000002 },
415 { 0x000e00ff, 0x00000002 },
416 { 0000000000, 0x00000006 },
417 { 0x0000008f, 0x00000018 },
418 { 0x0000005b, 0x00000004 },
419 { 0x000380e6, 0x00000002 },
420 { 0x040025c5, 0x00000002 },
421 { 0x00007576, 0x00000002 },
422 { 0x00065000, 0x00000002 },
423 { 0x00009000, 0x00000002 },
424 { 0x00041000, 0x00000002 },
425 { 0x0c00350e, 0x00000002 },
426 { 0x00049000, 0x00000002 },
427 { 0x00051000, 0x00000002 },
428 { 0x01e785f8, 0x00000002 },
429 { 0x00200000, 0x00000002 },
430 { 0x0060007e, 0x0000000c },
431 { 0x00007563, 0x00000002 },
432 { 0x006075f0, 0x00000021 },
433 { 0x20007073, 0x00000004 },
434 { 0x00005073, 0x00000004 },
435 { 0x000380e6, 0x00000002 },
436 { 0x040025c5, 0x00000002 },
437 { 0x00007576, 0x00000002 },
438 { 0x00007577, 0x00000002 },
439 { 0x0000750e, 0x00000002 },
440 { 0x0000750f, 0x00000002 },
441 { 0x00a05000, 0x00000002 },
442 { 0x00600083, 0x0000000c },
443 { 0x006075f0, 0x00000021 },
444 { 0x000075f8, 0x00000002 },
445 { 0x00000083, 0x00000004 },
446 { 0x000a750e, 0x00000002 },
447 { 0x000380e6, 0x00000002 },
448 { 0x040025c5, 0x00000002 },
449 { 0x0020750f, 0x00000002 },
450 { 0x00600086, 0x00000004 },
451 { 0x00007570, 0x00000002 },
452 { 0x00007571, 0x00000002 },
453 { 0x00007572, 0x00000006 },
454 { 0x000380e6, 0x00000002 },
455 { 0x040025c5, 0x00000002 },
456 { 0x00005000, 0x00000002 },
457 { 0x00a05000, 0x00000002 },
458 { 0x00007568, 0x00000002 },
459 { 0x00061000, 0x00000002 },
460 { 0x00000095, 0x0000000c },
461 { 0x00058000, 0x00000002 },
462 { 0x0c607562, 0x00000002 },
463 { 0x00000097, 0x00000004 },
464 { 0x000380e6, 0x00000002 },
465 { 0x040025c5, 0x00000002 },
466 { 0x00600096, 0x00000004 },
467 { 0x400070e5, 0000000000 },
468 { 0x000380e6, 0x00000002 },
469 { 0x040025c5, 0x00000002 },
470 { 0x000380e5, 0x00000002 },
471 { 0x000000a8, 0x0000001c },
472 { 0x000650aa, 0x00000018 },
473 { 0x040025bb, 0x00000002 },
474 { 0x000610ab, 0x00000018 },
475 { 0x040075bc, 0000000000 },
476 { 0x000075bb, 0x00000002 },
477 { 0x000075bc, 0000000000 },
478 { 0x00090000, 0x00000006 },
479 { 0x00090000, 0x00000002 },
480 { 0x000d8002, 0x00000006 },
481 { 0x00007832, 0x00000002 },
482 { 0x00005000, 0x00000002 },
483 { 0x000380e7, 0x00000002 },
484 { 0x04002c97, 0x00000002 },
485 { 0x00007820, 0x00000002 },
486 { 0x00007821, 0x00000002 },
487 { 0x00007800, 0000000000 },
488 { 0x01200000, 0x00000002 },
489 { 0x20077000, 0x00000002 },
490 { 0x01200000, 0x00000002 },
491 { 0x20007000, 0x00000002 },
492 { 0x00061000, 0x00000002 },
493 { 0x0120751b, 0x00000002 },
494 { 0x8040750a, 0x00000002 },
495 { 0x8040750b, 0x00000002 },
496 { 0x00110000, 0x00000002 },
497 { 0x000380e5, 0x00000002 },
498 { 0x000000c6, 0x0000001c },
499 { 0x000610ab, 0x00000018 },
500 { 0x844075bd, 0x00000002 },
501 { 0x000610aa, 0x00000018 },
502 { 0x840075bb, 0x00000002 },
503 { 0x000610ab, 0x00000018 },
504 { 0x844075bc, 0x00000002 },
505 { 0x000000c9, 0x00000004 },
506 { 0x804075bd, 0x00000002 },
507 { 0x800075bb, 0x00000002 },
508 { 0x804075bc, 0x00000002 },
509 { 0x00108000, 0x00000002 },
510 { 0x01400000, 0x00000002 },
511 { 0x006000cd, 0x0000000c },
512 { 0x20c07000, 0x00000020 },
513 { 0x000000cf, 0x00000012 },
514 { 0x00800000, 0x00000006 },
515 { 0x0080751d, 0x00000006 },
516 { 0000000000, 0000000000 },
517 { 0x0000775c, 0x00000002 },
518 { 0x00a05000, 0x00000002 },
519 { 0x00661000, 0x00000002 },
520 { 0x0460275d, 0x00000020 },
521 { 0x00004000, 0000000000 },
522 { 0x01e00830, 0x00000002 },
523 { 0x21007000, 0000000000 },
524 { 0x6464614d, 0000000000 },
525 { 0x69687420, 0000000000 },
526 { 0x00000073, 0000000000 },
527 { 0000000000, 0000000000 },
528 { 0x00005000, 0x00000002 },
529 { 0x000380d0, 0x00000002 },
530 { 0x040025e0, 0x00000002 },
531 { 0x000075e1, 0000000000 },
532 { 0x00000001, 0000000000 },
533 { 0x000380e0, 0x00000002 },
534 { 0x04002394, 0x00000002 },
535 { 0x00005000, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0x00000008, 0000000000 },
539 { 0x00000004, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 { 0000000000, 0000000000 },
560 { 0000000000, 0000000000 },
561 { 0000000000, 0000000000 },
562 { 0000000000, 0000000000 },
563 { 0000000000, 0000000000 },
567 int RADEON_READ_PLL(drm_device_t *dev, int addr)
569 drm_radeon_private_t *dev_priv = dev->dev_private;
571 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
572 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
575 #if RADEON_FIFO_DEBUG
576 static void radeon_status( drm_radeon_private_t *dev_priv )
578 printk( "%s:\n", __FUNCTION__ );
579 printk( "RBBM_STATUS = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
581 printk( "CP_RB_RTPR = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
583 printk( "CP_RB_WTPR = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
585 printk( "AIC_CNTL = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
587 printk( "AIC_STAT = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
589 printk( "AIC_PT_BASE = 0x%08x\n",
590 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
591 printk( "TLB_ADDR = 0x%08x\n",
592 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
593 printk( "TLB_DATA = 0x%08x\n",
594 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
599 /* ================================================================
600 * Engine, FIFO control
603 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
608 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
610 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
611 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
612 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
614 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
615 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
616 & RADEON_RB2D_DC_BUSY) ) {
622 #if RADEON_FIFO_DEBUG
623 DRM_ERROR( "failed!\n" );
624 radeon_status( dev_priv );
626 return DRM_ERR(EBUSY);
629 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
634 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
636 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
637 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
638 & RADEON_RBBM_FIFOCNT_MASK );
639 if ( slots >= entries ) return 0;
643 #if RADEON_FIFO_DEBUG
644 DRM_ERROR( "failed!\n" );
645 radeon_status( dev_priv );
647 return DRM_ERR(EBUSY);
650 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
654 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
656 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
657 if ( ret ) return ret;
659 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
660 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
661 & RADEON_RBBM_ACTIVE) ) {
662 radeon_do_pixcache_flush( dev_priv );
668 #if RADEON_FIFO_DEBUG
669 DRM_ERROR( "failed!\n" );
670 radeon_status( dev_priv );
672 return DRM_ERR(EBUSY);
676 /* ================================================================
677 * CP control, initialization
680 /* Load the microcode for the CP */
681 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
686 radeon_do_wait_for_idle( dev_priv );
688 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
690 if (dev_priv->is_r200)
692 DRM_INFO("Loading R200 Microcode\n");
693 for ( i = 0 ; i < 256 ; i++ )
695 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
696 R200_cp_microcode[i][1] );
697 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
698 R200_cp_microcode[i][0] );
703 for ( i = 0 ; i < 256 ; i++ ) {
704 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
705 radeon_cp_microcode[i][1] );
706 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
707 radeon_cp_microcode[i][0] );
712 /* Flush any pending commands to the CP. This should only be used just
713 * prior to a wait for idle, as it informs the engine that the command
716 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
722 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
723 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
727 /* Wait for the CP to go idle.
729 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
736 RADEON_PURGE_CACHE();
737 RADEON_PURGE_ZCACHE();
738 RADEON_WAIT_UNTIL_IDLE();
743 return radeon_do_wait_for_idle( dev_priv );
746 /* Start the Command Processor.
748 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
753 radeon_do_wait_for_idle( dev_priv );
755 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
757 dev_priv->cp_running = 1;
761 RADEON_PURGE_CACHE();
762 RADEON_PURGE_ZCACHE();
763 RADEON_WAIT_UNTIL_IDLE();
769 /* Reset the Command Processor. This will not flush any pending
770 * commands, so you must wait for the CP command stream to complete
771 * before calling this routine.
773 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
778 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
779 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
780 *dev_priv->ring.head = cur_read_ptr;
781 dev_priv->ring.tail = cur_read_ptr;
784 /* Stop the Command Processor. This will not flush any pending
785 * commands, so you must flush the command stream and wait for the CP
786 * to go idle before calling this routine.
788 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
792 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
794 dev_priv->cp_running = 0;
797 /* Reset the engine. This will stop the CP if it is running.
799 static int radeon_do_engine_reset( drm_device_t *dev )
801 drm_radeon_private_t *dev_priv = dev->dev_private;
802 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
805 radeon_do_pixcache_flush( dev_priv );
807 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
808 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
810 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
811 RADEON_FORCEON_MCLKA |
812 RADEON_FORCEON_MCLKB |
813 RADEON_FORCEON_YCLKA |
814 RADEON_FORCEON_YCLKB |
816 RADEON_FORCEON_AIC ) );
818 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
820 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
821 RADEON_SOFT_RESET_CP |
822 RADEON_SOFT_RESET_HI |
823 RADEON_SOFT_RESET_SE |
824 RADEON_SOFT_RESET_RE |
825 RADEON_SOFT_RESET_PP |
826 RADEON_SOFT_RESET_E2 |
827 RADEON_SOFT_RESET_RB ) );
828 RADEON_READ( RADEON_RBBM_SOFT_RESET );
829 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
830 ~( RADEON_SOFT_RESET_CP |
831 RADEON_SOFT_RESET_HI |
832 RADEON_SOFT_RESET_SE |
833 RADEON_SOFT_RESET_RE |
834 RADEON_SOFT_RESET_PP |
835 RADEON_SOFT_RESET_E2 |
836 RADEON_SOFT_RESET_RB ) ) );
837 RADEON_READ( RADEON_RBBM_SOFT_RESET );
840 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
841 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
842 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
844 /* Reset the CP ring */
845 radeon_do_cp_reset( dev_priv );
847 /* The CP is no longer running after an engine reset */
848 dev_priv->cp_running = 0;
850 /* Reset any pending vertex, indirect buffers */
851 radeon_freelist_reset( dev );
856 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
857 drm_radeon_private_t *dev_priv )
859 u32 ring_start, cur_read_ptr;
862 /* Initialize the memory controller */
863 RADEON_WRITE( RADEON_MC_FB_LOCATION,
864 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
866 if ( !dev_priv->is_pci ) {
867 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
868 (((dev_priv->agp_vm_start - 1 +
869 dev_priv->agp_size) & 0xffff0000) |
870 (dev_priv->agp_vm_start >> 16)) );
873 #if __REALLY_HAVE_AGP
874 if ( !dev_priv->is_pci )
875 ring_start = (dev_priv->cp_ring->offset
877 + dev_priv->agp_vm_start);
880 ring_start = (dev_priv->cp_ring->offset
882 + dev_priv->agp_vm_start);
884 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
886 /* Set the write pointer delay */
887 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
889 /* Initialize the ring buffer's read and write pointers */
890 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
891 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
892 *dev_priv->ring.head = cur_read_ptr;
893 dev_priv->ring.tail = cur_read_ptr;
895 if ( !dev_priv->is_pci ) {
896 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
897 dev_priv->ring_rptr->offset );
899 drm_sg_mem_t *entry = dev->sg;
900 unsigned long tmp_ofs, page_ofs;
902 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
903 page_ofs = tmp_ofs >> PAGE_SHIFT;
905 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
906 entry->busaddr[page_ofs]);
907 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
908 entry->busaddr[page_ofs],
909 entry->handle + tmp_ofs );
912 /* Initialize the scratch register pointer. This will cause
913 * the scratch register values to be written out to memory
914 * whenever they are updated.
916 * We simply put this behind the ring read pointer, this works
917 * with PCI GART as well as (whatever kind of) AGP GART
919 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
920 + RADEON_SCRATCH_REG_OFFSET );
922 dev_priv->scratch = ((__volatile__ u32 *)
923 dev_priv->ring.head +
924 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
926 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
928 /* Writeback doesn't seem to work everywhere, test it first */
929 DRM_WRITE32( &dev_priv->scratch[1], 0 );
930 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
932 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
933 if ( DRM_READ32( &dev_priv->scratch[1] ) == 0xdeadbeef )
938 if ( tmp < dev_priv->usec_timeout ) {
939 dev_priv->writeback_works = 1;
940 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
942 dev_priv->writeback_works = 0;
943 DRM_DEBUG( "writeback test failed\n" );
946 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
947 RADEON_WRITE( RADEON_LAST_FRAME_REG,
948 dev_priv->sarea_priv->last_frame );
950 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
951 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
952 dev_priv->sarea_priv->last_dispatch );
954 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
955 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
956 dev_priv->sarea_priv->last_clear );
958 /* Set ring buffer size */
960 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
962 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
965 radeon_do_wait_for_idle( dev_priv );
967 /* Turn on bus mastering */
968 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
969 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
971 /* Sync everything up */
972 RADEON_WRITE( RADEON_ISYNC_CNTL,
973 (RADEON_ISYNC_ANY2D_IDLE3D |
974 RADEON_ISYNC_ANY3D_IDLE2D |
975 RADEON_ISYNC_WAIT_IDLEGUI |
976 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
979 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
981 drm_radeon_private_t *dev_priv;
985 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
986 if ( dev_priv == NULL )
987 return DRM_ERR(ENOMEM);
989 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
991 dev_priv->is_pci = init->is_pci;
993 #if !defined(PCIGART_ENABLED)
994 /* PCI support is not 100% working, so we disable it here.
996 if ( dev_priv->is_pci ) {
997 DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
998 dev->dev_private = (void *)dev_priv;
999 radeon_do_cleanup_cp(dev);
1000 return DRM_ERR(EINVAL);
1004 if ( dev_priv->is_pci && !dev->sg ) {
1005 DRM_ERROR( "PCI GART memory not allocated!\n" );
1006 dev->dev_private = (void *)dev_priv;
1007 radeon_do_cleanup_cp(dev);
1008 return DRM_ERR(EINVAL);
1011 dev_priv->usec_timeout = init->usec_timeout;
1012 if ( dev_priv->usec_timeout < 1 ||
1013 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1014 DRM_DEBUG( "TIMEOUT problem!\n" );
1015 dev->dev_private = (void *)dev_priv;
1016 radeon_do_cleanup_cp(dev);
1017 return DRM_ERR(EINVAL);
1020 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1021 dev_priv->do_boxes = 0;
1022 dev_priv->cp_mode = init->cp_mode;
1024 /* We don't support anything other than bus-mastering ring mode,
1025 * but the ring can be in either AGP or PCI space for the ring
1028 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1029 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1030 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1031 dev->dev_private = (void *)dev_priv;
1032 radeon_do_cleanup_cp(dev);
1033 return DRM_ERR(EINVAL);
1036 switch ( init->fb_bpp ) {
1038 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1042 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1045 dev_priv->front_offset = init->front_offset;
1046 dev_priv->front_pitch = init->front_pitch;
1047 dev_priv->back_offset = init->back_offset;
1048 dev_priv->back_pitch = init->back_pitch;
1050 switch ( init->depth_bpp ) {
1052 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1056 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1059 dev_priv->depth_offset = init->depth_offset;
1060 dev_priv->depth_pitch = init->depth_pitch;
1062 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1063 (dev_priv->front_offset >> 10));
1064 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1065 (dev_priv->back_offset >> 10));
1066 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1067 (dev_priv->depth_offset >> 10));
1069 /* Hardware state for depth clears. Remove this if/when we no
1070 * longer clear the depth buffer with a 3D rectangle. Hard-code
1071 * all values to prevent unwanted 3D state from slipping through
1072 * and screwing with the clear operation.
1074 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1075 (dev_priv->color_fmt << 10) |
1078 dev_priv->depth_clear.rb3d_zstencilcntl =
1079 (dev_priv->depth_fmt |
1080 RADEON_Z_TEST_ALWAYS |
1081 RADEON_STENCIL_TEST_ALWAYS |
1082 RADEON_STENCIL_S_FAIL_REPLACE |
1083 RADEON_STENCIL_ZPASS_REPLACE |
1084 RADEON_STENCIL_ZFAIL_REPLACE |
1085 RADEON_Z_WRITE_ENABLE);
1087 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1088 RADEON_BFACE_SOLID |
1089 RADEON_FFACE_SOLID |
1090 RADEON_FLAT_SHADE_VTX_LAST |
1091 RADEON_DIFFUSE_SHADE_FLAT |
1092 RADEON_ALPHA_SHADE_FLAT |
1093 RADEON_SPECULAR_SHADE_FLAT |
1094 RADEON_FOG_SHADE_FLAT |
1095 RADEON_VTX_PIX_CENTER_OGL |
1096 RADEON_ROUND_MODE_TRUNC |
1097 RADEON_ROUND_PREC_8TH_PIX);
1101 if(!dev_priv->sarea) {
1102 DRM_ERROR("could not find sarea!\n");
1103 dev->dev_private = (void *)dev_priv;
1104 radeon_do_cleanup_cp(dev);
1105 return DRM_ERR(EINVAL);
1108 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1110 DRM_ERROR("could not find framebuffer!\n");
1111 dev->dev_private = (void *)dev_priv;
1112 radeon_do_cleanup_cp(dev);
1113 return DRM_ERR(EINVAL);
1115 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1116 if(!dev_priv->mmio) {
1117 DRM_ERROR("could not find mmio region!\n");
1118 dev->dev_private = (void *)dev_priv;
1119 radeon_do_cleanup_cp(dev);
1120 return DRM_ERR(EINVAL);
1122 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1123 if(!dev_priv->cp_ring) {
1124 DRM_ERROR("could not find cp ring region!\n");
1125 dev->dev_private = (void *)dev_priv;
1126 radeon_do_cleanup_cp(dev);
1127 return DRM_ERR(EINVAL);
1129 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1130 if(!dev_priv->ring_rptr) {
1131 DRM_ERROR("could not find ring read pointer!\n");
1132 dev->dev_private = (void *)dev_priv;
1133 radeon_do_cleanup_cp(dev);
1134 return DRM_ERR(EINVAL);
1136 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1137 if(!dev_priv->buffers) {
1138 DRM_ERROR("could not find dma buffer region!\n");
1139 dev->dev_private = (void *)dev_priv;
1140 radeon_do_cleanup_cp(dev);
1141 return DRM_ERR(EINVAL);
1144 if ( !dev_priv->is_pci ) {
1145 DRM_FIND_MAP( dev_priv->agp_textures,
1146 init->agp_textures_offset );
1147 if(!dev_priv->agp_textures) {
1148 DRM_ERROR("could not find agp texture region!\n");
1149 dev->dev_private = (void *)dev_priv;
1150 radeon_do_cleanup_cp(dev);
1151 return DRM_ERR(EINVAL);
1155 dev_priv->sarea_priv =
1156 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1157 init->sarea_priv_offset);
1159 if ( !dev_priv->is_pci ) {
1160 DRM_IOREMAP( dev_priv->cp_ring );
1161 DRM_IOREMAP( dev_priv->ring_rptr );
1162 DRM_IOREMAP( dev_priv->buffers );
1163 if(!dev_priv->cp_ring->handle ||
1164 !dev_priv->ring_rptr->handle ||
1165 !dev_priv->buffers->handle) {
1166 DRM_ERROR("could not find ioremap agp regions!\n");
1167 dev->dev_private = (void *)dev_priv;
1168 radeon_do_cleanup_cp(dev);
1169 return DRM_ERR(EINVAL);
1172 dev_priv->cp_ring->handle =
1173 (void *)dev_priv->cp_ring->offset;
1174 dev_priv->ring_rptr->handle =
1175 (void *)dev_priv->ring_rptr->offset;
1176 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1178 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1179 dev_priv->cp_ring->handle );
1180 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1181 dev_priv->ring_rptr->handle );
1182 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1183 dev_priv->buffers->handle );
1187 dev_priv->agp_size = init->agp_size;
1188 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1189 #if __REALLY_HAVE_AGP
1190 if ( !dev_priv->is_pci )
1191 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1193 + dev_priv->agp_vm_start);
1196 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1198 + dev_priv->agp_vm_start);
1200 DRM_DEBUG( "dev_priv->agp_size %d\n",
1201 dev_priv->agp_size );
1202 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1203 dev_priv->agp_vm_start );
1204 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1205 dev_priv->agp_buffers_offset );
1207 dev_priv->ring.head = ((__volatile__ u32 *)
1208 dev_priv->ring_rptr->handle);
1210 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1211 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1212 + init->ring_size / sizeof(u32));
1213 dev_priv->ring.size = init->ring_size;
1214 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1216 dev_priv->ring.tail_mask =
1217 (dev_priv->ring.size / sizeof(u32)) - 1;
1219 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1221 #if __REALLY_HAVE_SG
1222 if ( dev_priv->is_pci ) {
1223 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1224 &dev_priv->bus_pci_gart)) {
1225 DRM_ERROR( "failed to init PCI GART!\n" );
1226 dev->dev_private = (void *)dev_priv;
1227 radeon_do_cleanup_cp(dev);
1228 return DRM_ERR(ENOMEM);
1232 tmp = RADEON_READ( RADEON_AIC_CNTL )
1233 | RADEON_PCIGART_TRANSLATE_EN;
1234 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1236 /* set PCI GART page-table base address
1238 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1240 /* set address range for PCI address translate
1242 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1243 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1244 + dev_priv->agp_size - 1);
1246 /* Turn off AGP aperture -- is this required for PCIGART?
1248 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1249 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1251 #endif /* __REALLY_HAVE_SG */
1252 /* Turn off PCI GART
1254 tmp = RADEON_READ( RADEON_AIC_CNTL )
1255 & ~RADEON_PCIGART_TRANSLATE_EN;
1256 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1257 #if __REALLY_HAVE_SG
1259 #endif /* __REALLY_HAVE_SG */
1261 radeon_cp_load_microcode( dev_priv );
1262 radeon_cp_init_ring_buffer( dev, dev_priv );
1264 dev_priv->last_buf = 0;
1266 dev->dev_private = (void *)dev_priv;
1268 radeon_do_engine_reset( dev );
1273 int radeon_do_cleanup_cp( drm_device_t *dev )
1277 if ( dev->dev_private ) {
1278 drm_radeon_private_t *dev_priv = dev->dev_private;
1280 if ( !dev_priv->is_pci ) {
1281 DRM_IOREMAPFREE( dev_priv->cp_ring );
1282 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1283 DRM_IOREMAPFREE( dev_priv->buffers );
1285 #if __REALLY_HAVE_SG
1286 if (!DRM(ati_pcigart_cleanup)( dev,
1287 dev_priv->phys_pci_gart,
1288 dev_priv->bus_pci_gart ))
1289 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1290 #endif /* __REALLY_HAVE_SG */
1293 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1295 dev->dev_private = NULL;
1301 int radeon_cp_init( DRM_IOCTL_ARGS )
1304 drm_radeon_init_t init;
1306 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1308 switch ( init.func ) {
1309 case RADEON_INIT_CP:
1310 case RADEON_INIT_R200_CP:
1311 return radeon_do_init_cp( dev, &init );
1312 case RADEON_CLEANUP_CP:
1313 return radeon_do_cleanup_cp( dev );
1316 return DRM_ERR(EINVAL);
1319 int radeon_cp_start( DRM_IOCTL_ARGS )
1322 drm_radeon_private_t *dev_priv = dev->dev_private;
1325 LOCK_TEST_WITH_RETURN( dev );
1327 if ( dev_priv->cp_running ) {
1328 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1331 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1332 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1333 __FUNCTION__, dev_priv->cp_mode );
1337 radeon_do_cp_start( dev_priv );
1342 /* Stop the CP. The engine must have been idled before calling this
1345 int radeon_cp_stop( DRM_IOCTL_ARGS )
1348 drm_radeon_private_t *dev_priv = dev->dev_private;
1349 drm_radeon_cp_stop_t stop;
1353 LOCK_TEST_WITH_RETURN( dev );
1355 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1357 if (!dev_priv->cp_running)
1360 /* Flush any pending CP commands. This ensures any outstanding
1361 * commands are exectuted by the engine before we turn it off.
1364 radeon_do_cp_flush( dev_priv );
1367 /* If we fail to make the engine go idle, we return an error
1368 * code so that the DRM ioctl wrapper can try again.
1371 ret = radeon_do_cp_idle( dev_priv );
1372 if ( ret ) return ret;
1375 /* Finally, we can turn off the CP. If the engine isn't idle,
1376 * we will get some dropped triangles as they won't be fully
1377 * rendered before the CP is shut down.
1379 radeon_do_cp_stop( dev_priv );
1381 /* Reset the engine */
1382 radeon_do_engine_reset( dev );
1388 void radeon_do_release( drm_device_t *dev )
1390 drm_radeon_private_t *dev_priv = dev->dev_private;
1394 radeon_do_cp_flush( dev_priv );
1395 radeon_do_cp_idle( dev_priv );
1396 radeon_do_cp_stop( dev_priv );
1397 radeon_do_engine_reset( dev );
1399 /* Disable *all* interrupts */
1400 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1402 /* Destroy agp heap ??? */
1403 /* radeon_mem_takedown( &(dev_priv->agp_heap) ); */
1405 /* deallocate kernel resources */
1406 radeon_do_cleanup_cp( dev );
1410 /* Just reset the CP ring. Called as part of an X Server engine reset.
1412 int radeon_cp_reset( DRM_IOCTL_ARGS )
1415 drm_radeon_private_t *dev_priv = dev->dev_private;
1418 LOCK_TEST_WITH_RETURN( dev );
1421 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1422 return DRM_ERR(EINVAL);
1425 radeon_do_cp_reset( dev_priv );
1427 /* The CP is no longer running after an engine reset */
1428 dev_priv->cp_running = 0;
1433 int radeon_cp_idle( DRM_IOCTL_ARGS )
1436 drm_radeon_private_t *dev_priv = dev->dev_private;
1439 LOCK_TEST_WITH_RETURN( dev );
1441 return radeon_do_cp_idle( dev_priv );
1444 int radeon_engine_reset( DRM_IOCTL_ARGS )
1449 LOCK_TEST_WITH_RETURN( dev );
1451 return radeon_do_engine_reset( dev );
1455 /* ================================================================
1459 /* KW: Deprecated to say the least:
1461 int radeon_fullscreen( DRM_IOCTL_ARGS )
1467 /* ================================================================
1468 * Freelist management
1471 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1472 * bufs until freelist code is used. Note this hides a problem with
1473 * the scratch register * (used to keep track of last buffer
1474 * completed) being written to before * the last buffer has actually
1475 * completed rendering.
1477 * KW: It's also a good way to find free buffers quickly.
1479 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1480 * sleep. However, bugs in older versions of radeon_accel.c mean that
1481 * we essentially have to do this, else old clients will break.
1483 * However, it does leave open a potential deadlock where all the
1484 * buffers are held by other clients, which can't release them because
1485 * they can't get the lock.
1488 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1490 drm_device_dma_t *dma = dev->dma;
1491 drm_radeon_private_t *dev_priv = dev->dev_private;
1492 drm_radeon_buf_priv_t *buf_priv;
1497 if ( ++dev_priv->last_buf >= dma->buf_count )
1498 dev_priv->last_buf = 0;
1500 start = dev_priv->last_buf;
1502 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1503 u32 done_age = GET_SCRATCH( 1 );
1504 DRM_DEBUG("done_age = %d\n",done_age);
1505 for ( i = start ; i < dma->buf_count ; i++ ) {
1506 buf = dma->buflist[i];
1507 buf_priv = buf->dev_private;
1508 if ( buf->pid == 0 || (buf->pending &&
1509 buf_priv->age <= done_age) ) {
1510 dev_priv->stats.requested_bufs++;
1519 dev_priv->stats.freelist_loops++;
1523 DRM_DEBUG( "returning NULL!\n" );
1527 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1529 drm_device_dma_t *dma = dev->dma;
1530 drm_radeon_private_t *dev_priv = dev->dev_private;
1531 drm_radeon_buf_priv_t *buf_priv;
1535 u32 done_age = DRM_READ32(&dev_priv->scratch[1]);
1537 if ( ++dev_priv->last_buf >= dma->buf_count )
1538 dev_priv->last_buf = 0;
1540 start = dev_priv->last_buf;
1541 dev_priv->stats.freelist_loops++;
1543 for ( t = 0 ; t < 2 ; t++ ) {
1544 for ( i = start ; i < dma->buf_count ; i++ ) {
1545 buf = dma->buflist[i];
1546 buf_priv = buf->dev_private;
1547 if ( buf->pid == 0 || (buf->pending &&
1548 buf_priv->age <= done_age) ) {
1549 dev_priv->stats.requested_bufs++;
1561 void radeon_freelist_reset( drm_device_t *dev )
1563 drm_device_dma_t *dma = dev->dma;
1564 drm_radeon_private_t *dev_priv = dev->dev_private;
1567 dev_priv->last_buf = 0;
1568 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1569 drm_buf_t *buf = dma->buflist[i];
1570 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1576 /* ================================================================
1577 * CP command submission
1580 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1582 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1584 u32 last_head = GET_RING_HEAD(ring);
1586 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1587 u32 head = GET_RING_HEAD(ring);
1589 ring->space = (head - ring->tail) * sizeof(u32);
1590 if ( ring->space <= 0 )
1591 ring->space += ring->size;
1592 if ( ring->space > n )
1595 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1597 if (head != last_head)
1604 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1605 #if RADEON_FIFO_DEBUG
1606 radeon_status( dev_priv );
1607 DRM_ERROR( "failed!\n" );
1609 return DRM_ERR(EBUSY);
1612 static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
1617 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1618 buf = radeon_freelist_get( dev );
1619 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1621 buf->pid = DRM_CURRENTPID;
1623 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1624 sizeof(buf->idx) ) )
1625 return DRM_ERR(EFAULT);
1626 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1627 sizeof(buf->total) ) )
1628 return DRM_ERR(EFAULT);
1635 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1638 drm_device_dma_t *dma = dev->dma;
1642 LOCK_TEST_WITH_RETURN( dev );
1644 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1646 /* Please don't send us buffers.
1648 if ( d.send_count != 0 ) {
1649 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1650 DRM_CURRENTPID, d.send_count );
1651 return DRM_ERR(EINVAL);
1654 /* We'll send you buffers.
1656 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1657 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1658 DRM_CURRENTPID, d.request_count, dma->buf_count );
1659 return DRM_ERR(EINVAL);
1662 d.granted_count = 0;
1664 if ( d.request_count ) {
1665 ret = radeon_cp_get_buffers( dev, &d );
1668 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );