results/Intel/pentium4-northwood.txt

   1 x86info v1.11.  Dave Jones 2001, 2002
   2 Feedback to <davej@suse.de>.
   3
   4 Found 2 CPUs
   5 MP Table:
   6 #       APIC ID Version State           Family  Model   Step    Flags
   7 #        0       0x14    BSP, usable     15      2       7       0xbfebfbff
   8 #        1       0x14    AP, usable      15      2       7       0xbfebfbff
   9
  10 CPU #1
  11 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
  12 eax in: 0x00000001, eax = 00000f27 ebx = 00020809 ecx = 00000400 edx = bfebfbff
  13 eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040
  14
  15 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
  16 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
  17 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
  18 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
  19 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
  20
  21 Family: 15 Model: 2 Stepping: 7 Type: 0
  22 CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM
  23 Processor name string:
  24
  25 Feature flags:
  26         Onboard FPU
  27         Virtual Mode Extensions
  28         Debugging Extensions
  29         Page Size Extensions
  30         Time Stamp Counter
  31         Model-Specific Registers
  32         Physical Address Extensions
  33         Machine Check Architecture
  34         CMPXCHG8 instruction
  35         Onboard APIC
  36         SYSENTER/SYSEXIT
  37         Memory Type Range Registers
  38         Page Global Enable
  39         Machine Check Architecture
  40         CMOV instruction
  41         Page Attribute Table
  42         36-bit PSEs
  43         CLFLUSH instruction
  44         Debug Trace Store
  45         ACPI via MSR
  46         MMX support
  47         FXSAVE and FXRESTORE instructions
  48         SSE support
  49         SSE2 support
  50         CPU self snoop
  51         Hyper-Threading
  52         Automatic clock Control
  53         Pending Break Enable
  54
  55
  56 Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
  57 Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
  58 L1 Data cache:
  59         Size: 8KB       Sectored, 4-way associative.
  60         line size=64 bytes.
  61 No L3 cache
  62 Instruction trace cache:
  63         Size: 12K uOps  8-way associative.
  64 L2 unified cache:
  65         Size: 512KB     Sectored, 8-way associative.
  66         line size=64 bytes.
  67
  68
  69 Number of reporting banks : 4
  70
  71 Number of extended MC registers : 12
  72
  73
  74 Bank: 0 (0x400)
  75 MC0CTL:    00000000 00000000 00000000 00000000
  76            00000000 00000000 00000000 00000000
  77 MC0STATUS: 00000000 00000000 00000000 00000000
  78            00000000 00000000 00000000 00000000
  79 MC0ADDR:   00000000 00000000 00000000 00000000
  80            00000000 00000000 00000000 00000000
  81
  82 Bank: 1 (0x404)
  83 MC1CTL:    00000000 00000000 00000000 00000000
  84            00000000 00000011 10000000 00000000
  85 MC1STATUS: 00000000 00000000 00000000 00000000
  86            00000000 00000000 00000000 00000000
  87 MC1ADDR:   00000000 00000000 00000000 00000000
  88            00000000 00000000 00000000 00000000
  89
  90 Bank: 2 (0x408)
  91 MC2CTL:    00000000 00000000 00000000 00000000
  92            00000000 00000000 00000000 10000000
  93 MC2STATUS: 00000000 00000000 00000000 00000000
  94            00000000 00000000 00000000 00000000
  95 MC2ADDR:   Couldn't read MSR 0x40a
  96
  97 Bank: 3 (0x40c)
  98 MC3CTL:    00000000 00000000 00000000 00000000
  99            00000000 00000000 00000000 01111110
 100 MC3STATUS: 00000000 00000000 00000000 00000000
 101            00000000 00000000 00000000 00000000
 102 MC3ADDR:   00000000 00000000 00000000 00000000
 103            00000000 00000000 00000000 00000000
 104
 105 Number of logical processors supported within the physical package: 2
 106
 107 Connector type: Socket478 (PGA478 Socket)
 108
 109 Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
 110         http://developer.intel.com/design/pentium4/datashts/29864304.pdf
 111 Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf
 112
 113 MTRR registers:
 114 MTRRcap (0xfe): 0x0000000000000508
 115 MTRRphysBase0 (0x200): 0x0000000000000006
 116 MTRRphysMask0 (0x201): 0x0000000ff0000800
 117 MTRRphysBase1 (0x202): 0x00000000e0000001
 118 MTRRphysMask1 (0x203): 0x0000000ffc000800
 119 MTRRphysBase2 (0x204): 0x0000000000000000
 120 MTRRphysMask2 (0x205): 0x0000000000000000
 121 MTRRphysBase3 (0x206): 0x0000000000000000
 122 MTRRphysMask3 (0x207): 0x0000000000000000
 123 MTRRphysBase4 (0x208): 0x0000000000000000
 124 MTRRphysMask4 (0x209): 0x0000000000000000
 125 MTRRphysBase5 (0x20a): 0x0000000000000000
 126 MTRRphysMask5 (0x20b): 0x0000000000000000
 127 MTRRphysBase6 (0x20c): 0x0000000000000000
 128 MTRRphysMask6 (0x20d): 0x0000000000000000
 129 MTRRphysBase7 (0x20e): 0x0000000000000000
 130 MTRRphysMask7 (0x20f): 0x0000000000000000
 131 MTRRfix64K_00000 (0x250): 0x0606060606060606
 132 MTRRfix16K_80000 (0x258): 0x0606060606060606
 133 MTRRfix16K_A0000 (0x259): 0x0000000000000000
 134 MTRRfix4K_C8000 (0x269): 0x0505050505050505
 135 MTRRfix4K_D0000 0x26a: 0x0000000000000000
 136 MTRRfix4K_D8000 0x26b: 0x0000000000000000
 137 MTRRfix4K_E0000 0x26c: 0x0505050505050505
 138 MTRRfix4K_E8000 0x26d: 0x0505050505050505
 139 MTRRfix4K_F0000 0x26e: 0x0505050505050505
 140 MTRRfix4K_F8000 0x26f: 0x0505050505050505
 141 MTRRdefType (0x2ff): 0x0000000000000c00
 142
 143
 144 2784.34 MHz processor (estimate).
 145
 146 CPU #2
 147 eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx = 49656e69
 148 eax in: 0x00000001, eax = 00000f27 ebx = 01020809 ecx = 00000400 edx = bfebfbff
 149 eax in: 0x00000002, eax = 665b5001 ebx = 00000000 ecx = 00000000 edx = 007b7040
 150
 151 eax in: 0x80000000, eax = 80000004 ebx = 00000000 ecx = 00000000 edx = 00000000
 152 eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
 153 eax in: 0x80000002, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
 154 eax in: 0x80000003, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
 155 eax in: 0x80000004, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 00000000
 156
 157 Family: 15 Model: 2 Stepping: 7 Type: 0
 158 CPU Model: Pentium 4 Xeon (Northwood) [C1] Original OEM
 159 Processor name string:
 160
 161 Feature flags:
 162         Onboard FPU
 163         Virtual Mode Extensions
 164         Debugging Extensions
 165         Page Size Extensions
 166         Time Stamp Counter
 167         Model-Specific Registers
 168         Physical Address Extensions
 169         Machine Check Architecture
 170         CMPXCHG8 instruction
 171         Onboard APIC
 172         SYSENTER/SYSEXIT
 173         Memory Type Range Registers
 174         Page Global Enable
 175         Machine Check Architecture
 176         CMOV instruction
 177         Page Attribute Table
 178         36-bit PSEs
 179         CLFLUSH instruction
 180         Debug Trace Store
 181         ACPI via MSR
 182         MMX support
 183         FXSAVE and FXRESTORE instructions
 184         SSE support
 185         SSE2 support
 186         CPU self snoop
 187         Hyper-Threading
 188         Automatic clock Control
 189         Pending Break Enable
 190
 191
 192 Instruction TLB: 4K, 2MB or 4MB pages, fully associative, 64 entries.
 193 Data TLB: 4KB or 4MB pages, fully associative, 64 entries.
 194 L1 Data cache:
 195         Size: 8KB       Sectored, 4-way associative.
 196         line size=64 bytes.
 197 No L3 cache
 198 Instruction trace cache:
 199         Size: 12K uOps  8-way associative.
 200 L2 unified cache:
 201         Size: 512KB     Sectored, 8-way associative.
 202         line size=64 bytes.
 203
 204
 205 Number of reporting banks : 4
 206
 207 Number of extended MC registers : 12
 208
 209
 210 Bank: 0 (0x400)
 211 MC0CTL:    00000000 00000000 00000000 00000000
 212            00000000 00000000 00000000 00000000
 213 MC0STATUS: 00000000 00000000 00000000 00000000
 214            00000000 00000000 00000000 00000000
 215 MC0ADDR:   00000000 00000000 00000000 00000000
 216            00000000 00000000 00000000 00000000
 217
 218 Bank: 1 (0x404)
 219 MC1CTL:    00000000 00000000 00000000 00000000
 220            00000000 00000011 10000000 00000000
 221 MC1STATUS: 00000000 00000000 00000000 00000000
 222            00000000 00000000 00000000 00000000
 223 MC1ADDR:   00000000 00000000 00000000 00000000
 224            00000000 00000000 00000000 00000000
 225
 226 Bank: 2 (0x408)
 227 MC2CTL:    00000000 00000000 00000000 00000000
 228            00000000 00000000 00000000 10000000
 229 MC2STATUS: 00000000 00000000 00000000 00000000
 230            00000000 00000000 00000000 00000000
 231 MC2ADDR:   Couldn't read MSR 0x40a
 232
 233 Bank: 3 (0x40c)
 234 MC3CTL:    00000000 00000000 00000000 00000000
 235            00000000 00000000 00000000 01111110
 236 MC3STATUS: 00000000 00000000 00000000 00000000
 237            00000000 00000000 00000000 00000000
 238 MC3ADDR:   00000000 00000000 00000000 00000000
 239            00000000 00000000 00000000 00000000
 240
 241 Number of logical processors supported within the physical package: 2
 242
 243 Connector type: Socket478 (PGA478 Socket)
 244
 245 Datasheet: http://developer.intel.com/design/pentium4/datashts/24988703.pdf
 246         http://developer.intel.com/design/pentium4/datashts/29864304.pdf
 247 Errata: http://developer.intel.com/design/pentium4/specupdt/24919928.pdf
 248
 249 MTRR registers:
 250 MTRRcap (0xfe): 0x0000000000000508
 251 MTRRphysBase0 (0x200): 0x0000000000000006
 252 MTRRphysMask0 (0x201): 0x0000000ff0000800
 253 MTRRphysBase1 (0x202): 0x00000000e0000001
 254 MTRRphysMask1 (0x203): 0x0000000ffc000800
 255 MTRRphysBase2 (0x204): 0x0000000000000000
 256 MTRRphysMask2 (0x205): 0x0000000000000000
 257 MTRRphysBase3 (0x206): 0x0000000000000000
 258 MTRRphysMask3 (0x207): 0x0000000000000000
 259 MTRRphysBase4 (0x208): 0x0000000000000000
 260 MTRRphysMask4 (0x209): 0x0000000000000000
 261 MTRRphysBase5 (0x20a): 0x0000000000000000
 262 MTRRphysMask5 (0x20b): 0x0000000000000000
 263 MTRRphysBase6 (0x20c): 0x0000000000000000
 264 MTRRphysMask6 (0x20d): 0x0000000000000000
 265 MTRRphysBase7 (0x20e): 0x0000000000000000
 266 MTRRphysMask7 (0x20f): 0x0000000000000000
 267 MTRRfix64K_00000 (0x250): 0x0606060606060606
 268 MTRRfix16K_80000 (0x258): 0x0606060606060606
 269 MTRRfix16K_A0000 (0x259): 0x0000000000000000
 270 MTRRfix4K_C8000 (0x269): 0x0505050505050505
 271 MTRRfix4K_D0000 0x26a: 0x0000000000000000
 272 MTRRfix4K_D8000 0x26b: 0x0000000000000000
 273 MTRRfix4K_E0000 0x26c: 0x0505050505050505
 274 MTRRfix4K_E8000 0x26d: 0x0505050505050505
 275 MTRRfix4K_F0000 0x26e: 0x0505050505050505
 276 MTRRfix4K_F8000 0x26f: 0x0505050505050505
 277 MTRRdefType (0x2ff): 0x0000000000000c00
 278
 279
 280 2784.36 MHz processor (estimate).
 281