2 * Copyright © 2011 Red Hat All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
27 * Jérôme Glisse <jglisse@redhat.com>
34 #include <sys/ioctl.h>
37 #include "radeon_drm.h"
38 #include "radeon_surface.h"
40 #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
41 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
42 #define MIN2(A, B) ((A) < (B) ? (A) : (B))
44 /* keep this private */
74 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
75 struct radeon_surface *surf);
76 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
77 struct radeon_surface *surf);
79 struct radeon_hw_info {
89 struct radeon_surface_manager {
92 struct radeon_hw_info hw_info;
94 hw_init_surface_t surface_init;
95 hw_best_surface_t surface_best;
99 static int radeon_get_value(int fd, unsigned req, uint32_t *value)
101 struct drm_radeon_info info = {};
106 info.value = (uintptr_t)value;
107 r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
108 sizeof(struct drm_radeon_info));
112 static int radeon_get_family(struct radeon_surface_manager *surf_man)
114 switch (surf_man->device_id) {
115 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break;
116 #include "r600_pci_ids.h"
124 static unsigned next_power_of_two(unsigned x)
129 return (1 << ((sizeof(unsigned) * 8) - __builtin_clz(x - 1)));
132 static unsigned mip_minify(unsigned size, unsigned level)
136 val = MAX2(1, size >> level);
138 val = next_power_of_two(val);
142 static void surf_minify(struct radeon_surface *surf,
144 uint32_t xalign, uint32_t yalign, uint32_t zalign,
147 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
148 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
149 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
150 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
151 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
152 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
153 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
154 if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) {
155 surf->level[level].mode = RADEON_SURF_MODE_1D;
159 surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign);
160 surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign);
161 surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign);
163 surf->level[level].offset = offset;
164 surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe;
165 surf->level[level].slice_size = surf->level[level].pitch_bytes * surf->level[level].nblk_y;
167 surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size;
170 /* ===========================================================================
173 static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
175 uint32_t tiling_config;
176 drmVersionPtr version;
179 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
185 surf_man->hw_info.allow_2d = 0;
186 version = drmGetVersion(surf_man->fd);
187 if (version && version->version_minor >= 14) {
188 surf_man->hw_info.allow_2d = 1;
191 switch ((tiling_config & 0xe) >> 1) {
193 surf_man->hw_info.num_pipes = 1;
196 surf_man->hw_info.num_pipes = 2;
199 surf_man->hw_info.num_pipes = 4;
202 surf_man->hw_info.num_pipes = 8;
208 switch ((tiling_config & 0x30) >> 4) {
210 surf_man->hw_info.num_banks = 4;
213 surf_man->hw_info.num_banks = 8;
219 switch ((tiling_config & 0xc0) >> 6) {
221 surf_man->hw_info.group_bytes = 256;
224 surf_man->hw_info.group_bytes = 512;
232 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
233 struct radeon_surface *surf,
234 uint64_t offset, unsigned start_level)
236 uint32_t xalign, yalign, zalign;
239 /* compute alignment */
241 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
243 /* the 32 alignment is for scanout, cb or db but to allow texture to be
244 * easily bound as such we force this alignment to all surface
246 xalign = MAX2(32, surf_man->hw_info.group_bytes / surf->bpe);
250 /* build mipmap tree */
251 for (i = start_level; i <= surf->last_level; i++) {
252 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
253 surf_minify(surf, i, xalign, yalign, zalign, offset);
254 /* level0 and first mipmap need to have alignment */
255 offset = surf->bo_size;
257 offset = ALIGN(offset, surf->bo_alignment);
263 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
264 struct radeon_surface *surf,
265 uint64_t offset, unsigned start_level)
267 uint32_t xalign, yalign, zalign;
270 /* compute alignment */
272 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
274 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
278 /* build mipmap tree */
279 for (i = start_level; i <= surf->last_level; i++) {
280 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
281 surf_minify(surf, i, xalign, yalign, zalign, offset);
282 /* level0 and first mipmap need to have alignment */
283 offset = surf->bo_size;
285 offset = ALIGN(offset, surf->bo_alignment);
291 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
292 struct radeon_surface *surf,
293 uint64_t offset, unsigned start_level)
295 uint32_t xalign, yalign, zalign, tilew;
298 /* compute alignment */
300 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
301 xalign = MAX2(tilew, xalign);
305 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
308 /* build mipmap tree */
309 for (i = start_level; i <= surf->last_level; i++) {
310 surf->level[i].mode = RADEON_SURF_MODE_1D;
311 surf_minify(surf, i, xalign, yalign, zalign, offset);
312 /* level0 and first mipmap need to have alignment */
313 offset = surf->bo_size;
315 offset = ALIGN(offset, surf->bo_alignment);
321 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
322 struct radeon_surface *surf,
323 uint64_t offset, unsigned start_level)
325 uint32_t xalign, yalign, zalign, tilew;
328 /* compute alignment */
331 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
332 (tilew * surf->bpe * surf->nsamples);
333 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
334 yalign = tilew * surf_man->hw_info.num_pipes;
337 MAX2(surf_man->hw_info.num_pipes *
338 surf_man->hw_info.num_banks *
340 xalign * yalign * surf->nsamples * surf->bpe);
343 /* build mipmap tree */
344 for (i = start_level; i <= surf->last_level; i++) {
345 surf->level[i].mode = RADEON_SURF_MODE_2D;
346 surf_minify(surf, i, xalign, yalign, zalign, offset);
347 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
348 return r6_surface_init_1d(surf_man, surf, offset, i);
350 /* level0 and first mipmap need to have alignment */
351 offset = surf->bo_size;
353 offset = ALIGN(offset, surf->bo_alignment);
359 static int r6_surface_init(struct radeon_surface_manager *surf_man,
360 struct radeon_surface *surf)
366 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
368 /* force 1d on kernel that can't do 2d */
369 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
370 mode = RADEON_SURF_MODE_1D;
371 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
372 surf->flags |= RADEON_SURF_SET(mode, MODE);
375 /* check surface dimension */
376 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
380 /* check mipmap last_level */
381 if (surf->last_level > 14) {
385 /* check tiling mode */
387 case RADEON_SURF_MODE_LINEAR:
388 r = r6_surface_init_linear(surf_man, surf, 0, 0);
390 case RADEON_SURF_MODE_LINEAR_ALIGNED:
391 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
393 case RADEON_SURF_MODE_1D:
394 r = r6_surface_init_1d(surf_man, surf, 0, 0);
396 case RADEON_SURF_MODE_2D:
397 r = r6_surface_init_2d(surf_man, surf, 0, 0);
405 static int r6_surface_best(struct radeon_surface_manager *surf_man,
406 struct radeon_surface *surf)
408 /* no value to optimize for r6xx/r7xx */
413 /* ===========================================================================
416 static int eg_init_hw_info(struct radeon_surface_manager *surf_man)
418 uint32_t tiling_config;
419 drmVersionPtr version;
422 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
428 surf_man->hw_info.allow_2d = 0;
429 version = drmGetVersion(surf_man->fd);
430 if (version && version->version_minor >= 14) {
431 surf_man->hw_info.allow_2d = 1;
434 switch (tiling_config & 0xf) {
436 surf_man->hw_info.num_pipes = 1;
439 surf_man->hw_info.num_pipes = 2;
442 surf_man->hw_info.num_pipes = 4;
445 surf_man->hw_info.num_pipes = 8;
451 switch ((tiling_config & 0xf0) >> 4) {
453 surf_man->hw_info.num_banks = 4;
456 surf_man->hw_info.num_banks = 8;
459 surf_man->hw_info.num_banks = 16;
465 switch ((tiling_config & 0xf00) >> 8) {
467 surf_man->hw_info.group_bytes = 256;
470 surf_man->hw_info.group_bytes = 512;
476 switch ((tiling_config & 0xf000) >> 12) {
478 surf_man->hw_info.row_size = 1024;
481 surf_man->hw_info.row_size = 2048;
484 surf_man->hw_info.row_size = 4096;
492 static void eg_surf_minify(struct radeon_surface *surf,
500 unsigned mtile_pr, mtile_ps;
502 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
503 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
504 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
505 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
506 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
507 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
508 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
509 if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) {
510 surf->level[level].mode = RADEON_SURF_MODE_1D;
514 surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew);
515 surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh);
516 surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1);
518 /* macro tile per row */
519 mtile_pr = surf->level[level].nblk_x / mtilew;
520 /* macro tile per slice */
521 mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh;
523 surf->level[level].offset = offset;
524 surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * slice_pt;
525 surf->level[level].slice_size = mtile_ps * mtileb * slice_pt;
527 surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size;
530 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
531 struct radeon_surface *surf,
532 uint64_t offset, unsigned start_level)
534 uint32_t xalign, yalign, zalign, tilew;
537 /* compute alignment */
539 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
540 if (surf->flags & RADEON_SURF_SBUFFER) {
541 surf->stencil_offset = 0;
542 surf->stencil_tile_split = 0;
543 xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples);
545 xalign = MAX2(tilew, xalign);
549 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
552 /* build mipmap tree */
553 for (i = start_level; i <= surf->last_level; i++) {
554 surf->level[i].mode = RADEON_SURF_MODE_1D;
555 surf_minify(surf, i, xalign, yalign, zalign, offset);
556 /* level0 and first mipmap need to have alignment */
557 offset = surf->bo_size;
559 offset = ALIGN(offset, surf->bo_alignment);
563 if (surf->flags & RADEON_SURF_SBUFFER) {
564 surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
565 surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
571 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
572 struct radeon_surface *surf,
573 uint64_t offset, unsigned start_level)
575 unsigned tilew, tileh, tileb;
576 unsigned mtilew, mtileh, mtileb;
580 surf->stencil_offset = 0;
581 /* compute tile values */
584 tileb = tilew * tileh * surf->bpe * surf->nsamples;
585 /* slices per tile */
587 if (tileb > surf->tile_split) {
588 slice_pt = tileb / surf->tile_split;
590 tileb = tileb / slice_pt;
592 /* macro tile width & height */
593 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
594 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
595 /* macro tile bytes */
596 mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
599 surf->bo_alignment = MAX2(256, mtileb);
602 /* build mipmap tree */
603 for (i = start_level; i <= surf->last_level; i++) {
604 surf->level[i].mode = RADEON_SURF_MODE_2D;
605 eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset);
606 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
607 return eg_surface_init_1d(surf_man, surf, offset, i);
609 /* level0 and first mipmap need to have alignment */
610 offset = surf->bo_size;
612 offset = ALIGN(offset, surf->bo_alignment);
616 if (surf->flags & RADEON_SURF_SBUFFER) {
617 surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
618 surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
624 static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
625 struct radeon_surface *surf,
630 /* check surface dimension */
631 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
635 /* check mipmap last_level */
636 if (surf->last_level > 15) {
640 /* force 1d on kernel that can't do 2d */
641 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
642 mode = RADEON_SURF_MODE_1D;
643 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
644 surf->flags |= RADEON_SURF_SET(mode, MODE);
647 /* check tile split */
648 if (mode == RADEON_SURF_MODE_2D) {
649 switch (surf->tile_split) {
661 switch (surf->mtilea) {
670 /* check aspect ratio */
671 if (surf_man->hw_info.num_banks < surf->mtilea) {
674 /* check bank width */
675 switch (surf->bankw) {
684 /* check bank height */
685 switch (surf->bankh) {
694 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
695 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
703 static int eg_surface_init(struct radeon_surface_manager *surf_man,
704 struct radeon_surface *surf)
710 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
712 /* for some reason eg need to have room for stencil right after depth */
713 if (surf->flags & RADEON_SURF_ZBUFFER) {
714 surf->flags |= RADEON_SURF_SBUFFER;
717 r = eg_surface_sanity(surf_man, surf, mode);
722 /* check tiling mode */
724 case RADEON_SURF_MODE_LINEAR:
725 r = r6_surface_init_linear(surf_man, surf, 0, 0);
727 case RADEON_SURF_MODE_LINEAR_ALIGNED:
728 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
730 case RADEON_SURF_MODE_1D:
731 r = eg_surface_init_1d(surf_man, surf, 0, 0);
733 case RADEON_SURF_MODE_2D:
734 r = eg_surface_init_2d(surf_man, surf, 0, 0);
742 static unsigned log2_int(unsigned x)
750 if ((unsigned)(1 << l) > x) {
757 /* compute best tile_split, bankw, bankh, mtilea
758 * depending on surface
760 static int eg_surface_best(struct radeon_surface_manager *surf_man,
761 struct radeon_surface *surf)
763 unsigned mode, tileb, h_over_w;
767 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
769 /* for some reason eg need to have room for stencil right after depth */
770 if (surf->flags & RADEON_SURF_ZBUFFER) {
771 surf->flags |= RADEON_SURF_SBUFFER;
774 /* set some default value to avoid sanity check choking on them */
775 surf->tile_split = 1024;
778 surf->mtilea = surf_man->hw_info.num_banks;
779 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
780 for (; surf->bankh <= 8; surf->bankh *= 2) {
781 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
785 if (surf->mtilea > 8) {
789 r = eg_surface_sanity(surf_man, surf, mode);
794 if (mode != RADEON_SURF_MODE_2D) {
795 /* nothing to do for non 2D tiled surface */
799 /* set tile split to row size, optimize latter for multi-sample surface
800 * tile split >= 256 for render buffer surface. Also depth surface want
801 * smaller value for optimal performances.
803 surf->tile_split = surf_man->hw_info.row_size;
804 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
806 /* bankw or bankh greater than 1 increase alignment requirement, not
807 * sure if it's worth using smaller bankw & bankh to stick with 2D
808 * tiling on small surface rather than falling back to 1D tiling.
809 * Use recommanded value based on tile size for now.
811 * fmask buffer has different optimal value figure them out once we
814 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
815 /* assume 1 bytes for stencil, we optimize for stencil as stencil
816 * and depth shares surface values
818 tileb = MIN2(surf->tile_split, 64 * surf->nsamples);
820 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
823 /* use bankw of 1 to minimize width alignment, might be interesting to
824 * increase it for large surface
839 /* double check the constraint */
840 for (; surf->bankh <= 8; surf->bankh *= 2) {
841 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
846 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
847 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
848 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
854 /* ===========================================================================
857 struct radeon_surface_manager *radeon_surface_manager_new(int fd)
859 struct radeon_surface_manager *surf_man;
861 surf_man = calloc(1, sizeof(struct radeon_surface_manager));
862 if (surf_man == NULL) {
866 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) {
869 if (radeon_get_family(surf_man)) {
873 if (surf_man->family <= CHIP_RV740) {
874 if (r6_init_hw_info(surf_man)) {
877 surf_man->surface_init = &r6_surface_init;
878 surf_man->surface_best = &r6_surface_best;
880 if (eg_init_hw_info(surf_man)) {
883 surf_man->surface_init = &eg_surface_init;
884 surf_man->surface_best = &eg_surface_best;
893 void radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
898 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
899 struct radeon_surface *surf,
903 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
907 /* all dimension must be at least 1 ! */
908 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
911 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
914 if (!surf->array_size) {
917 /* array size must be a power of 2 */
918 surf->array_size = next_power_of_two(surf->array_size);
920 switch (surf->nsamples) {
931 case RADEON_SURF_TYPE_1D:
932 if (surf->npix_y > 1) {
935 case RADEON_SURF_TYPE_2D:
936 if (surf->npix_z > 1) {
940 case RADEON_SURF_TYPE_CUBEMAP:
941 if (surf->npix_z > 1) {
944 /* deal with cubemap as they were texture array */
945 if (surf_man->family >= CHIP_RV770) {
946 surf->array_size = 8;
948 surf->array_size = 6;
951 case RADEON_SURF_TYPE_3D:
953 case RADEON_SURF_TYPE_1D_ARRAY:
954 if (surf->npix_y > 1) {
957 case RADEON_SURF_TYPE_2D_ARRAY:
965 int radeon_surface_init(struct radeon_surface_manager *surf_man,
966 struct radeon_surface *surf)
971 type = RADEON_SURF_GET(surf->flags, TYPE);
972 mode = RADEON_SURF_GET(surf->flags, MODE);
974 r = radeon_surface_sanity(surf_man, surf, type, mode);
978 return surf_man->surface_init(surf_man, surf);
981 int radeon_surface_best(struct radeon_surface_manager *surf_man,
982 struct radeon_surface *surf)
987 type = RADEON_SURF_GET(surf->flags, TYPE);
988 mode = RADEON_SURF_GET(surf->flags, MODE);
990 r = radeon_surface_sanity(surf_man, surf, type, mode);
994 return surf_man->surface_best(surf_man, surf);