2 * Copyright © 2011 Red Hat All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
27 * Jérôme Glisse <jglisse@redhat.com>
34 #include <sys/ioctl.h>
37 #include "radeon_drm.h"
38 #include "radeon_surface.h"
40 #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
41 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
42 #define MIN2(A, B) ((A) < (B) ? (A) : (B))
44 /* keep this private */
78 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
79 struct radeon_surface *surf);
80 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
81 struct radeon_surface *surf);
83 struct radeon_hw_info {
93 struct radeon_surface_manager {
96 struct radeon_hw_info hw_info;
98 hw_init_surface_t surface_init;
99 hw_best_surface_t surface_best;
103 static int radeon_get_value(int fd, unsigned req, uint32_t *value)
105 struct drm_radeon_info info = {};
110 info.value = (uintptr_t)value;
111 r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
112 sizeof(struct drm_radeon_info));
116 static int radeon_get_family(struct radeon_surface_manager *surf_man)
118 switch (surf_man->device_id) {
119 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break;
120 #include "r600_pci_ids.h"
128 static unsigned next_power_of_two(unsigned x)
133 return (1 << ((sizeof(unsigned) * 8) - __builtin_clz(x - 1)));
136 static unsigned mip_minify(unsigned size, unsigned level)
140 val = MAX2(1, size >> level);
142 val = next_power_of_two(val);
146 static void surf_minify(struct radeon_surface *surf,
148 uint32_t xalign, uint32_t yalign, uint32_t zalign,
151 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
152 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
153 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
154 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
155 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
156 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
157 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
158 if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) {
159 surf->level[level].mode = RADEON_SURF_MODE_1D;
163 surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign);
164 surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign);
165 surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign);
167 surf->level[level].offset = offset;
168 surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe;
169 surf->level[level].slice_size = surf->level[level].pitch_bytes * surf->level[level].nblk_y;
171 surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size;
174 /* ===========================================================================
177 static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
179 uint32_t tiling_config;
180 drmVersionPtr version;
183 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
189 surf_man->hw_info.allow_2d = 0;
190 version = drmGetVersion(surf_man->fd);
191 if (version && version->version_minor >= 14) {
192 surf_man->hw_info.allow_2d = 1;
194 drmFreeVersion(version);
196 switch ((tiling_config & 0xe) >> 1) {
198 surf_man->hw_info.num_pipes = 1;
201 surf_man->hw_info.num_pipes = 2;
204 surf_man->hw_info.num_pipes = 4;
207 surf_man->hw_info.num_pipes = 8;
210 surf_man->hw_info.num_pipes = 8;
211 surf_man->hw_info.allow_2d = 0;
215 switch ((tiling_config & 0x30) >> 4) {
217 surf_man->hw_info.num_banks = 4;
220 surf_man->hw_info.num_banks = 8;
223 surf_man->hw_info.num_banks = 8;
224 surf_man->hw_info.allow_2d = 0;
228 switch ((tiling_config & 0xc0) >> 6) {
230 surf_man->hw_info.group_bytes = 256;
233 surf_man->hw_info.group_bytes = 512;
236 surf_man->hw_info.group_bytes = 256;
237 surf_man->hw_info.allow_2d = 0;
243 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man,
244 struct radeon_surface *surf,
245 uint64_t offset, unsigned start_level)
247 uint32_t xalign, yalign, zalign;
250 /* compute alignment */
252 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
254 /* the 32 alignment is for scanout, cb or db but to allow texture to be
255 * easily bound as such we force this alignment to all surface
257 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
260 if (surf->flags & RADEON_SURF_SCANOUT) {
261 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
264 /* build mipmap tree */
265 for (i = start_level; i <= surf->last_level; i++) {
266 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
267 surf_minify(surf, i, xalign, yalign, zalign, offset);
268 /* level0 and first mipmap need to have alignment */
269 offset = surf->bo_size;
271 offset = ALIGN(offset, surf->bo_alignment);
277 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man,
278 struct radeon_surface *surf,
279 uint64_t offset, unsigned start_level)
281 uint32_t xalign, yalign, zalign;
284 /* compute alignment */
286 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
288 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
292 /* build mipmap tree */
293 for (i = start_level; i <= surf->last_level; i++) {
294 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
295 surf_minify(surf, i, xalign, yalign, zalign, offset);
296 /* level0 and first mipmap need to have alignment */
297 offset = surf->bo_size;
299 offset = ALIGN(offset, surf->bo_alignment);
305 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man,
306 struct radeon_surface *surf,
307 uint64_t offset, unsigned start_level)
309 uint32_t xalign, yalign, zalign, tilew;
312 /* compute alignment */
314 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
315 xalign = MAX2(tilew, xalign);
318 if (surf->flags & RADEON_SURF_SCANOUT) {
319 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
322 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
325 /* build mipmap tree */
326 for (i = start_level; i <= surf->last_level; i++) {
327 surf->level[i].mode = RADEON_SURF_MODE_1D;
328 surf_minify(surf, i, xalign, yalign, zalign, offset);
329 /* level0 and first mipmap need to have alignment */
330 offset = surf->bo_size;
332 offset = ALIGN(offset, surf->bo_alignment);
338 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
339 struct radeon_surface *surf,
340 uint64_t offset, unsigned start_level)
342 uint32_t xalign, yalign, zalign, tilew;
345 /* compute alignment */
348 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
349 (tilew * surf->bpe * surf->nsamples);
350 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
351 yalign = tilew * surf_man->hw_info.num_pipes;
352 if (surf->flags & RADEON_SURF_SCANOUT) {
353 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
357 MAX2(surf_man->hw_info.num_pipes *
358 surf_man->hw_info.num_banks *
360 xalign * yalign * surf->nsamples * surf->bpe);
363 /* build mipmap tree */
364 for (i = start_level; i <= surf->last_level; i++) {
365 surf->level[i].mode = RADEON_SURF_MODE_2D;
366 surf_minify(surf, i, xalign, yalign, zalign, offset);
367 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
368 return r6_surface_init_1d(surf_man, surf, offset, i);
370 /* level0 and first mipmap need to have alignment */
371 offset = surf->bo_size;
373 offset = ALIGN(offset, surf->bo_alignment);
379 static int r6_surface_init(struct radeon_surface_manager *surf_man,
380 struct radeon_surface *surf)
386 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
388 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
389 /* zbuffer only support 1D or 2D tiled surface */
391 case RADEON_SURF_MODE_1D:
392 case RADEON_SURF_MODE_2D:
395 mode = RADEON_SURF_MODE_1D;
396 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
397 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
402 /* force 1d on kernel that can't do 2d */
403 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
404 mode = RADEON_SURF_MODE_1D;
405 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
406 surf->flags |= RADEON_SURF_SET(mode, MODE);
409 /* check surface dimension */
410 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
414 /* check mipmap last_level */
415 if (surf->last_level > 14) {
419 /* check tiling mode */
421 case RADEON_SURF_MODE_LINEAR:
422 r = r6_surface_init_linear(surf_man, surf, 0, 0);
424 case RADEON_SURF_MODE_LINEAR_ALIGNED:
425 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
427 case RADEON_SURF_MODE_1D:
428 r = r6_surface_init_1d(surf_man, surf, 0, 0);
430 case RADEON_SURF_MODE_2D:
431 r = r6_surface_init_2d(surf_man, surf, 0, 0);
439 static int r6_surface_best(struct radeon_surface_manager *surf_man,
440 struct radeon_surface *surf)
442 /* no value to optimize for r6xx/r7xx */
447 /* ===========================================================================
450 static int eg_init_hw_info(struct radeon_surface_manager *surf_man)
452 uint32_t tiling_config;
453 drmVersionPtr version;
456 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
462 surf_man->hw_info.allow_2d = 0;
463 version = drmGetVersion(surf_man->fd);
464 if (version && version->version_minor >= 16) {
465 surf_man->hw_info.allow_2d = 1;
467 drmFreeVersion(version);
469 switch (tiling_config & 0xf) {
471 surf_man->hw_info.num_pipes = 1;
474 surf_man->hw_info.num_pipes = 2;
477 surf_man->hw_info.num_pipes = 4;
480 surf_man->hw_info.num_pipes = 8;
483 surf_man->hw_info.num_pipes = 8;
484 surf_man->hw_info.allow_2d = 0;
488 switch ((tiling_config & 0xf0) >> 4) {
490 surf_man->hw_info.num_banks = 4;
493 surf_man->hw_info.num_banks = 8;
496 surf_man->hw_info.num_banks = 16;
499 surf_man->hw_info.num_banks = 8;
500 surf_man->hw_info.allow_2d = 0;
504 switch ((tiling_config & 0xf00) >> 8) {
506 surf_man->hw_info.group_bytes = 256;
509 surf_man->hw_info.group_bytes = 512;
512 surf_man->hw_info.group_bytes = 256;
513 surf_man->hw_info.allow_2d = 0;
517 switch ((tiling_config & 0xf000) >> 12) {
519 surf_man->hw_info.row_size = 1024;
522 surf_man->hw_info.row_size = 2048;
525 surf_man->hw_info.row_size = 4096;
528 surf_man->hw_info.row_size = 4096;
529 surf_man->hw_info.allow_2d = 0;
535 static void eg_surf_minify(struct radeon_surface *surf,
543 unsigned mtile_pr, mtile_ps;
545 surf->level[level].npix_x = mip_minify(surf->npix_x, level);
546 surf->level[level].npix_y = mip_minify(surf->npix_y, level);
547 surf->level[level].npix_z = mip_minify(surf->npix_z, level);
548 surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
549 surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
550 surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
551 if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
552 if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) {
553 surf->level[level].mode = RADEON_SURF_MODE_1D;
557 surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew);
558 surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh);
559 surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1);
561 /* macro tile per row */
562 mtile_pr = surf->level[level].nblk_x / mtilew;
563 /* macro tile per slice */
564 mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh;
566 surf->level[level].offset = offset;
567 surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * slice_pt;
568 surf->level[level].slice_size = mtile_ps * mtileb * slice_pt;
570 surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size;
573 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
574 struct radeon_surface *surf,
575 uint64_t offset, unsigned start_level)
577 uint32_t xalign, yalign, zalign, tilew;
580 /* compute alignment */
582 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
583 if (surf->flags & RADEON_SURF_SBUFFER) {
584 xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples);
586 xalign = MAX2(tilew, xalign);
589 if (surf->flags & RADEON_SURF_SCANOUT) {
590 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
593 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
596 /* build mipmap tree */
597 for (i = start_level; i <= surf->last_level; i++) {
598 surf->level[i].mode = RADEON_SURF_MODE_1D;
599 surf_minify(surf, i, xalign, yalign, zalign, offset);
600 /* level0 and first mipmap need to have alignment */
601 offset = surf->bo_size;
603 offset = ALIGN(offset, surf->bo_alignment);
607 /* The depth and stencil buffers are in separate resources on evergreen.
608 * We allocate them in one buffer next to each other to simplify
609 * communication between the DDX and the Mesa driver. */
610 if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
611 (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
612 surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
613 surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
619 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
620 struct radeon_surface *surf,
621 uint64_t offset, unsigned start_level)
623 unsigned tilew, tileh, tileb;
624 unsigned mtilew, mtileh, mtileb;
628 /* compute tile values */
631 tileb = tilew * tileh * surf->bpe * surf->nsamples;
632 /* slices per tile */
634 if (tileb > surf->tile_split) {
635 slice_pt = tileb / surf->tile_split;
637 tileb = tileb / slice_pt;
639 /* macro tile width & height */
640 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
641 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
642 /* macro tile bytes */
643 mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
646 surf->bo_alignment = MAX2(256, mtileb);
649 /* build mipmap tree */
650 for (i = start_level; i <= surf->last_level; i++) {
651 surf->level[i].mode = RADEON_SURF_MODE_2D;
652 eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset);
653 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
654 return eg_surface_init_1d(surf_man, surf, offset, i);
656 /* level0 and first mipmap need to have alignment */
657 offset = surf->bo_size;
659 offset = ALIGN(offset, surf->bo_alignment);
663 if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
664 (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
665 surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
666 surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
672 static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
673 struct radeon_surface *surf,
678 /* check surface dimension */
679 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
683 /* check mipmap last_level */
684 if (surf->last_level > 15) {
688 /* force 1d on kernel that can't do 2d */
689 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
690 mode = RADEON_SURF_MODE_1D;
691 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
692 surf->flags |= RADEON_SURF_SET(mode, MODE);
695 /* check tile split */
696 if (mode == RADEON_SURF_MODE_2D) {
697 switch (surf->tile_split) {
709 switch (surf->mtilea) {
718 /* check aspect ratio */
719 if (surf_man->hw_info.num_banks < surf->mtilea) {
722 /* check bank width */
723 switch (surf->bankw) {
732 /* check bank height */
733 switch (surf->bankh) {
742 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
743 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
751 static int eg_surface_init(struct radeon_surface_manager *surf_man,
752 struct radeon_surface *surf)
758 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
760 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
761 /* zbuffer only support 1D or 2D tiled surface */
763 case RADEON_SURF_MODE_1D:
764 case RADEON_SURF_MODE_2D:
767 mode = RADEON_SURF_MODE_1D;
768 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
769 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
774 r = eg_surface_sanity(surf_man, surf, mode);
779 surf->stencil_offset = 0;
780 surf->stencil_tile_split = 0;
782 /* check tiling mode */
784 case RADEON_SURF_MODE_LINEAR:
785 r = r6_surface_init_linear(surf_man, surf, 0, 0);
787 case RADEON_SURF_MODE_LINEAR_ALIGNED:
788 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
790 case RADEON_SURF_MODE_1D:
791 r = eg_surface_init_1d(surf_man, surf, 0, 0);
793 case RADEON_SURF_MODE_2D:
794 r = eg_surface_init_2d(surf_man, surf, 0, 0);
802 static unsigned log2_int(unsigned x)
810 if ((unsigned)(1 << l) > x) {
817 /* compute best tile_split, bankw, bankh, mtilea
818 * depending on surface
820 static int eg_surface_best(struct radeon_surface_manager *surf_man,
821 struct radeon_surface *surf)
823 unsigned mode, tileb, h_over_w;
827 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
829 /* set some default value to avoid sanity check choking on them */
830 surf->tile_split = 1024;
833 surf->mtilea = surf_man->hw_info.num_banks;
834 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
835 for (; surf->bankh <= 8; surf->bankh *= 2) {
836 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
840 if (surf->mtilea > 8) {
844 r = eg_surface_sanity(surf_man, surf, mode);
849 if (mode != RADEON_SURF_MODE_2D) {
850 /* nothing to do for non 2D tiled surface */
854 /* set tile split to row size, optimize latter for multi-sample surface
855 * tile split >= 256 for render buffer surface. Also depth surface want
856 * smaller value for optimal performances.
858 surf->tile_split = surf_man->hw_info.row_size;
859 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
861 /* bankw or bankh greater than 1 increase alignment requirement, not
862 * sure if it's worth using smaller bankw & bankh to stick with 2D
863 * tiling on small surface rather than falling back to 1D tiling.
864 * Use recommanded value based on tile size for now.
866 * fmask buffer has different optimal value figure them out once we
869 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
870 /* assume 1 bytes for stencil, we optimize for stencil as stencil
871 * and depth shares surface values
873 tileb = MIN2(surf->tile_split, 64 * surf->nsamples);
875 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
878 /* use bankw of 1 to minimize width alignment, might be interesting to
879 * increase it for large surface
894 /* double check the constraint */
895 for (; surf->bankh <= 8; surf->bankh *= 2) {
896 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
901 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
902 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
903 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
909 /* ===========================================================================
912 struct radeon_surface_manager *radeon_surface_manager_new(int fd)
914 struct radeon_surface_manager *surf_man;
916 surf_man = calloc(1, sizeof(struct radeon_surface_manager));
917 if (surf_man == NULL) {
921 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) {
924 if (radeon_get_family(surf_man)) {
928 if (surf_man->family <= CHIP_RV740) {
929 if (r6_init_hw_info(surf_man)) {
932 surf_man->surface_init = &r6_surface_init;
933 surf_man->surface_best = &r6_surface_best;
935 if (eg_init_hw_info(surf_man)) {
938 surf_man->surface_init = &eg_surface_init;
939 surf_man->surface_best = &eg_surface_best;
948 void radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
953 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
954 struct radeon_surface *surf,
958 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
962 /* all dimension must be at least 1 ! */
963 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
966 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
969 if (!surf->array_size) {
972 /* array size must be a power of 2 */
973 surf->array_size = next_power_of_two(surf->array_size);
975 switch (surf->nsamples) {
986 case RADEON_SURF_TYPE_1D:
987 if (surf->npix_y > 1) {
990 case RADEON_SURF_TYPE_2D:
991 if (surf->npix_z > 1) {
995 case RADEON_SURF_TYPE_CUBEMAP:
996 if (surf->npix_z > 1) {
999 /* deal with cubemap as they were texture array */
1000 if (surf_man->family >= CHIP_RV770) {
1001 surf->array_size = 8;
1003 surf->array_size = 6;
1006 case RADEON_SURF_TYPE_3D:
1008 case RADEON_SURF_TYPE_1D_ARRAY:
1009 if (surf->npix_y > 1) {
1012 case RADEON_SURF_TYPE_2D_ARRAY:
1020 int radeon_surface_init(struct radeon_surface_manager *surf_man,
1021 struct radeon_surface *surf)
1023 unsigned mode, type;
1026 type = RADEON_SURF_GET(surf->flags, TYPE);
1027 mode = RADEON_SURF_GET(surf->flags, MODE);
1029 r = radeon_surface_sanity(surf_man, surf, type, mode);
1033 return surf_man->surface_init(surf_man, surf);
1036 int radeon_surface_best(struct radeon_surface_manager *surf_man,
1037 struct radeon_surface *surf)
1039 unsigned mode, type;
1042 type = RADEON_SURF_GET(surf->flags, TYPE);
1043 mode = RADEON_SURF_GET(surf->flags, MODE);
1045 r = radeon_surface_sanity(surf_man, surf, type, mode);
1049 return surf_man->surface_best(surf_man, surf);