2 * Copyright © 2008 Dave Airlie
3 * Copyright © 2008 Jérôme Glisse
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
30 * Jérôme Glisse <glisse@freedesktop.org>
43 #include "radeon_drm.h"
44 #include "radeon_bo.h"
45 #include "radeon_bo_gem.h"
47 struct radeon_bo_gem {
48 struct radeon_bo base;
54 struct bo_manager_gem {
55 struct radeon_bo_manager base;
58 static int bo_wait(struct radeon_bo *bo);
60 static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
67 struct radeon_bo_gem *bo;
70 bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
78 bo->base.alignment = alignment;
79 bo->base.domains = domains;
80 bo->base.flags = flags;
84 struct drm_gem_open open_arg;
86 memset(&open_arg, 0, sizeof(open_arg));
87 open_arg.name = handle;
88 r = drmIoctl(bom->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
93 bo->base.handle = open_arg.handle;
94 bo->base.size = open_arg.size;
97 struct drm_radeon_gem_create args;
100 args.alignment = alignment;
101 args.initial_domain = bo->base.domains;
104 r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
105 &args, sizeof(args));
106 bo->base.handle = args.handle;
108 fprintf(stderr, "Failed to allocate :\n");
109 fprintf(stderr, " size : %d bytes\n", size);
110 fprintf(stderr, " alignment : %d bytes\n", alignment);
111 fprintf(stderr, " domains : %d\n", bo->base.domains);
116 radeon_bo_ref((struct radeon_bo*)bo);
117 return (struct radeon_bo*)bo;
120 static void bo_ref(struct radeon_bo *bo)
124 static struct radeon_bo *bo_unref(struct radeon_bo *bo)
126 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
127 struct drm_gem_close args;
135 if (bo_gem->priv_ptr) {
136 munmap(bo_gem->priv_ptr, bo->size);
139 /* Zero out args to make valgrind happy */
140 memset(&args, 0, sizeof(args));
143 args.handle = bo->handle;
144 drmIoctl(bo->bom->fd, DRM_IOCTL_GEM_CLOSE, &args);
145 memset(bo_gem, 0, sizeof(struct radeon_bo_gem));
150 static int bo_map(struct radeon_bo *bo, int write)
152 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
153 struct drm_radeon_gem_mmap args;
157 if (bo_gem->map_count++ != 0) {
160 if (bo_gem->priv_ptr) {
166 /* Zero out args to make valgrind happy */
167 memset(&args, 0, sizeof(args));
168 args.handle = bo->handle;
170 args.size = (uint64_t)bo->size;
171 r = drmCommandWriteRead(bo->bom->fd,
176 fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
180 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, bo->bom->fd, args.addr_ptr);
181 if (ptr == MAP_FAILED)
183 bo_gem->priv_ptr = ptr;
185 bo->ptr = bo_gem->priv_ptr;
192 static int bo_unmap(struct radeon_bo *bo)
194 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
196 if (--bo_gem->map_count > 0) {
199 //munmap(bo->ptr, bo->size);
204 static int bo_wait(struct radeon_bo *bo)
206 struct drm_radeon_gem_wait_idle args;
209 /* Zero out args to make valgrind happy */
210 memset(&args, 0, sizeof(args));
211 args.handle = bo->handle;
213 ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
214 &args, sizeof(args));
215 } while (ret == -EBUSY);
219 static int bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
221 struct drm_radeon_gem_busy args;
224 args.handle = bo->handle;
227 ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_BUSY,
228 &args, sizeof(args));
230 *domain = args.domain;
234 static int bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags,
237 struct drm_radeon_gem_set_tiling args;
240 args.handle = bo->handle;
241 args.tiling_flags = tiling_flags;
244 r = drmCommandWriteRead(bo->bom->fd,
245 DRM_RADEON_GEM_SET_TILING,
251 static int bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags,
254 struct drm_radeon_gem_set_tiling args;
257 args.handle = bo->handle;
259 r = drmCommandWriteRead(bo->bom->fd,
260 DRM_RADEON_GEM_GET_TILING,
267 *tiling_flags = args.tiling_flags;
272 static struct radeon_bo_funcs bo_gem_funcs = {
285 struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
287 struct bo_manager_gem *bomg;
289 bomg = (struct bo_manager_gem*)calloc(1, sizeof(struct bo_manager_gem));
293 bomg->base.funcs = &bo_gem_funcs;
295 return (struct radeon_bo_manager*)bomg;
298 void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom)
300 struct bo_manager_gem *bomg = (struct bo_manager_gem*)bom;
308 uint32_t radeon_gem_name_bo(struct radeon_bo *bo)
310 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
314 int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
316 struct drm_gem_flink flink;
319 flink.handle = bo->handle;
320 r = drmIoctl(bo->bom->fd, DRM_IOCTL_GEM_FLINK, &flink);
328 int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
330 struct drm_radeon_gem_set_domain args;
333 args.handle = bo->handle;
334 args.read_domains = read_domains;
335 args.write_domain = write_domain;
337 r = drmCommandWriteRead(bo->bom->fd,
338 DRM_RADEON_GEM_SET_DOMAIN,