4 * Copyright IBM, Corp. 2011
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include "qapi/error.h"
16 #include "qemu-common.h"
18 #include "sysemu/qtest.h"
20 #include "sysemu/char.h"
21 #include "exec/ioport.h"
22 #include "exec/memory.h"
24 #include "sysemu/accel.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/cpus.h"
27 #include "qemu/config-file.h"
28 #include "qemu/option.h"
29 #include "qemu/error-report.h"
30 #include "qemu/cutils.h"
36 static DeviceState *irq_intercept_dev;
37 static FILE *qtest_log_fp;
38 static CharDriverState *qtest_chr;
39 static GString *inbuf;
40 static int irq_levels[MAX_IRQ];
41 static qemu_timeval start_time;
42 static bool qtest_opened;
44 #define FMT_timeval "%ld.%06ld"
49 * Line based protocol, request/response based. Server can send async messages
50 * so clients should always handle many async messages before the response
57 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
58 * let you adjust the value of the clock (monotonically). All the commands
59 * return the current value of the clock in nanoseconds.
64 * Advance the clock to the next deadline. Useful when waiting for
65 * asynchronous events.
70 * Advance the clock by NS nanoseconds.
75 * Advance the clock to NS nanoseconds (do nothing if it's already past).
77 * PIO and memory access:
100 * > writew ADDR VALUE
103 * > writel ADDR VALUE
106 * > writeq ADDR VALUE
124 * > write ADDR SIZE DATA
127 * > b64read ADDR SIZE
130 * > b64write ADDR SIZE B64_DATA
133 * > memset ADDR SIZE VALUE
136 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
137 * For 'memset' a zero size is permitted and does nothing.
139 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
140 * than the expected size, the value will be zero filled at the end of the data
143 * B64_DATA is an arbitrarily long base64 encoded string.
144 * If the sizes do not match, the data will be truncated.
148 * > irq_intercept_in QOM-PATH
151 * > irq_intercept_out QOM-PATH
154 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
155 * QOM-PATH. When the pin is triggered, one of the following async messages
156 * will be printed to the qtest stream:
161 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
162 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
163 * NUM=0 even though it is remapped to GSI 2).
166 static int hex2nib(char ch)
168 if (ch >= '0' && ch <= '9') {
170 } else if (ch >= 'a' && ch <= 'f') {
171 return 10 + (ch - 'a');
172 } else if (ch >= 'A' && ch <= 'F') {
173 return 10 + (ch - 'A');
179 static void qtest_get_time(qemu_timeval *tv)
181 qemu_gettimeofday(tv);
182 tv->tv_sec -= start_time.tv_sec;
183 tv->tv_usec -= start_time.tv_usec;
184 if (tv->tv_usec < 0) {
185 tv->tv_usec += 1000000;
190 static void qtest_send_prefix(CharDriverState *chr)
194 if (!qtest_log_fp || !qtest_opened) {
199 fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
200 (long) tv.tv_sec, (long) tv.tv_usec);
203 static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
207 if (!qtest_log_fp || !qtest_opened) {
211 qtest_send_prefix(NULL);
214 vfprintf(qtest_log_fp, fmt, ap);
218 static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
220 qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
221 if (qtest_log_fp && qtest_opened) {
222 fprintf(qtest_log_fp, "%s", str);
226 static void qtest_send(CharDriverState *chr, const char *str)
228 do_qtest_send(chr, str, strlen(str));
231 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
232 const char *fmt, ...)
238 buffer = g_strdup_vprintf(fmt, ap);
239 qtest_send(chr, buffer);
243 static void qtest_irq_handler(void *opaque, int n, int level)
245 qemu_irq old_irq = *(qemu_irq *)opaque;
246 qemu_set_irq(old_irq, level);
248 if (irq_levels[n] != level) {
249 CharDriverState *chr = qtest_chr;
250 irq_levels[n] = level;
251 qtest_send_prefix(chr);
252 qtest_sendf(chr, "IRQ %s %d\n",
253 level ? "raise" : "lower", n);
257 static void qtest_process_command(CharDriverState *chr, gchar **words)
259 const gchar *command;
270 fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
271 (long) tv.tv_sec, (long) tv.tv_usec);
272 for (i = 0; words[i]; i++) {
273 fprintf(qtest_log_fp, " %s", words[i]);
275 fprintf(qtest_log_fp, "\n");
279 if (strcmp(words[0], "irq_intercept_out") == 0
280 || strcmp(words[0], "irq_intercept_in") == 0) {
285 dev = DEVICE(object_resolve_path(words[1], NULL));
287 qtest_send_prefix(chr);
288 qtest_send(chr, "FAIL Unknown device\n");
292 if (irq_intercept_dev) {
293 qtest_send_prefix(chr);
294 if (irq_intercept_dev != dev) {
295 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
297 qtest_send(chr, "OK\n");
302 QLIST_FOREACH(ngl, &dev->gpios, node) {
303 /* We don't support intercept of named GPIOs yet */
307 if (words[0][14] == 'o') {
309 for (i = 0; i < ngl->num_out; ++i) {
310 qemu_irq *disconnected = g_new0(qemu_irq, 1);
311 qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
314 *disconnected = qdev_intercept_gpio_out(dev, icpt,
318 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
322 irq_intercept_dev = dev;
323 qtest_send_prefix(chr);
324 qtest_send(chr, "OK\n");
326 } else if (strcmp(words[0], "outb") == 0 ||
327 strcmp(words[0], "outw") == 0 ||
328 strcmp(words[0], "outl") == 0) {
332 g_assert(words[1] && words[2]);
333 g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
334 g_assert(qemu_strtoul(words[2], NULL, 0, &value) == 0);
335 g_assert(addr <= 0xffff);
337 if (words[0][3] == 'b') {
338 cpu_outb(addr, value);
339 } else if (words[0][3] == 'w') {
340 cpu_outw(addr, value);
341 } else if (words[0][3] == 'l') {
342 cpu_outl(addr, value);
344 qtest_send_prefix(chr);
345 qtest_send(chr, "OK\n");
346 } else if (strcmp(words[0], "inb") == 0 ||
347 strcmp(words[0], "inw") == 0 ||
348 strcmp(words[0], "inl") == 0) {
350 uint32_t value = -1U;
353 g_assert(qemu_strtoul(words[1], NULL, 0, &addr) == 0);
354 g_assert(addr <= 0xffff);
356 if (words[0][2] == 'b') {
357 value = cpu_inb(addr);
358 } else if (words[0][2] == 'w') {
359 value = cpu_inw(addr);
360 } else if (words[0][2] == 'l') {
361 value = cpu_inl(addr);
363 qtest_send_prefix(chr);
364 qtest_sendf(chr, "OK 0x%04x\n", value);
365 } else if (strcmp(words[0], "writeb") == 0 ||
366 strcmp(words[0], "writew") == 0 ||
367 strcmp(words[0], "writel") == 0 ||
368 strcmp(words[0], "writeq") == 0) {
372 g_assert(words[1] && words[2]);
373 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
374 g_assert(qemu_strtoull(words[2], NULL, 0, &value) == 0);
376 if (words[0][5] == 'b') {
377 uint8_t data = value;
378 cpu_physical_memory_write(addr, &data, 1);
379 } else if (words[0][5] == 'w') {
380 uint16_t data = value;
382 cpu_physical_memory_write(addr, &data, 2);
383 } else if (words[0][5] == 'l') {
384 uint32_t data = value;
386 cpu_physical_memory_write(addr, &data, 4);
387 } else if (words[0][5] == 'q') {
388 uint64_t data = value;
390 cpu_physical_memory_write(addr, &data, 8);
392 qtest_send_prefix(chr);
393 qtest_send(chr, "OK\n");
394 } else if (strcmp(words[0], "readb") == 0 ||
395 strcmp(words[0], "readw") == 0 ||
396 strcmp(words[0], "readl") == 0 ||
397 strcmp(words[0], "readq") == 0) {
399 uint64_t value = UINT64_C(-1);
402 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
404 if (words[0][4] == 'b') {
406 cpu_physical_memory_read(addr, &data, 1);
408 } else if (words[0][4] == 'w') {
410 cpu_physical_memory_read(addr, &data, 2);
411 value = tswap16(data);
412 } else if (words[0][4] == 'l') {
414 cpu_physical_memory_read(addr, &data, 4);
415 value = tswap32(data);
416 } else if (words[0][4] == 'q') {
417 cpu_physical_memory_read(addr, &value, 8);
420 qtest_send_prefix(chr);
421 qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
422 } else if (strcmp(words[0], "read") == 0) {
423 uint64_t addr, len, i;
427 g_assert(words[1] && words[2]);
428 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
429 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
431 data = g_malloc(len);
432 cpu_physical_memory_read(addr, data, len);
434 enc = g_malloc(2 * len + 1);
435 for (i = 0; i < len; i++) {
436 sprintf(&enc[i * 2], "%02x", data[i]);
439 qtest_send_prefix(chr);
440 qtest_sendf(chr, "OK 0x%s\n", enc);
444 } else if (strcmp(words[0], "b64read") == 0) {
449 g_assert(words[1] && words[2]);
450 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
451 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
453 data = g_malloc(len);
454 cpu_physical_memory_read(addr, data, len);
455 b64_data = g_base64_encode(data, len);
456 qtest_send_prefix(chr);
457 qtest_sendf(chr, "OK %s\n", b64_data);
461 } else if (strcmp(words[0], "write") == 0) {
462 uint64_t addr, len, i;
466 g_assert(words[1] && words[2] && words[3]);
467 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
468 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
470 data_len = strlen(words[3]);
472 qtest_send(chr, "ERR invalid argument size\n");
476 data = g_malloc(len);
477 for (i = 0; i < len; i++) {
478 if ((i * 2 + 4) <= data_len) {
479 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
480 data[i] |= hex2nib(words[3][i * 2 + 3]);
485 cpu_physical_memory_write(addr, data, len);
488 qtest_send_prefix(chr);
489 qtest_send(chr, "OK\n");
490 } else if (strcmp(words[0], "memset") == 0) {
493 unsigned long pattern;
495 g_assert(words[1] && words[2] && words[3]);
496 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
497 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
498 g_assert(qemu_strtoul(words[3], NULL, 0, &pattern) == 0);
501 data = g_malloc(len);
502 memset(data, pattern, len);
503 cpu_physical_memory_write(addr, data, len);
507 qtest_send_prefix(chr);
508 qtest_send(chr, "OK\n");
509 } else if (strcmp(words[0], "b64write") == 0) {
515 g_assert(words[1] && words[2] && words[3]);
516 g_assert(qemu_strtoull(words[1], NULL, 0, &addr) == 0);
517 g_assert(qemu_strtoull(words[2], NULL, 0, &len) == 0);
519 data_len = strlen(words[3]);
521 qtest_send(chr, "ERR invalid argument size\n");
525 data = g_base64_decode_inplace(words[3], &out_len);
526 if (out_len != len) {
527 qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
530 out_len = MIN(out_len, len);
533 cpu_physical_memory_write(addr, data, out_len);
535 qtest_send_prefix(chr);
536 qtest_send(chr, "OK\n");
537 } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
541 g_assert(qemu_strtoll(words[1], NULL, 0, &ns) == 0);
543 ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
545 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
546 qtest_send_prefix(chr);
547 qtest_sendf(chr, "OK %"PRIi64"\n",
548 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
549 } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
553 g_assert(qemu_strtoll(words[1], NULL, 0, &ns) == 0);
554 qtest_clock_warp(ns);
555 qtest_send_prefix(chr);
556 qtest_sendf(chr, "OK %"PRIi64"\n",
557 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
559 qtest_send_prefix(chr);
560 qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
564 static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
568 while ((end = strchr(inbuf->str, '\n')) != NULL) {
573 offset = end - inbuf->str;
575 cmd = g_string_new_len(inbuf->str, offset);
576 g_string_erase(inbuf, 0, offset + 1);
578 words = g_strsplit(cmd->str, " ", 0);
579 qtest_process_command(chr, words);
582 g_string_free(cmd, TRUE);
586 static void qtest_read(void *opaque, const uint8_t *buf, int size)
588 CharDriverState *chr = opaque;
590 g_string_append_len(inbuf, (const gchar *)buf, size);
591 qtest_process_inbuf(chr, inbuf);
594 static int qtest_can_read(void *opaque)
599 static void qtest_event(void *opaque, int event)
604 case CHR_EVENT_OPENED:
606 * We used to call qemu_system_reset() here, hoping we could
607 * use the same process for multiple tests that way. Never
608 * used. Injects an extra reset even when it's not used, and
609 * that can mess up tests, e.g. -boot once.
611 for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
614 qemu_gettimeofday(&start_time);
617 fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
618 (long) start_time.tv_sec, (long) start_time.tv_usec);
621 case CHR_EVENT_CLOSED:
622 qtest_opened = false;
626 fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
627 (long) tv.tv_sec, (long) tv.tv_usec);
635 static int qtest_init_accel(MachineState *ms)
637 QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
639 qemu_opt_set(opts, "shift", "0", &error_abort);
640 configure_icount(opts, &error_abort);
645 void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
647 CharDriverState *chr;
649 chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
652 error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
658 if (strcmp(qtest_log, "none") != 0) {
659 qtest_log_fp = fopen(qtest_log, "w+");
662 qtest_log_fp = stderr;
665 qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
666 qemu_chr_fe_set_echo(chr, true);
668 inbuf = g_string_new("");
672 bool qtest_driver(void)
677 static void qtest_accel_class_init(ObjectClass *oc, void *data)
679 AccelClass *ac = ACCEL_CLASS(oc);
681 ac->available = qtest_available;
682 ac->init_machine = qtest_init_accel;
683 ac->allowed = &qtest_allowed;
686 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
688 static const TypeInfo qtest_accel_type = {
689 .name = TYPE_QTEST_ACCEL,
690 .parent = TYPE_ACCEL,
691 .class_init = qtest_accel_class_init,
694 static void qtest_type_init(void)
696 type_register_static(&qtest_accel_type);
699 type_init(qtest_type_init);