4 * Copyright IBM, Corp. 2011
7 * Anthony Liguori <aliguori@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "sysemu/qtest.h"
16 #include "sysemu/char.h"
17 #include "exec/ioport.h"
18 #include "exec/memory.h"
20 #include "sysemu/accel.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/cpus.h"
23 #include "qemu/config-file.h"
24 #include "qemu/option.h"
25 #include "qemu/error-report.h"
31 static DeviceState *irq_intercept_dev;
32 static FILE *qtest_log_fp;
33 static CharDriverState *qtest_chr;
34 static GString *inbuf;
35 static int irq_levels[MAX_IRQ];
36 static qemu_timeval start_time;
37 static bool qtest_opened;
39 #define FMT_timeval "%ld.%06ld"
44 * Line based protocol, request/response based. Server can send async messages
45 * so clients should always handle many async messages before the response
52 * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL. qtest commands
53 * let you adjust the value of the clock (monotonically). All the commands
54 * return the current value of the clock in nanoseconds.
59 * Advance the clock to the next deadline. Useful when waiting for
60 * asynchronous events.
65 * Advance the clock by NS nanoseconds.
70 * Advance the clock to NS nanoseconds (do nothing if it's already past).
72 * PIO and memory access:
101 * > writeq ADDR VALUE
119 * > write ADDR SIZE DATA
122 * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
124 * DATA is an arbitrarily long hex number prefixed with '0x'. If it's smaller
125 * than the expected size, the value will be zero filled at the end of the data
130 * > irq_intercept_in QOM-PATH
133 * > irq_intercept_out QOM-PATH
136 * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
137 * QOM-PATH. When the pin is triggered, one of the following async messages
138 * will be printed to the qtest stream:
143 * where NUM is an IRQ number. For the PC, interrupts can be intercepted
144 * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
145 * NUM=0 even though it is remapped to GSI 2).
148 static int hex2nib(char ch)
150 if (ch >= '0' && ch <= '9') {
152 } else if (ch >= 'a' && ch <= 'f') {
153 return 10 + (ch - 'a');
154 } else if (ch >= 'A' && ch <= 'F') {
155 return 10 + (ch - 'A');
161 static void qtest_get_time(qemu_timeval *tv)
163 qemu_gettimeofday(tv);
164 tv->tv_sec -= start_time.tv_sec;
165 tv->tv_usec -= start_time.tv_usec;
166 if (tv->tv_usec < 0) {
167 tv->tv_usec += 1000000;
172 static void qtest_send_prefix(CharDriverState *chr)
176 if (!qtest_log_fp || !qtest_opened) {
181 fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
182 (long) tv.tv_sec, (long) tv.tv_usec);
185 static void do_qtest_send(CharDriverState *chr, const char *str, size_t len)
187 qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
188 if (qtest_log_fp && qtest_opened) {
189 fprintf(qtest_log_fp, "%s", str);
193 static void qtest_send(CharDriverState *chr, const char *str)
195 do_qtest_send(chr, str, strlen(str));
198 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharDriverState *chr,
199 const char *fmt, ...)
205 buffer = g_strdup_vprintf(fmt, ap);
206 qtest_send(chr, buffer);
210 static void qtest_irq_handler(void *opaque, int n, int level)
212 qemu_irq old_irq = *(qemu_irq *)opaque;
213 qemu_set_irq(old_irq, level);
215 if (irq_levels[n] != level) {
216 CharDriverState *chr = qtest_chr;
217 irq_levels[n] = level;
218 qtest_send_prefix(chr);
219 qtest_sendf(chr, "IRQ %s %d\n",
220 level ? "raise" : "lower", n);
224 static void qtest_process_command(CharDriverState *chr, gchar **words)
226 const gchar *command;
237 fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
238 (long) tv.tv_sec, (long) tv.tv_usec);
239 for (i = 0; words[i]; i++) {
240 fprintf(qtest_log_fp, " %s", words[i]);
242 fprintf(qtest_log_fp, "\n");
246 if (strcmp(words[0], "irq_intercept_out") == 0
247 || strcmp(words[0], "irq_intercept_in") == 0) {
252 dev = DEVICE(object_resolve_path(words[1], NULL));
254 qtest_send_prefix(chr);
255 qtest_send(chr, "FAIL Unknown device\n");
259 if (irq_intercept_dev) {
260 qtest_send_prefix(chr);
261 if (irq_intercept_dev != dev) {
262 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
264 qtest_send(chr, "OK\n");
269 QLIST_FOREACH(ngl, &dev->gpios, node) {
270 /* We don't support intercept of named GPIOs yet */
274 if (words[0][14] == 'o') {
276 for (i = 0; i < ngl->num_out; ++i) {
277 qemu_irq *disconnected = g_new0(qemu_irq, 1);
278 qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
281 *disconnected = qdev_intercept_gpio_out(dev, icpt,
285 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
289 irq_intercept_dev = dev;
290 qtest_send_prefix(chr);
291 qtest_send(chr, "OK\n");
293 } else if (strcmp(words[0], "outb") == 0 ||
294 strcmp(words[0], "outw") == 0 ||
295 strcmp(words[0], "outl") == 0) {
299 g_assert(words[1] && words[2]);
300 addr = strtoul(words[1], NULL, 0);
301 value = strtoul(words[2], NULL, 0);
303 if (words[0][3] == 'b') {
304 cpu_outb(addr, value);
305 } else if (words[0][3] == 'w') {
306 cpu_outw(addr, value);
307 } else if (words[0][3] == 'l') {
308 cpu_outl(addr, value);
310 qtest_send_prefix(chr);
311 qtest_send(chr, "OK\n");
312 } else if (strcmp(words[0], "inb") == 0 ||
313 strcmp(words[0], "inw") == 0 ||
314 strcmp(words[0], "inl") == 0) {
316 uint32_t value = -1U;
319 addr = strtoul(words[1], NULL, 0);
321 if (words[0][2] == 'b') {
322 value = cpu_inb(addr);
323 } else if (words[0][2] == 'w') {
324 value = cpu_inw(addr);
325 } else if (words[0][2] == 'l') {
326 value = cpu_inl(addr);
328 qtest_send_prefix(chr);
329 qtest_sendf(chr, "OK 0x%04x\n", value);
330 } else if (strcmp(words[0], "writeb") == 0 ||
331 strcmp(words[0], "writew") == 0 ||
332 strcmp(words[0], "writel") == 0 ||
333 strcmp(words[0], "writeq") == 0) {
337 g_assert(words[1] && words[2]);
338 addr = strtoull(words[1], NULL, 0);
339 value = strtoull(words[2], NULL, 0);
341 if (words[0][5] == 'b') {
342 uint8_t data = value;
343 cpu_physical_memory_write(addr, &data, 1);
344 } else if (words[0][5] == 'w') {
345 uint16_t data = value;
347 cpu_physical_memory_write(addr, &data, 2);
348 } else if (words[0][5] == 'l') {
349 uint32_t data = value;
351 cpu_physical_memory_write(addr, &data, 4);
352 } else if (words[0][5] == 'q') {
353 uint64_t data = value;
355 cpu_physical_memory_write(addr, &data, 8);
357 qtest_send_prefix(chr);
358 qtest_send(chr, "OK\n");
359 } else if (strcmp(words[0], "readb") == 0 ||
360 strcmp(words[0], "readw") == 0 ||
361 strcmp(words[0], "readl") == 0 ||
362 strcmp(words[0], "readq") == 0) {
364 uint64_t value = UINT64_C(-1);
367 addr = strtoull(words[1], NULL, 0);
369 if (words[0][4] == 'b') {
371 cpu_physical_memory_read(addr, &data, 1);
373 } else if (words[0][4] == 'w') {
375 cpu_physical_memory_read(addr, &data, 2);
376 value = tswap16(data);
377 } else if (words[0][4] == 'l') {
379 cpu_physical_memory_read(addr, &data, 4);
380 value = tswap32(data);
381 } else if (words[0][4] == 'q') {
382 cpu_physical_memory_read(addr, &value, 8);
385 qtest_send_prefix(chr);
386 qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
387 } else if (strcmp(words[0], "read") == 0) {
388 uint64_t addr, len, i;
391 g_assert(words[1] && words[2]);
392 addr = strtoull(words[1], NULL, 0);
393 len = strtoull(words[2], NULL, 0);
395 data = g_malloc(len);
396 cpu_physical_memory_read(addr, data, len);
398 qtest_send_prefix(chr);
399 qtest_send(chr, "OK 0x");
400 for (i = 0; i < len; i++) {
401 qtest_sendf(chr, "%02x", data[i]);
403 qtest_send(chr, "\n");
406 } else if (strcmp(words[0], "write") == 0) {
407 uint64_t addr, len, i;
411 g_assert(words[1] && words[2] && words[3]);
412 addr = strtoull(words[1], NULL, 0);
413 len = strtoull(words[2], NULL, 0);
415 data_len = strlen(words[3]);
417 qtest_send(chr, "ERR invalid argument size\n");
421 data = g_malloc(len);
422 for (i = 0; i < len; i++) {
423 if ((i * 2 + 4) <= data_len) {
424 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
425 data[i] |= hex2nib(words[3][i * 2 + 3]);
430 cpu_physical_memory_write(addr, data, len);
433 qtest_send_prefix(chr);
434 qtest_send(chr, "OK\n");
435 } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
439 ns = strtoll(words[1], NULL, 0);
441 ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
443 qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
444 qtest_send_prefix(chr);
445 qtest_sendf(chr, "OK %"PRIi64"\n",
446 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
447 } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
451 ns = strtoll(words[1], NULL, 0);
452 qtest_clock_warp(ns);
453 qtest_send_prefix(chr);
454 qtest_sendf(chr, "OK %"PRIi64"\n",
455 (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
457 qtest_send_prefix(chr);
458 qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
462 static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
466 while ((end = strchr(inbuf->str, '\n')) != NULL) {
471 offset = end - inbuf->str;
473 cmd = g_string_new_len(inbuf->str, offset);
474 g_string_erase(inbuf, 0, offset + 1);
476 words = g_strsplit(cmd->str, " ", 0);
477 qtest_process_command(chr, words);
480 g_string_free(cmd, TRUE);
484 static void qtest_read(void *opaque, const uint8_t *buf, int size)
486 CharDriverState *chr = opaque;
488 g_string_append_len(inbuf, (const gchar *)buf, size);
489 qtest_process_inbuf(chr, inbuf);
492 static int qtest_can_read(void *opaque)
497 static void qtest_event(void *opaque, int event)
502 case CHR_EVENT_OPENED:
504 * We used to call qemu_system_reset() here, hoping we could
505 * use the same process for multiple tests that way. Never
506 * used. Injects an extra reset even when it's not used, and
507 * that can mess up tests, e.g. -boot once.
509 for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
512 qemu_gettimeofday(&start_time);
515 fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
516 (long) start_time.tv_sec, (long) start_time.tv_usec);
519 case CHR_EVENT_CLOSED:
520 qtest_opened = false;
524 fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
525 (long) tv.tv_sec, (long) tv.tv_usec);
533 static int qtest_init_accel(MachineState *ms)
535 QemuOpts *opts = qemu_opts_create(qemu_find_opts("icount"), NULL, 0,
537 qemu_opt_set(opts, "shift", "0", &error_abort);
538 configure_icount(opts, &error_abort);
543 void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
545 CharDriverState *chr;
547 chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
550 error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
556 if (strcmp(qtest_log, "none") != 0) {
557 qtest_log_fp = fopen(qtest_log, "w+");
560 qtest_log_fp = stderr;
563 qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
564 qemu_chr_fe_set_echo(chr, true);
566 inbuf = g_string_new("");
570 bool qtest_driver(void)
575 static void qtest_accel_class_init(ObjectClass *oc, void *data)
577 AccelClass *ac = ACCEL_CLASS(oc);
579 ac->available = qtest_available;
580 ac->init_machine = qtest_init_accel;
581 ac->allowed = &qtest_allowed;
584 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
586 static const TypeInfo qtest_accel_type = {
587 .name = TYPE_QTEST_ACCEL,
588 .parent = TYPE_ACCEL,
589 .class_init = qtest_accel_class_init,
592 static void qtest_type_init(void)
594 type_register_static(&qtest_accel_type);
597 type_init(qtest_type_init);