pvr/services4/include/sgxinfo.h

   1 /**********************************************************************
   2  Copyright (c) Imagination Technologies Ltd.
   3
   4  Permission is hereby granted, free of charge, to any person obtaining a copy
   5  of this software and associated documentation files (the "Software"), to deal
   6  in the Software without restriction, including without limitation the rights
   7  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  copies of the Software, and to permit persons to whom the Software is
   9  furnished to do so, subject to the following conditions:
  10
  11  The above copyright notice and this permission notice shall be included in
  12  all copies or substantial portions of the Software.
  13
  14  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  THE SOFTWARE.
  21  ******************************************************************************/
  22
  23 #if !defined (__SGXINFO_H__)
  24 #define __SGXINFO_H__
  25
  26 #include "sgxscript.h"
  27 #include "servicesint.h"
  28 #include "services.h"
  29 #include "sgxapi_km.h"
  30 #include "sgx_mkif_km.h"
  31
  32
  33 #define SGX_MAX_DEV_DATA                        24
  34 #define SGX_MAX_INIT_MEM_HANDLES        16
  35
  36
  37 typedef struct _SGX_BRIDGE_INFO_FOR_SRVINIT
  38 {
  39         IMG_DEV_PHYADDR sPDDevPAddr;
  40         PVRSRV_HEAP_INFO asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
  41 } SGX_BRIDGE_INFO_FOR_SRVINIT;
  42
  43
  44 typedef enum _SGXMKIF_CMD_TYPE_
  45 {
  46         SGXMKIF_CMD_TA                          = 0,
  47         SGXMKIF_CMD_TRANSFER            = 1,
  48         SGXMKIF_CMD_2D                          = 2,
  49         SGXMKIF_CMD_POWER                       = 3,
  50         SGXMKIF_CMD_CLEANUP                     = 4,
  51         SGXMKIF_CMD_GETMISCINFO         = 5,
  52         SGXMKIF_CMD_PROCESS_QUEUES      = 6,
  53         SGXMKIF_CMD_MAX                         = 7,
  54
  55         SGXMKIF_CMD_FORCE_I32           = -1,
  56
  57 } SGXMKIF_CMD_TYPE;
  58
  59
  60 typedef struct _SGX_BRIDGE_INIT_INFO_
  61 {
  62         IMG_HANDLE      hKernelCCBMemInfo;
  63         IMG_HANDLE      hKernelCCBCtlMemInfo;
  64         IMG_HANDLE      hKernelCCBEventKickerMemInfo;
  65         IMG_HANDLE      hKernelSGXHostCtlMemInfo;
  66         IMG_HANDLE      hKernelSGXTA3DCtlMemInfo;
  67         IMG_HANDLE      hKernelSGXMiscMemInfo;
  68
  69         IMG_UINT32      aui32HostKickAddr[SGXMKIF_CMD_MAX];
  70
  71         SGX_INIT_SCRIPTS sScripts;
  72
  73         IMG_UINT32      ui32ClientBuildOptions;
  74         SGX_MISCINFO_STRUCT_SIZES       sSGXStructSizes;
  75
  76 #if defined(SGX_SUPPORT_HWPROFILING)
  77         IMG_HANDLE      hKernelHWProfilingMemInfo;
  78 #endif
  79 #if defined(SUPPORT_SGX_HWPERF)
  80         IMG_HANDLE      hKernelHWPerfCBMemInfo;
  81 #endif
  82 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
  83         IMG_HANDLE      hKernelEDMStatusBufferMemInfo;
  84 #endif
  85 #if defined(SGX_FEATURE_OVERLAPPED_SPM)
  86         IMG_HANDLE hKernelTmpRgnHeaderMemInfo;
  87 #endif
  88 #if defined(SGX_FEATURE_SPM_MODE_0)
  89         IMG_HANDLE hKernelTmpDPMStateMemInfo;
  90 #endif
  91
  92         IMG_UINT32 ui32EDMTaskReg0;
  93         IMG_UINT32 ui32EDMTaskReg1;
  94
  95         IMG_UINT32 ui32ClkGateStatusReg;
  96         IMG_UINT32 ui32ClkGateStatusMask;
  97 #if defined(SGX_FEATURE_MP)
  98         IMG_UINT32 ui32MasterClkGateStatusReg;
  99         IMG_UINT32 ui32MasterClkGateStatusMask;
 100 #endif
 101
 102         IMG_UINT32 ui32CacheControl;
 103
 104         IMG_UINT32      asInitDevData[SGX_MAX_DEV_DATA];
 105         IMG_HANDLE      asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
 106
 107 } SGX_BRIDGE_INIT_INFO;
 108
 109
 110 typedef struct _SGX_DEVICE_SYNC_LIST_
 111 {
 112         PSGXMKIF_HWDEVICE_SYNC_LIST     psHWDeviceSyncList;
 113
 114         IMG_HANDLE                              hKernelHWSyncListMemInfo;
 115         PVRSRV_CLIENT_MEM_INFO  *psHWDeviceSyncListClientMemInfo;
 116         PVRSRV_CLIENT_MEM_INFO  *psAccessResourceClientMemInfo;
 117
 118         volatile IMG_UINT32             *pui32Lock;
 119
 120         struct _SGX_DEVICE_SYNC_LIST_   *psNext;
 121
 122
 123         IMG_UINT32                      ui32NumSyncObjects;
 124         IMG_HANDLE                      ahSyncHandles[1];
 125 } SGX_DEVICE_SYNC_LIST, *PSGX_DEVICE_SYNC_LIST;
 126
 127
 128 typedef struct _SGX_INTERNEL_STATUS_UPDATE_
 129 {
 130         CTL_STATUS                              sCtlStatus;
 131         IMG_HANDLE                              hKernelMemInfo;
 132
 133         IMG_UINT32                              ui32LastStatusUpdateDumpVal;
 134 } SGX_INTERNEL_STATUS_UPDATE;
 135
 136
 137 typedef struct _SGX_CCB_KICK_
 138 {
 139         SGXMKIF_COMMAND         sCommand;
 140         IMG_HANDLE                      hCCBKernelMemInfo;
 141
 142         IMG_UINT32      ui32NumDstSyncObjects;
 143         IMG_HANDLE      hKernelHWSyncListMemInfo;
 144
 145
 146         IMG_HANDLE      *pahDstSyncHandles;
 147
 148         IMG_UINT32      ui32NumTAStatusVals;
 149         IMG_UINT32      ui32Num3DStatusVals;
 150
 151 #if defined(SUPPORT_SGX_NEW_STATUS_VALS)
 152         SGX_INTERNEL_STATUS_UPDATE      asTAStatusUpdate[SGX_MAX_TA_STATUS_VALS];
 153         SGX_INTERNEL_STATUS_UPDATE      as3DStatusUpdate[SGX_MAX_3D_STATUS_VALS];
 154 #else
 155         IMG_HANDLE      ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
 156         IMG_HANDLE      ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
 157 #endif
 158
 159         IMG_BOOL        bFirstKickOrResume;
 160 #if (defined(NO_HARDWARE) || defined(PDUMP))
 161         IMG_BOOL        bTerminateOrAbort;
 162 #endif
 163 #if defined(SUPPORT_SGX_HWPERF)
 164         IMG_BOOL                        bKickRender;
 165 #endif
 166
 167
 168         IMG_UINT32      ui32CCBOffset;
 169
 170 #if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
 171
 172         IMG_UINT32      ui32NumTASrcSyncs;
 173         IMG_HANDLE      ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS];
 174         IMG_UINT32      ui32NumTADstSyncs;
 175         IMG_HANDLE      ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS];
 176         IMG_UINT32      ui32Num3DSrcSyncs;
 177         IMG_HANDLE      ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS];
 178 #else
 179
 180         IMG_UINT32      ui32NumSrcSyncs;
 181         IMG_HANDLE      ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
 182 #endif
 183
 184
 185         IMG_BOOL        bTADependency;
 186         IMG_HANDLE      hTA3DSyncInfo;
 187
 188         IMG_HANDLE      hTASyncInfo;
 189         IMG_HANDLE      h3DSyncInfo;
 190 #if defined(PDUMP)
 191         IMG_UINT32      ui32CCBDumpWOff;
 192 #endif
 193 #if defined(NO_HARDWARE)
 194         IMG_UINT32      ui32WriteOpsPendingVal;
 195 #endif
 196 } SGX_CCB_KICK;
 197
 198
 199 #define SGX_KERNEL_USE_CODE_BASE_INDEX          15
 200
 201
 202 typedef struct _SGX_CLIENT_INFO_
 203 {
 204         IMG_UINT32                                      ui32ProcessID;
 205         IMG_VOID                                        *pvProcess;
 206         PVRSRV_MISC_INFO                        sMiscInfo;
 207
 208         IMG_UINT32                                      asDevData[SGX_MAX_DEV_DATA];
 209
 210 } SGX_CLIENT_INFO;
 211
 212 typedef struct _SGX_INTERNAL_DEVINFO_
 213 {
 214         IMG_UINT32                      ui32Flags;
 215         IMG_HANDLE                      hHostCtlKernelMemInfoHandle;
 216         IMG_BOOL                        bForcePTOff;
 217 } SGX_INTERNAL_DEVINFO;
 218
 219
 220 #if defined(TRANSFER_QUEUE)
 221 typedef struct _PVRSRV_TRANSFER_SGX_KICK_
 222 {
 223         IMG_HANDLE              hCCBMemInfo;
 224         IMG_UINT32              ui32SharedCmdCCBOffset;
 225
 226         IMG_DEV_VIRTADDR        sHWTransferContextDevVAddr;
 227
 228         IMG_HANDLE              hTASyncInfo;
 229         IMG_HANDLE              h3DSyncInfo;
 230
 231         IMG_UINT32              ui32NumSrcSync;
 232         IMG_HANDLE              ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 233
 234         IMG_UINT32              ui32NumDstSync;
 235         IMG_HANDLE              ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 236
 237         IMG_UINT32              ui32Flags;
 238
 239         IMG_UINT32              ui32PDumpFlags;
 240 #if defined(PDUMP)
 241         IMG_UINT32              ui32CCBDumpWOff;
 242 #endif
 243
 244         IMG_HANDLE              display;
 245         IMG_UINT32              headline;
 246         IMG_UINT32              footline;
 247 } PVRSRV_TRANSFER_SGX_KICK, *PPVRSRV_TRANSFER_SGX_KICK;
 248
 249 #if defined(SGX_FEATURE_2D_HARDWARE)
 250 typedef struct _PVRSRV_2D_SGX_KICK_
 251 {
 252         IMG_HANDLE              hCCBMemInfo;
 253         IMG_UINT32              ui32SharedCmdCCBOffset;
 254
 255         IMG_DEV_VIRTADDR        sHW2DContextDevVAddr;
 256
 257         IMG_UINT32              ui32NumSrcSync;
 258         IMG_HANDLE              ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS];
 259
 260
 261         IMG_HANDLE              hDstSyncInfo;
 262
 263
 264         IMG_HANDLE              hTASyncInfo;
 265
 266
 267         IMG_HANDLE              h3DSyncInfo;
 268
 269         IMG_UINT32              ui32PDumpFlags;
 270 #if defined(PDUMP)
 271         IMG_UINT32              ui32CCBDumpWOff;
 272 #endif
 273 } PVRSRV_2D_SGX_KICK, *PPVRSRV_2D_SGX_KICK;
 274 #endif
 275 #endif
 276
 277 #define PVRSRV_SGX_DIFF_NUM_COUNTERS    9
 278
 279 typedef struct _PVRSRV_SGXDEV_DIFF_INFO_
 280 {
 281         IMG_UINT32      aui32Counters[PVRSRV_SGX_DIFF_NUM_COUNTERS];
 282         IMG_UINT32      ui32Time[3];
 283         IMG_UINT32      ui32Marker[2];
 284 } PVRSRV_SGXDEV_DIFF_INFO, *PPVRSRV_SGXDEV_DIFF_INFO;
 285
 286
 287
 288 #endif