3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <ppc_asm.tmpl>
31 #include <asm/cache.h>
34 #if CONFIG_POST & CFG_POST_CACHE
39 * All 44x variants deal with cache management differently
40 * because they have the address translation always enabled.
41 * The 40x ppc's don't use address translation in U-Boot at all,
42 * so we have to distinguish here between 40x and 44x.
45 /* void cache_post_disable (int tlb)
49 ori r0, r0, TLB_WORD2_I_ENABLE@l
55 /* void cache_post_wt (int tlb)
59 ori r0, r0, TLB_WORD2_W_ENABLE@l
60 andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
66 /* void cache_post_wb (int tlb)
70 andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
71 andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
77 /* void cache_post_disable (int tlb)
87 /* void cache_post_wt (int tlb)
100 /* void cache_post_wb (int tlb)
114 /* void cache_post_dinvalidate (void *p, int size)
116 cache_post_dinvalidate:
118 addi r3, r3, CFG_CACHELINE_SIZE
119 subic. r4, r4, CFG_CACHELINE_SIZE
120 bgt cache_post_dinvalidate
124 /* void cache_post_dstore (void *p, int size)
128 addi r3, r3, CFG_CACHELINE_SIZE
129 subic. r4, r4, CFG_CACHELINE_SIZE
130 bgt cache_post_dstore
134 /* void cache_post_dtouch (void *p, int size)
138 addi r3, r3, CFG_CACHELINE_SIZE
139 subic. r4, r4, CFG_CACHELINE_SIZE
140 bgt cache_post_dtouch
144 /* void cache_post_iinvalidate (void)
146 cache_post_iinvalidate:
151 /* void cache_post_memset (void *p, int val, int size)
161 /* int cache_post_check (void *p, int size)
177 #define CACHE_POST_DISABLE() \
179 bl cache_post_disable
181 #define CACHE_POST_WT() \
185 #define CACHE_POST_WB() \
189 #define CACHE_POST_DINVALIDATE() \
192 bl cache_post_dinvalidate
194 #define CACHE_POST_DFLUSH() \
199 #define CACHE_POST_DSTORE() \
204 #define CACHE_POST_DTOUCH() \
209 #define CACHE_POST_IINVALIDATE() \
210 bl cache_post_iinvalidate
212 #define CACHE_POST_MEMSET(val) \
218 #define CACHE_POST_CHECK() \
221 bl cache_post_check; \
225 * Write and read 0xff pattern with caching enabled.
227 .global cache_post_test1
232 mr r12, r5 /* size */
235 CACHE_POST_DINVALIDATE()
237 /* Write the negative pattern to the test area */
238 CACHE_POST_MEMSET(0xff)
240 /* Read the test area */
243 CACHE_POST_DINVALIDATE()
251 * Write zeroes with caching enabled.
252 * Write 0xff pattern with caching disabled.
253 * Read 0xff pattern with caching enabled.
255 .global cache_post_test2
260 mr r12, r5 /* size */
263 CACHE_POST_DINVALIDATE()
265 /* Write the zero pattern to the test area */
268 CACHE_POST_DINVALIDATE()
271 /* Write the negative pattern to the test area */
272 CACHE_POST_MEMSET(0xff)
276 /* Read the test area */
279 CACHE_POST_DINVALIDATE()
287 * Write-through mode test.
288 * Write zeroes, store the cache, write 0xff pattern.
289 * Invalidate the cache.
290 * Check that 0xff pattern is read.
292 .global cache_post_test3
297 mr r12, r5 /* size */
300 CACHE_POST_DINVALIDATE()
302 /* Cache the test area */
305 /* Write the zero pattern to the test area */
310 /* Write the negative pattern to the test area */
311 CACHE_POST_MEMSET(0xff)
313 CACHE_POST_DINVALIDATE()
316 /* Read the test area */
324 * Write-back mode test.
325 * Write 0xff pattern, store the cache, write zeroes.
326 * Invalidate the cache.
327 * Check that 0xff pattern is read.
329 .global cache_post_test4
334 mr r12, r5 /* size */
337 CACHE_POST_DINVALIDATE()
339 /* Cache the test area */
342 /* Write the negative pattern to the test area */
343 CACHE_POST_MEMSET(0xff)
347 /* Write the zero pattern to the test area */
350 CACHE_POST_DINVALIDATE()
353 /* Read the test area */
361 * Load the test instructions into the instruction cache.
362 * Replace the test instructions.
363 * Check that the original instructions are executed.
365 .global cache_post_test5
370 mr r12, r5 /* size */
373 CACHE_POST_IINVALIDATE()
375 /* Compute r13 = cache_post_test_inst */
376 bl cache_post_test5_reloc
377 cache_post_test5_reloc:
379 lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
380 ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
383 /* Copy the test instructions to the test area */
390 /* Invalidate the cache line */
395 /* Execute the test instructions */
399 /* Replace the test instruction */
404 /* Do not invalidate the cache line */
407 /* Execute the test instructions */
412 CACHE_POST_IINVALIDATE()
413 CACHE_POST_DINVALIDATE()
421 * Load the test instructions into the instruction cache.
422 * Replace the test instructions and invalidate the cache.
423 * Check that the replaced instructions are executed.
425 .global cache_post_test6
430 mr r12, r5 /* size */
433 CACHE_POST_IINVALIDATE()
435 /* Compute r13 = cache_post_test_inst */
436 bl cache_post_test6_reloc
437 cache_post_test6_reloc:
439 lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
440 ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
443 /* Copy the test instructions to the test area */
450 /* Invalidate the cache line */
455 /* Execute the test instructions */
459 /* Replace the test instruction */
464 /* Invalidate the cache line */
469 /* Execute the test instructions */
474 CACHE_POST_IINVALIDATE()
475 CACHE_POST_DINVALIDATE()
482 /* Test instructions.
484 cache_post_test_inst:
489 #endif /* CONFIG_POST & CFG_POST_CACHE */