3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * This test verifies the CPU data and instruction cache using
31 * several test scenarios.
38 #if CONFIG_POST & CFG_POST_CACHE
43 #define CACHE_POST_SIZE 1024
45 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
47 int cache_post_test1 (int tlb, void *p, int size);
48 int cache_post_test2 (int tlb, void *p, int size);
49 int cache_post_test3 (int tlb, void *p, int size);
50 int cache_post_test4 (int tlb, void *p, int size);
51 int cache_post_test5 (int tlb, void *p, int size);
52 int cache_post_test6 (int tlb, void *p, int size);
54 static int tlb = -1; /* index to the victim TLB entry */
56 static unsigned char testarea[CACHE_POST_SIZE]
57 __attribute__((__aligned__(CACHE_POST_SIZE)));
59 int cache_post_test (int flags)
61 void* virt = (void*)CFG_POST_CACHE_ADDR;
67 * Allocate a new TLB entry, since we are going to modify
68 * the write-through and caching inhibited storage attributes.
70 program_tlb((u32)testarea, (u32)virt,
71 CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
73 /* Find the TLB entry */
75 if (i >= PPC4XX_TLB_SIZE) {
76 printf ("Failed to program tlb entry\n");
80 if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
86 ints = disable_interrupts ();
90 res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE);
93 res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE);
96 res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE);
99 res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE);
102 res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE);
105 res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE);
108 enable_interrupts ();
113 #endif /* CONFIG_POST & CFG_POST_CACHE */
114 #endif /* CONFIG_POST */