3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * The Serial Management Controllers (SMC) and the Serial Communication
30 * Controllers (SCC) listed in ctlr_list array below are tested in
31 * the loopback UART mode.
32 * The controllers are configured accordingly and several characters
33 * are transmitted. The configurable test parameters are:
34 * MIN_PACKET_LENGTH - minimum size of packet to transmit
35 * MAX_PACKET_LENGTH - maximum size of packet to transmit
36 * TEST_NUM - number of tests
40 #if CONFIG_POST & CONFIG_SYS_POST_UART
41 #if defined(CONFIG_8xx)
43 #elif defined(CONFIG_MPC8260)
44 #include <asm/cpm_8260.h>
46 #error "Apparently a bad configuration, please fix."
51 DECLARE_GLOBAL_DATA_PTR;
56 /* The list of controllers to test */
57 #if defined(CONFIG_MPC823)
58 static int ctlr_list[][2] =
59 { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
61 static int ctlr_list[][2] = { };
64 #define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
67 void (*init) (int index);
68 void (*halt) (int index);
69 void (*putc) (int index, const char c);
70 int (*getc) (int index);
73 static char *ctlr_name[2] = { "SMC", "SCC" };
75 static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
76 static int proff_scc[] =
77 { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
83 static void smc_init (int smc_index)
85 static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
87 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
89 volatile smc_uart_t *up;
90 volatile cbd_t *tbdf, *rbdf;
91 volatile cpm8xx_t *cp = &(im->im_cpm);
94 /* initialize pointers to SMC */
96 sp = (smc_t *) & (cp->cp_smc[smc_index]);
97 up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
99 /* Disable transmitter/receiver.
101 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
105 im->im_siu_conf.sc_sdcr = 1;
107 /* clear error conditions */
108 #ifdef CONFIG_SYS_SDSR
109 im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
111 im->im_sdma.sdma_sdsr = 0x83;
114 /* clear SDMA interrupt mask */
115 #ifdef CONFIG_SYS_SDMR
116 im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
118 im->im_sdma.sdma_sdmr = 0x00;
121 #if defined(CONFIG_FADS)
124 ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
127 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
128 /* Enable Monitor Port Transceiver */
129 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
132 /* Set the physical address of the host memory buffers in
133 * the buffer descriptors.
136 #ifdef CONFIG_SYS_ALLOC_DPRAM
137 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
139 dpaddr = CPM_POST_BASE;
142 /* Allocate space for two buffer descriptors in the DP ram.
143 * For now, this address seems OK, but it may have to
144 * change with newer versions of the firmware.
145 * damm: allocating space after the two buffers for rx/tx data
148 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
149 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
152 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
155 /* Set up the uart parameters in the parameter ram.
157 up->smc_rbase = dpaddr;
158 up->smc_tbase = dpaddr + sizeof (cbd_t);
159 up->smc_rfcr = SMC_EB;
160 up->smc_tfcr = SMC_EB;
162 #if defined(CONFIG_MBX)
163 board_serial_init ();
166 /* Set UART mode, 8 bit, no parity, one stop.
167 * Enable receive and transmit.
168 * Set local loopback mode.
170 sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
172 /* Mask all interrupts and remove anything pending.
177 /* Set up the baud rate generator.
179 cp->cp_simode = 0x00000000;
182 (((gd->cpu_clk / 16 / gd->baudrate) -
183 1) << 1) | CPM_BRG_EN;
185 /* Make the first buffer the only buffer.
187 tbdf->cbd_sc |= BD_SC_WRAP;
188 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
190 /* Single character receive.
195 /* Initialize Tx/Rx parameters.
198 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
202 mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
204 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
207 /* Enable transmitter/receiver.
209 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
212 static void smc_halt(int smc_index)
216 static void smc_putc (int smc_index, const char c)
218 volatile cbd_t *tbdf;
220 volatile smc_uart_t *up;
221 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
222 volatile cpm8xx_t *cpmp = &(im->im_cpm);
224 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
226 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
228 /* Wait for last character to go.
231 buf = (char *) tbdf->cbd_bufaddr;
234 while (tbdf->cbd_sc & BD_SC_READY)
239 tbdf->cbd_datlen = 1;
240 tbdf->cbd_sc |= BD_SC_READY;
243 while (tbdf->cbd_sc & BD_SC_READY)
248 static int smc_getc (int smc_index)
250 volatile cbd_t *rbdf;
251 volatile unsigned char *buf;
252 volatile smc_uart_t *up;
253 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
254 volatile cpm8xx_t *cpmp = &(im->im_cpm);
258 up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
260 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
262 /* Wait for character to show up.
264 buf = (unsigned char *) rbdf->cbd_bufaddr;
266 while (rbdf->cbd_sc & BD_SC_EMPTY);
268 for (i = 100; i > 0; i--) {
269 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
278 rbdf->cbd_sc |= BD_SC_EMPTY;
287 static void scc_init (int scc_index)
289 static int cpm_cr_ch[] = {
296 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
298 volatile scc_uart_t *up;
299 volatile cbd_t *tbdf, *rbdf;
300 volatile cpm8xx_t *cp = &(im->im_cpm);
303 /* initialize pointers to SCC */
305 sp = (scc_t *) & (cp->cp_scc[scc_index]);
306 up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
308 /* Disable transmitter/receiver.
310 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
313 /* Allocate space for two buffer descriptors in the DP ram.
316 #ifdef CONFIG_SYS_ALLOC_DPRAM
317 dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
319 dpaddr = CPM_POST_BASE;
324 im->im_siu_conf.sc_sdcr = 0x0001;
326 /* Set the physical address of the host memory buffers in
327 * the buffer descriptors.
330 rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
331 rbdf->cbd_bufaddr = (uint) (rbdf + 2);
334 tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
337 /* Set up the baud rate generator.
339 cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
340 /* no |= needed, since BRG1 is 000 */
343 (((gd->cpu_clk / 16 / gd->baudrate) -
344 1) << 1) | CPM_BRG_EN;
346 /* Set up the uart parameters in the parameter ram.
348 up->scc_genscc.scc_rbase = dpaddr;
349 up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
351 /* Initialize Tx/Rx parameters.
353 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
356 mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
358 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
361 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
362 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
364 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
365 up->scc_maxidl = 0; /* disable max idle */
366 up->scc_brkcr = 1; /* send one break character on stop TX */
374 up->scc_char1 = 0x8000;
375 up->scc_char2 = 0x8000;
376 up->scc_char3 = 0x8000;
377 up->scc_char4 = 0x8000;
378 up->scc_char5 = 0x8000;
379 up->scc_char6 = 0x8000;
380 up->scc_char7 = 0x8000;
381 up->scc_char8 = 0x8000;
382 up->scc_rccm = 0xc0ff;
384 /* Set low latency / small fifo.
386 sp->scc_gsmrh = SCC_GSMRH_RFW;
390 sp->scc_gsmrl &= ~0xF;
391 sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
393 /* Set local loopback mode.
395 sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
396 sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
398 /* Set clock divider 16 on Tx and Rx
400 sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
402 sp->scc_psmr |= SCU_PSMR_CL;
404 /* Mask all interrupts and remove anything pending.
407 sp->scc_scce = 0xffff;
408 sp->scc_dsr = 0x7e7e;
409 sp->scc_psmr = 0x3000;
411 /* Make the first buffer the only buffer.
413 tbdf->cbd_sc |= BD_SC_WRAP;
414 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
416 /* Enable transmitter/receiver.
418 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
421 static void scc_halt(int scc_index)
423 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
424 volatile cpm8xx_t *cp = &(im->im_cpm);
425 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
427 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
430 static void scc_putc (int scc_index, const char c)
432 volatile cbd_t *tbdf;
434 volatile scc_uart_t *up;
435 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
436 volatile cpm8xx_t *cpmp = &(im->im_cpm);
438 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
440 tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
442 /* Wait for last character to go.
445 buf = (char *) tbdf->cbd_bufaddr;
448 while (tbdf->cbd_sc & BD_SC_READY)
453 tbdf->cbd_datlen = 1;
454 tbdf->cbd_sc |= BD_SC_READY;
457 while (tbdf->cbd_sc & BD_SC_READY)
462 static int scc_getc (int scc_index)
464 volatile cbd_t *rbdf;
465 volatile unsigned char *buf;
466 volatile scc_uart_t *up;
467 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
468 volatile cpm8xx_t *cpmp = &(im->im_cpm);
472 up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
474 rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
476 /* Wait for character to show up.
478 buf = (unsigned char *) rbdf->cbd_bufaddr;
480 while (rbdf->cbd_sc & BD_SC_EMPTY);
482 for (i = 100; i > 0; i--) {
483 if (!(rbdf->cbd_sc & BD_SC_EMPTY))
492 rbdf->cbd_sc |= BD_SC_EMPTY;
501 static int test_ctlr (int ctlr, int index)
504 char test_str[] = "*** UART Test String ***\r\n";
507 ctlr_proc[ctlr].init (index);
509 for (i = 0; i < sizeof (test_str) - 1; i++) {
510 ctlr_proc[ctlr].putc (index, test_str[i]);
511 if (ctlr_proc[ctlr].getc (index) != test_str[i])
518 ctlr_proc[ctlr].halt (index);
521 post_log ("uart %s%d test failed\n",
522 ctlr_name[ctlr], index + 1);
528 int uart_post_test (int flags)
533 ctlr_proc[CTLR_SMC].init = smc_init;
534 ctlr_proc[CTLR_SMC].halt = smc_halt;
535 ctlr_proc[CTLR_SMC].putc = smc_putc;
536 ctlr_proc[CTLR_SMC].getc = smc_getc;
538 ctlr_proc[CTLR_SCC].init = scc_init;
539 ctlr_proc[CTLR_SCC].halt = scc_halt;
540 ctlr_proc[CTLR_SCC].putc = scc_putc;
541 ctlr_proc[CTLR_SCC].getc = scc_getc;
543 for (i = 0; i < CTRL_LIST_SIZE; i++) {
544 if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
549 #if !defined(CONFIG_8xx_CONS_NONE)
550 serial_reinit_all ();
556 #endif /* CONFIG_POST & CONFIG_SYS_POST_UART */